Applying Structure Exchange to Battery Charging to Enhance Light-Load Efficiency

Abstract

A full-bridge DC–DC converter with structure exchange is proposed to simulate battery charging based on an electronic load. The full-bridge phase-shift converter (FBPSC) uses an external resonant inductor and phase-shift control on the primary side to realize zero voltage switching (ZVS) above medium load. However, the energy of the resonant inductor is not enough to carry away the energy of the parasitic capacitance on the switch at light load, leading to the inability of ZVS as well as the circulating current problem due to the long duration of the primary-side circulating current. Consequently, in order to conquer such problems mentioned above, the structure exchange, with only the control strategy changed from the phase-shift control to the two-transistor forward control, is presented to increase the light-load efficiency remarkably. Furthermore, the number of inductors is reduced by using the center-tap structure on the secondary side compared to the current-doubler structure. In addition, the synchronous rectifier on the secondary side is used to further improve the overall efficiency of the converter.

1. Introduction

Recently, environmental problems such as global warming and air pollution caused by fossil fuels have become the focus of global concern. With the increasingly stringent environmental protection regulations and the high price of fossil fuels, how to reduce the use of fossil fuels in order to minimize the heavy burden of high oil prices has become the focus of attention, and therefore, at this stage, the world has begun to seek renewable energy sources, such as solar, biomass, hydro, wind, geothermal, etc., to replace fossil fuels, but renewable energy sources often cannot provide stable power supply due to weather and environmental factors. However, electronic products need a stable and undisturbed DC power source. Consequently, batteries will be an important topic in future research.

Since batteries can be used as stable power sources, they are often employed in various electronic devices, such as cell phones, notebook computers, and other portable electronic products, as well as in electric vehicles, energy storage equipment, and other high-power applications. Accordingly, battery-related technologies, such as charging, discharging, and battery balancing, are very important. In recent years, battery charging has mainly focused on extending battery life and reducing charging time [1,2,3].

With the advances in semiconductor components and power electronics technology, linear power converters are gradually being phased out and replaced by high-frequency switching power supplies, which offer high efficiency, small size, high energy density, and other advantages. Switching power supplies are designed for different load requirements using different topologies. In general, they can be categorized according to the output power [4], as shown in

Table 1. Topology versus output power [4].

Topology	Output Power
Flyback Converter	Below 100 W
Forward Converter	Between 100 W and 500 W
Half-Bridge Converter
Full-Bridge Converter	Above 500 W

.

From Table 1, one can see that if the output power of 500 W or more is to be needed, a full-bridge topology is more suitable. Since the output power specification in this paper is 1 kW, a full-bridge converter is adopted as the main power stage.

Efficiency has always been a concern in switching power supplies. In recent years, they have been increasingly moving toward high-speed switching frequency, and this can effectively reduce the volume of transformers and inductors, but the power semiconductor components will be faced with increased switching losses, increased switching stress, and strong electromagnetic interference (EMI). Therefore, in order to improve efficiency, the resonant switching technology [5] is used to improve the traditional pulse width modulation (PWM) switching technology. The resonant converter, with additional LC circuits used to generate resonance, makes the voltage across or the current through the power switch fall to zero and then turns this switch on or off to realize the ZVS or the ZCS, leading to reducing the switching loss.

In contrast, conventional converters use fast-recovery diodes (FRDs) or Schottky barrier diodes (SBDs) to realize the rectification function. However, these diodes will generate a forward conduction voltage during conduction, resulting in an increase in conduction loss, and this is even more serious in high-current applications. Consequently, the use of a synchronous rectifier (SR) on the secondary side is necessary for the sake of improving the efficiency of the converter [6,7,8]. There are three main gate-driving methods [9,10,11,12], namely, self-excited drive [9,10], current drive [10,11], and voltage drive [12]; the latter is widely employed and can be used with an integrated circuit or a digital controller together with advanced battery charging techniques [13,14,15,16,17] or artificial intelligence (AI)-based control strategies [18,19,20]. Based on the above, the FBPSC with an SR is adopted. As generally acknowledged, the full-bridge phase-shift converter has the characteristic of ZVS turn-on above middle load, but it is not easy to achieve ZVS turn-on at light load, leading to a relatively high switching loss and a relatively large circulating current. That is to say, low efficiency occurs under light loads. The literature [21] adds a power switch, a capacitor, and two diodes, called a CDD circuit, to the center tap of the secondary side to clamp the voltages on the rectifier diodes and hence to reduce the loss created by the reverse recovery current. The literature [22] reduces the power loss in [10] by changing the position of the secondary-side components to decrease the loss generated by the reverse recovery current by reducing one power switch, and at the same time, during the circulating current period, the energy will be transferred to the secondary side for reducing the conduction loss. The literature [23] is used to improve the circulating current problem in [22]; in addition to the CDD circuit on the secondary side, a half-bridge LLC converter is integrated into the full-bridge phase-shift converter, and the LLC converter is used to transfer the energy to the secondary side during the current circulating period. In [24], two symmetrical half-bridge converters are connected in parallel on the primary side, and two transformers are used to increase the resonant inductance to increase the ZVS range, and the secondary-side windings, having a CDD circuit to reduce the reverse recovery current loss, are connected in series. The literature [25] adds two power switches and one resonant inductor to the primary side, and at light load, the controllable switch is used to make the added resonant inductor participate in resonance to provide energy to the rear leg to increase the ZVS range. The literature [26] focuses on light load and adjusts the turn-on time of the rear-leg switches to reduce the voltages on the power switches, thereby making the switches turned on with efficiency improved as well as reducing the voltage stresses on secondary-side diodes. The literature [27] adjusts the blanking time to boost the overall efficiency. The literature [28] uses adaptive control to optimize the blanking time as well as burst mode control for very light loads to elevate the overall efficiency. Based on the above mentioned, upgrading the efficiency or efficiency range by increasing the number of components reduces the reliability of the circuit and raises the cost and complexity of the circuit, whereas enhancing the efficiency by adjusting the blanking time increases control complexity. Therefore, via digital control, this paper adopts the structure exchange strategy of switching from phase-shift topology to two-transistor forward topology at light load, which solves the primary-side circulating current problem without additional components to improve the light-load efficiency remarkably. In addition, the SR technique is incorporated to further promote overall efficiency.

As for battery charging, there are five charging methods for batteries, and each charging method will correspond to different applications in order to accelerate the charging speed and prolong the battery life. Nowadays, the commonly used charging methods for batteries can be categorized into five types: (1) constant-voltage (CV) charging [29]; (2) constant-current (CC) charging [30]; (3) CC/CV charging [31]; (4) pulse charging [32]; and (5) reflex charging [33]. Constant-voltage charging is suitable for secondary batteries with small capacity because this charging method has a maximum output current limitation, and when the output current is greater than the load range, the output voltage cannot be maintained. In addition, the battery life will be affected by the excessive current at low voltage, and constant-current charging will leave the battery in an undercharged state due to the internal resistance of the battery. This method uses a pulse current to provide a rest period for the battery to spread the battery fluid evenly to extend the battery life, while the reflex charging method is based on the pulse charging method, and the circuit is designed in a bidirectional way so that the battery can be discharged during the rest period to eliminate the bubbles generated during charging. Compared with the pulse charging method, the reflex charging method is more expensive and has a shorter life cycle, so it is less commonly used. The CC/CV charging method is the most common charging method. Accordingly, the proposed circuit with the corresponding control strategy is verified by the electronic load under the CC and voltage modes to simulate CC and CV charging.

In this paper, the dSPIC33EP16GS502 (Microchip Technology Inc., Chandler, AZ, USA) is used as the control kernel of the charger, which is designed based on the LiFePO₄ 40152S specifications with a capacity of 15 Ah, an input voltage of 380 V, an output voltage of 58.4 V, a maximum output current of 17 A, and a CC/CV charging mode. In CC mode, the output current is stabilized at 17 A, whereas in CV mode, when the output current is above 30% of the rated load, a full-bridge phase-shift structure is used, which has a ZVS characteristic to reduce the switching loss of the power switches and improve efficiency. When the output current is below 30% of the rated load, the output is converted to a two-transistor forward structure, which exacerbates the circulating current problem but increases the efficiency at light load. Additionally, since the rated load output is 17 A, an SR is added to the secondary side to further improve the efficiency.

This paper is divided into six sections. Section 1 reviews existing techniques and proposes the control strategy; Section 2 describes the proposed structure exchange; Section 3 provides the system and component specifications; Section 4 explains the program flowchart; Section 5 presents the experimental results; and Section 6 concludes the paper.

2. Operating Principle of Structure Exchange

In this section, the method to realize structure exchange is described; however, the basic operating principles of the full-bridge phase-shift circuit and the two-transistor forward converter are omitted.

2.1. Circuit Symbol Definitions and Assumptions

Figure 1 shows the main power stage with structure exchange and synchronous rectification. This circuit has four power switches, S₁–S₄, on the primary side, and two power switches, S₅ and S₆, on the secondary side; an output inductor L_o and an output capacitor C_o; six power diodes, D₁–D₆, are the body diodes for the individual power switches; a resonant inductor L_r, which is composed of the leakage inductance of the main transformer and the external inductance; and a resonant capacitor C_r, which is composed of the output capacitances of the power switches and is resonated with the resonant inductor L_r to achieve the goal of ZVS.

Before proceeding to the explanation of the proposed structure exchange, the following definitions and assumptions are given:

(1)

V_in, V_o, i_in, and i_o are the input voltage, the output voltage, the input current, and the output current, respectively;

(2)

V_AB is the voltage across the primary transformer;

(3)

I_p is the current of the primary transformer;

(4)

i_Lo is the current of the output inductor;

(5)

T_s is the switching period, and f_s is the switching frequency;

(6)

D and D_eff denote the duty cycle and the effective duty cycle, respectively;

(7)

N_p and N_s represent the number of coils on the primary side and the number of coils on the secondary side, respectively;

(8)

The output capacitances of the power switches, called C_oss1, C_oss2, C_oss3, and C_oss4, are all equal;

(9)

The output capacitances are not considered for the secondary-side power switches;

(10)

Since the resonant time is comparatively short, the resonant current can be considered linear as a result.

2.2. FBPSS Transferred to Two-Switch Forward Structure (TSFS)

This section describes the process of converting the FBPSS transferred to the TSFS. Figure 2 shows its key waveforms.

State 1 [t₀ ≤ t ≤ t₁]: In this state, the switches S₁, S₄, and S₆ are on, and the voltage across terminals A and B is v_AB is V_in. Figure 3 shows the current flow in this state for FBPSS transferred to TSFS. From Figure 3, one can see that the resonant inductor L_r and the magnetizing inductance of the main transformer are magnetized, while the main transformer transfers energy to the secondary side, and the output inductor L_o is magnetized. In addition, the secondary-side diode D₅ is cut off due to reverse bias, and the secondary-side current flows through the switch S₆, the output inductor L_o, and the output capacitor C_o to form a current loop. Until t₁, the switches S₁, S₄, and S₆ are cut off, and the circuit enters the next state.

State 2 [t₁ ≤ t ≤ t₂]: As shown in Figure 4, the switches S₁, S₄, and S₆ are cut off. As a result, the voltage across terminals A and B is v_AB is −V_in. During this state, the resonant inductor L_r and the magnetizing inductance of the main transformer are demagnetized, and the main transformer transfers energy to the secondary side through the body diodes D₂ and D₃. At the same time, not only the secondary-side body diode D₆ conducts due to the continuous current of the output inductor L_o but also the secondary-side body diode D₅ due to the reverse bias. Until the resonant inductor L_r is fully demagnetized, the circuit enters the next state.

State 3 [t₂ ≤ t ≤ t₃]: In this state, the switches S₁, S₄, and S₆ are still cut off, and the voltage across terminals A and B is v_AB is zero. Figure 5 shows the current flow in state 3 for FBPSS transferred to TSFS. During this state, not only the resonant inductor L_r has been fully demagnetized but also the output inductor L_o continues to be demagnetized. At the same time, since there is no voltage across the primary side of the transformer, the secondary-side current i_p flows through the output inductor L_o, the output capacitor C_o, and the body diodes D₅ and D₆ to form a current loop.

State 4 [t₃ ≤ t ≤ t₄]: As shown in Figure 6, the switches S₁, S₄, and S₆ are still cut off, and the voltage between terminals A and B is v_AB is zero. During this state, the output inductor L_o has been fully demagnetized, and the energy of load is provided by the output capacitor C_o. After this state, the circuit enters the two-transistor forward structure.

2.3. TSFS Transferred to FBPSS

This section describes the process of converting the TSFS transferred to the FBPSS. Figure 7 shows its key waveforms.

State 1 [t₀ ≤ t ≤ t₁]: As shown in Figure 8, the switches S₂, S₃, and S₅ are on, and the voltage across terminals A and B is v_AB is −V_in. From Figure 8, one can know that the resonant inductor L_r and the magnetizing inductance of the main transformer are demagnetized in the opposite direction, while the energy of the main transformer is transferred to the secondary side and the output inductor L_o is magnetized. At the same time, the secondary-side current flows through the output inductor L_o, the output capacitor C_o, and the switch S₅ to form a current loop.

State 2 [t₁ ≤ t ≤ t₂]: As shown in Figure 9, S₂, S₃, and S₅ are still cut off, and the voltage across terminals A and B is v_AB is −V_in. During this state, the resonant inductor L_r and the magnetizing inductance of the main transformer are magnetized in the opposite direction, and the main transformer transfers energy to the secondary side through the body diodes D₁ and D₄. At the same time, the secondary-side body diode D₅ conducts due to the continuous current of the output inductor L_o, and the secondary-side body diode D₆ cuts off due to the reverse bias. Until the current in the resonant inductor L_r is zero, the circuit enters the next state. The equations of the voltage v_AB and the currents i_Lo and i_p are shown below.

State 3 [t₂ ≤ t ≤ t₃]: As shown in Figure 10, the switches S₂, S₃, and S₅ are still cut off, and the voltage across terminals A and B is v_AB is zero. Simultaneously, the secondary-side current flows through the output inductor L_o, the output capacitor C_o, and the body diodes D₅ and D₆ to form a current loop.

State 4 [t₃ ≤ t ≤ t₄]: As shown in Figure 11, the switches S₁, S₄, and S₆ are still cut off, and the voltage across terminals A and B is v_AB is zero. During this state, the current in the output inductor L_o is zero, and the energy needed by the load is provided by the output capacitor C_o. After this state, the circuit enters the full-bridge phase-shift structure.

3. Design Considerations

This section describes the circuit design, including the given system specifications and the component specifications used.

3.1. System Configuration

Figure 12 shows the proposed system configuration, which consists of two types of circuits: the main circuit and the feedback control circuit. As shown in Figure 12, the main circuit is a full-bridge phase-shift circuit with synchronous rectification. In terms of the feedback control circuit, a current sensor and a voltage divider are used to detect the output voltage and current signals, which are then sent to the analog-to-digital converter (ADC 0 and ADC 1) inside the digital signal processor (DSP) to obtain the individual digital signals, and then the corresponding control forces are obtained by the algorithm to generate PWM signals to regulate the power switches so as to obtain the required output voltage and current.

3.2. System Specifications

Table 2. System specifications.

Rated Input Voltage (Vin)	380 V
Rated Input Voltage (Vo)	58.4 V
Rated Output Current (Io,rated)	17 A
Minimum Output Current (Io,min)	1.7 A
Output Power (Po)	1 kW
Switching Frequency (fs)	100 kHz

shows the system specifications, from which the required main component parameters of the circuit can be designed and summarized in

Table 3. Component specifications used.

Component	Specification
SiC FET Switches S1, S2, S3, S4	UJ3C065080T3S
SR MOSFET Switches S5, S6	IPP200N25N3G
Resonant Capacitor	488 µF
Resonant Inductor	60.4 µH
Additional Resonant Inductor Lext	48.2 µH
Output Inductor Lo	51.4 µH
Output Capacitor Co	660 µF/63 V

.

3.3. Design of Resonant Capacitor and Inductor

In order to achieve ZVS of the power switches on the primary side, the resonant inductor should resonate with the parasitic capacitance, and the energy should be large enough to convince the power switches to zero before they turn on to complete ZVS.

$${\displaystyle \frac{L_r\times I_p^2}{2}}\ge {\displaystyle \frac{C_r\times V_{in}^2}{2}}$$

(1)

where C_r is the sum of the parasitic capacitance of the power switch, C_oss, and the stray capacitance of the transformer XFMR, C_XFMR.

Accordingly, the resonant capacitor C_r can be expressed as

$$C_r=2\times C_{oss}+C_{XFMR}$$

(2)

Since the value of C_oss can be obtained to be 176 pF from the corresponding datasheet, and the value of C_XFMR can be measured to be about 136 pF, substituting these values into (2) yields

$$C_r=2\times 176+136=488 \mathrm{pF}$$

(3)

From (1), it can be seen that the resonance condition depends on the current I_p. Since the value of I_p is set at 30% of the load current, the corresponding value is

$$\begin{array}{l}{I}_p=0.3\times {\displaystyle \frac{N_s}{N_p}}\times I_{Lo}\\ =0.3\times {\displaystyle \frac{7}{33}}\times 17\\ =1.08 \mathrm{A}\end{array}$$

(4)

Substituting (3) and (4) into (1) yields

$$\begin{array}{l}{L}_r\ge {\displaystyle \frac{C_r\times V_{in}^2}{I_p^2}}={\displaystyle \frac{488\times {380}^2}{{1.08}^2}}\times {10}^{-12}\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} =60.4 \mathsf{\mu }\mathrm{H}\end{array}$$

(5)

The value of the resonant inductor L_r includes the primary-side leakage inductance L_lk and the required external resonant inductance L_ext. Since the value of L_lk can be measured to be 12.2 µH, the required primary-side external resonant inductance L_ext can be calculated to be

$$\begin{array}{l} L_r=L_{lk}+L_{ext}\\ \Rightarrow L_{ext}=L_r-L_{lk}\\ =60.4 \mathsf{\mu }\mathrm{H}-12.2 \mathsf{\mu }\mathrm{H}\\ =48.2 \mathsf{\mu }\mathrm{H}\end{array}$$

(6)

4. Control Program Flowchart

In this paper, a DSP is used as the control kernel, whose model name is dsPIC33EP16GS502, manufactured by Microchip Technology Inc. (Chandler, AZ, USA), and the C language is used to realize the required functions. The dsPIC33EP16GS502 has a 7.37 MHz oscillator, four high-speed PWMs, 12-bit analog-to-digital converters, a 12-bit digital-to-analog converter, flash memory of 16 kB, and 2 kB of random-access memory (RAM).

4.1. Main Program Flowchart

The main program flowchart is shown in Figure 13. The analog signals are sampled by triggering the analog-to-digital converters ADC0 and ADC1, converted to digital data, and then the errors are generated by subtracting these digital data from the target values and sent to the PI control module to obtain the required control forces that are sent the PWM module to obtain the corresponding gate-driving signals for the switches.

4.2. ADC Module

Figure 14 shows the flowchart of ADC. The ADC0 sampling and calculation and the ADC1 sampling and calculation are responsible for sampling the output voltage V_o and the output current I_o, respectively, which are triggered by the PWM1 signal to achieve the sampling purpose. After this, subtracting the voltage feedback signal v_fb and the current feedback signal i_fb from the voltage command v_ref and the current command i_ref, respectively, yields the error values V_Error and I_Error, which are finally sent to the PI module.

In order for the converter output voltage and current signals to be input to the digital controller, these signals need to be processed by the ADC module to convert them to digital signals. This DSP has a built-in 12-bit ADC, whose value is from 0 to 4095 in the decimal system. Since the acceptable voltage range of the ADC is 3.3 V, the output voltage and current commands are given in (7) and (8) as follows:

$$\mathrm{The} \mathrm{output} \mathrm{voltage} \mathrm{command}=4096\times {\displaystyle \frac{v_{ref}}{3.3}}$$

(7)

$$\mathrm{The} \mathrm{output} \mathrm{current} \mathrm{command}=4096\times {\displaystyle \frac{i_{ref}}{3.3}}$$

(8)

4.3. PI Module

Figure 15 shows the flowchart of the PI module, in which there are two gains of P (proportional gain) and I (integral gain) to control the output voltage and current, respectively. The proportional control forces P_v and P_i can be ob99++tained by multiplying the resulting voltage error V_Error and current error I_Error by the coefficients V_kp and I_kp, respectively. The integral control forces I_v and I_i can be obtained by multiplying the resulting voltage error V_Error and current error I_Error by the coefficients V_ki and I_ki, respectively, and adding with the previous integral control forces. Eventually, the voltage control force CF_v can be obtained by adding P_v and I_v, whereas the current control force CF_i can be obtained by adding P_i and I_i. Under constant current control, the full-bridge phase-shifted topology will be operated, and the current control force will be used to regulate the phase. Under constant-voltage control, the current is detected, and if this detected current is above the switching point value, the system will operate in the full-bridge phase-shift structure, with the phase regulated by the voltage control force. Conversely, if the detected current is below the switching point value, the system will operate in the two-transistor structure, and the voltage control force is used to regulate the duty cycle. In order to prevent the system from going out of control, it is necessary to add the minimum control force and the maximum control force to limit the duty cycle, and finally, the resulting control force is fed into the PWM module.

4.4. PWM Module

The PWM of the DSP is 16-bit, and the PWM control is realized by setting the PWM-related registers. The related registers are duty cycle, frequency, phase, blanking time, complementary relationship, etc., which can be set so the value of the control force CF can be directly fed into the registers related to the duty cycle. The full-bridge phase-shift structure requires three PWMs, and one PWM has two PWM outputs; the signal of the front leg is generated by PWM1, the signal of the rear leg is generated by PWM2, and the signal of the SR is generated by PWM3. The frequencies of PWM1, PWM2, and PWM3 are set to 100 kHz, and the blanking times are set to 300 ns to avoid damage to the switches due to turn-on of the switches on the same leg.

5. Experimental Results

To verify the parameters of the circuit shown in Table 2 and Table 3, an electronics load (3255, Prodigit Electronics Co., Ltd., Taiwan) and a DC power supply (PSW80-27, GW Instek., Taiwan) will be used to provide the load input and voltage. As a result, one can measure the waveforms, and afterward, the measured waveforms will be explained.

5.1. Measured Waveforms Under Constant Current at 40 V and 17 A for FBPSS

Figure 16 shows the waveforms of gate-driving signals v_gs1 for switch S₁, v_gs2 for S₂, v_gs3 for switch S₃, and v_gs4 for switch S₄. Figure 17 shows the waveforms of the gate-driving signals v_gs1 for switch S₁, v_gs4 for switch S₄, and v_gs6 for switch S₆. Figure 18 shows the gate-driving signals v_gs2 for switch S₂, v_gs3 for switch S₃, and v_gs5 for switch S₅. Figure 19 shows the waveforms of the primary-side voltage between points A and B, called v_AB, primary-side current i_p, the output voltage V_o, and the output current I_o. Figure 20 shows the waveforms of the gate-driving signal v_gs1 for switch S₁ and the voltage v_ds1 for switch S₁. Figure 21 shows the waveforms of the gate-driving signal v_gs2 for switch S₂ and the voltage v_ds2 for switch S₂. Figure 22 shows the waveforms of the gate-driving signal v_gs3 for switch S₃ and the voltage v_ds3 for switch S₃. Figure 23 shows the gate-driving signal v_gs4 for switch S₄ and the voltage v_ds4 for switch S₄. From Figure 16, Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22 and Figure 23, one can see that all switches at rated load have ZVS turn-on.

5.2. Measured Waveforms Under Constant Voltage at 58.4 V and 1.7 A for TSFS

Figure 24 shows the waveforms of the gate-driving signals v_gs1 for switch S₁, v_gs2 for S₂, v_gs3 for switch S₃, and v_gs4 for switch S₄. Figure 25 shows the gate-driving signals v_gs1 for switch S₁, v_gs4 for switch S₄, and v_gs6 for switch S₆. Figure 26 shows the gate-driving signals v_gs2 for switch S₂, v_gs3 for switch S₃, and v_gs5 for switch S₅. Figure 27 shows the waveforms of the primary-side voltage between points A and B, called v_AB, the output voltage V_o, the primary-side current i_p, the output current I_o, and the voltage v_ds3 for switch S₃. From Figure 24, Figure 25, Figure 26 and Figure 27, one can see that when the switch is turned off, the resonant inductor resonates with the body capacitance of the switch, resulting in oscillations in the primary-side voltage and current.

5.3. Measured Waveforms for Transferring FBPSS to TSFS

Figure 28 shows the waveforms of the voltage across points A and B on the primary side, v_AB, the primary-side current i_p, the output voltage V_o, and the output current I_o when the FBPSS is converted to the TSFS.

5.4. Measured Waveforms for Transferring TSFS to FBPSS

Figure 29 shows the waveforms of the voltage across points A and B on the primary side, v_AB, the primary-side current i_p, the output voltage V_o, and the output current I_o when the TSFS is converted to the FBPSS.

From Figure 28 and Figure 29, one can see that because of the larger output capacitance used, there are no significant spikes in output voltage and output current in the structure conversion process.

5.5. Efficiency Measurement

In this section, the efficiency of battery charging is measured in different modes of the converter. A digital meter is adopted to measure the input and output voltages, and a current-sensing resistor is used and connected in series with the input and output current. In addition, the digital meter is not only used to measure the voltage across the current-sensing resistor to find out the values of the input and output currents but also the input and output powers. At the same time, a DC electronic load is used to simulate the behavior of the battery on the load side. Finally, the actual circuit efficiency is calculated. Figure 30 shows the curves of the efficiency measurement of the full-bridge phase-shift structure and two-switch flyback structure in constant-voltage mode. From Figure 30, one can see that the converter is switched to the two-switch forward structure under constant voltage, and the efficiency below 30% of the rated load can be improved by up to 7.1% compared to the full-bridge phase-shift structure. Figure 31 shows the curve of efficiency measurement of the full-bridge phase-shift structure under constant current. From Figure 31, it can be seen that the efficiency rises slightly as the output voltage increases.

5.6. Comparison Between the Proposed Converter and Other Topologies

Comparisons of the proposed converter with topologies operated as battery chargers [6,7,13,14,15,16,28] based on various criteria and features are presented in

Table 4. Comparisons between the proposed converter and existing topologies.

		[6]	[7]	[13]	[14]	[15]	[16]	[28]	Proposed
Circuit Structure		Full-Bridge + SR	Full-Bridge + SR	Full-Bridge + Resonant Tank+ Full-Bridge Rectifier	Dual-Boost	Full-Bridge + Resonant Tank+ Full-Bridge Converter	DAHB+ Buck-Boost	Half-Bridge + Resonant Tank+ Full-Bridge Rectifier	Full-Bridge + Two-Switches
Rated-load Power (W)		1176	---	1100	37	3700	1000	2000	1000
Output Voltage (V)		75	24	110	15	630	400	0	58.4
Switching Frequency (kHz)		300	200	55	20	130	---	28	100
Switches		GaN Transistor	Mosfet	Mosfet	Mosfet	Mosfet	Mosfet	IGBT	SiC FET
Light-load Power (W)		120	---	100	6.2	370	50	---	100
Light-load Power Ratio (%)		10.0	40.0	9.1	16.76	10.0	5.0	---	10.0
Light-load Efficiency (%)		91.8	88.1	91.2	91.3	92.5	77.3	88.9	92.4
Control Strategy		Phase-Shift	Phase-Shift	LLC Resonant	PWM	Adaptive-Frequency	PWM	Phase-Shift	Phase-Shift + Structure Exchange
Isolation		v	v	x	x	v	x	v	v

. From this table, the proposed converter possesses the highest light-load efficiency.

6. Conclusions

In this paper, a full-bridge DC–DC converter with structure exchange is applied to battery charging. The full-bridge phase-shift converter uses an external resonant inductor and phase-shift control on the primary side to achieve ZVS above medium load. However, the energy of the resonant inductor is not so enough to carry away the energy of the parasitic capacitance on the switch at light load, resulting in the inability of ZVS as well as the circulating current problem existed by the long duration of the primary-side circulating current time. Therefore, to solve these problems, the structure exchange, with only the control strategy changed from the phase-shift control to the two-switch forward control, is adopted to enhance the light-load efficiency significantly. Compared to the conventional BFPSS, the light-load efficiency of this converter can be increased by up to 7.1%.