Time-Domain Fault Detection and Location Scheme for Flexible DC Distribution Networks

Abstract

Accurately detecting and locating the fault point of the DC line is significant for eliminating the fault and restoring the power supply of the flexible DC distribution network as soon as possible. Firstly, a direction pilot protection scheme for a complex DC distribution network is proposed based on the integral of the current superposition to identify the fault direction. Then, an online time-domain fault location method based on the least square (LS) method to solve the overdetermined equations is proposed by analyzing the fault loop circuit after the DC line fault. The proposed location scheme utilizes fault data at both ends of the line to eliminate the theoretical impact of fault resistance, and the calculation of the current difference method is discussed to reduce the location error of whether the fault current-limiting reactor (CLR) exists. Finally, various simulations by PSCAD/EMTDC V4.5 demonstrate that the proposed scheme has high protection reliability and location results after different fault positions and resistances. The proposed scheme has low requirements for the sampling rate, fault data length, and implementation costs, which can meet practical application requirements.

1. Introduction

With the significant progress of power semiconductor devices and the rapid development of DC loads, distributed generation (DG), energy storage systems, etc., DC distribution networks or DC microgrids have advantages, such as high transmission capacity, large power supply radius, more suitable access to DGs, excellent power quality, and low line losses [1,2,3]. Protection technology, as a bottleneck in the application of DC distribution, is still in the theoretical research stage [4,5]. When a DC line malfunctions, to quickly eliminate the fault and restore the power supply, it is important to detect and locate the fault point accurately [6].

On the one hand, although single-ended fault detection schemes, such as overcurrent protection (O/C), low-voltage protection (Under-voltage), and current direction, can meet the requirements of fault protection for speed response, they are difficult to ensure selectivity, have low reliability, and cannot detect high-resistance ground faults [4,7]. Usually in DC networks, to limit the rapid rise of short-circuit currents, current-limiting reactors (CLRs) are connected in series on both ends of the DC line. The CLRs can play a role in smoothing fault signals and forming the boundary of protection. Therefore, the voltage change rate-based protection method can accelerate the speed and sensitivity of fault detection. Reference [8] employs the frequency domain impedance to detect the DC faults in DC distribution grids. The single-ended method can accelerate the speed of fault protection without relying on communication systems and has a simple principle. However, in complex flexible DC distribution networks, the reliability and selectivity of protection are insufficient. References [9,10,11,12,13] study the application of communication-based current differential protection in DC distribution systems. Reference [12] proposes a pilot protection scheme that utilizes the direction of current at both ends of the line. In the case of high-resistance faults, the amplitude of the fault current is small, and there are limitations to current differential protection and current direction pilot protection. To solve the problem of identifying high-resistance faults, Reference [13] adopts a pilot protection scheme with current superposition, but it is hard to ensure reliability by only comparing the directional information at a certain moment.

On the other hand, the DC cable lines are mostly buried underground, and time-consuming and labor-intensive manual line inspection makes it difficult to detect the fault point. Moreover, since DC circuit breakers (DCCBs) will quickly cutoff faulty lines, the length of data available for fault location is limited, which increases the difficulty of online fault location. The distance between DC distribution lines is relatively short. Using the traditional traveling-wave fault location method may require a higher sampling rate to ensure distance accuracy, which is costly, and it is difficult to eliminate interference from multiple reflections in complex networks.

At present, the fault location of DC distribution lines can be divided into two categories. The first type is the injection signal method. References [14,15,16] use a probe power unit (PPU) to inject signals for fault location. Its essence is to input a capacitor bank with initial voltage to form RCL second-order attenuation oscillation in the fault circuit and extract oscillation information through algorithms, such as FFT [14] and Prony [15,16], to calculate the fault distance. Reference [16] equates cable lines to π models, adopts the concept of apparent pseudo-impedance, and uses the Prony algorithm to extract attenuation oscillation parameters. The above injection signal method is used for fault location after the completion of DCCB operation, which requires additional distance-measuring devices and increases the cost of fault location.

The second type is online fault location methods. Reference [17] uses a discrete median filter and mathematical morphology to design a diagnosis scheme for DC distribution systems. Reference [18] establishes the circuit equations for the discharge stages of the capacitors at both ends of the line and eliminates the influence of fault resistance to calculate the fault distance. However, the above method does not regard the influence of adjacent lines and is only applicable to point-to-point DC lines. Reference [19] utilizes the Hausdorff distance and cubic spline interpolation to locate the fault, but a higher sampling rate is required to ensure location accuracy. Reference [20] obtains two independent equations from two different measurement values at different time points after a DC line short-circuit fault and solves the fault circuit parameters for fault location. However, it does not apply to single-pole grounding faults. References [21,22,23,24] use a series of measurement data after a fault to calculate the reactance between the protection measurement point and the fault point by solving the pseudo-inverse matrix, thereby calculating the fault distance. However, the influence of distributed capacitance is not considered, and only fault data from one end are utilized, which cannot eliminate the influence of multiple power sources and are only applicable to radial networks.

To accurately detect and locate the fault point, this paper first proposes a direction pilot protection scheme suitable for complex DC distribution networks in Section 2. Secondly, based on the analysis of the state equation of the fault circuit, an online fault location scheme is proposed, and the current difference calculation problem is discussed regarding whether the CLR exists or not in Section 3. Finally, the performance of the proposed fault detection and fault location scheme is verified through PSCAD/EMTDC in Section 4. Conclusions are drawn in Section 5. The proposed scheme is suitable for complex DC networks and has high reliability and accuracy under different fault resistances and locations.

2. Fault Detection for Flexible DC Networks

In response to the limitations of existing fault detection schemes for DC distribution networks, especially in complex mesh DC distribution grids, this paper proposes a fault detection scheme suitable for complex mesh DC distribution networks. The protection station’s intelligent electronic devices (IEDs) collect each outgoing line’s current in real time at a lower sampling rate (such as 5 kHz) and communicate data with adjacent stations. The protection schematic is shown in Figure 1, where DC buses A and B have n and m feeders, respectively, line AB is the DC line connecting DC buses A and B, i₁ and i₂ are the collection currents of IED A and B by current sensors, and f is the fault point. Once the IED detects a DC line fault, the IED will send an action command to DCCB to cutoff the faulty line.

This fault detection scheme is based on data communication, and due to the short distance of the DC distribution network, communication delay can be accepted to a certain extent [10,11]. If the system requires a high speed of protection, it would be used as a backup protection scheme.

To distinguish between normal and disturbance situations, the current change is used to detect disturbances, and the start-up criterion is as follows:

$$\Delta i_{nm}(k)={\displaystyle \sum _{n=0}^{M-1}\left|i_{mn}(k-M+n+1)-i_{mn}(k-M+n)\right|}>\mathsf{\Lambda }$$

(1)

where i_mn is the DC flowing from the DC bus m along the DC line to the DC bus n, k is the corresponding sampling point, the current reference direction is the direction of the bus flowing toward the line by default, M is the data length for the start-up criterion, and Λ is the set threshold value. To detect most grounding fault disturbances (more than 100 Ω fault resistance) under a 10 kHz sampling rate of a 10 kV DC system, the optimal values for case studies in this paper were set as M = 3 and Λ = 20 A. When the starting criterion was met, subsequent protection actions were taken.

The integral of the current superposition can be expressed discretely as follows:

$$S_{nm}={\displaystyle \sum _{j=0}^{N-1}(i_{nm}(k+j)-i^{\mathrm{pre}}})$$

(2)

where i^pre is the steady-state current, which can be expressed as i^pre = i(k − P). In this paper, P = 5 was adopted for the case study according to our large number simulation, and the data calculation length was N = 8 after taking into account both the reliability and computational speed. The fault direction can be determined by integrating the positive and negative values of the current superposition, and the criterion is as follows:

$$\left\{\begin{array}{c}{S}_{nm}>k_1,\mathrm{forward} \mathrm{fault}\\ S_{nm}\le k_1,\mathrm{reverse}\mathrm{fault}\mathrm{or}\mathrm{healthy}\end{array}\right.$$

(3)

where k₁ is the reliability coefficient, which was set as 0.1 in this paper.

The flowchart of the proposed direction pilot protection scheme is depicted in Figure 2. The signal measurement point (SMP), R_nm, samples the pole current at time k in real time and determines whether the starting criterion is met. If it does not meet the requirements, the next data point is sampled.

After meeting the startup criteria, the integral value, S_nm, of the current superposition at the k-sampling time is calculated. A label symbol, f_nm, is used to determine whether it is a positive-direction fault. The label symbol, f_nm, and fault sampling time, k, are transmitted to the SMP, R_mn. The protection setting method of the SMP, R_mn, on the other end is similar to the local R_nm.

After obtaining the positive direction fault, f_nm = 1, R_nm receives the signal, f_mn, and corresponding time, k′, sent by the other end R_mn and determines whether the difference between k and k′ is greater than a set value k₂. This criterion is mainly to avoid mis-operation caused by long waiting times. The value of k₂ is greater than the maximum communication delay and multiplied by a reliability coefficient.

It is worth noting that the data at both terminals do not need to be strictly synchronized (general Beidou or GPS satellite synchronization is required).

3. Principle of Fault Location Scheme

The following sections will introduce the principle of online fault location and study the fault circuits after the pole-to-ground (PTG) fault and pole-to-pole (PTP) fault to locate the fault point, mainly discussing the existence and absence of CLRs at both ends of DC lines.

3.1. DC Lines without CLRs

When there are no series CLRs at either end of the line, the line model is equivalent to a π-type model. Because the equivalent capacitance of the parallel connection of the DC side of the converter is much larger than the line’s distributed capacitance, the line terminal’s distributed capacitance can be ignored. Therefore, the equivalent fault circuit of a PTG fault can be obtained, as depicted in Figure 3.

In Figure 3, u₁ and i₁ indicate the voltage and current measured at A terminal, u₂ and i₂ denote the voltage and current measured at B terminal, R₁ and L₁ represent the equivalent line resistance and reactance from A to the fault point, f, R₂ and L₂ represent the equivalent line resistance and reactance from B to f, C_f is the equivalent line capacitance at f, and R_f is the fault resistance. In Figure 3, according to Kirchhoff’s voltage law (KVL), it can be obtained as follows:

$$u_1=R_1{i}_1+L_1{\displaystyle \frac{d{i}_1}{dt}}+u_f$$

(4)

where u_f is the voltage at f. If it is assumed that the equivalent impedance of C_f during the fault transient process is x_c, then u_f can be expressed as [19]:

$$u_f={\displaystyle \frac{1}{C_f}}{\displaystyle \int i_C\mathrm{d}t}={\displaystyle \frac{1}{C_f}}{\displaystyle \int \frac{R_f}{R_f+x_c}{i}_3\mathrm{d}t}$$

(5)

where i₃ = i₁ + i₂. Generally, after a period of fault, the frequency of transient current i₃ will decrease, and u_f is mainly related to R_f. Due to the need for differential calculation in the equation and the fact that the transient fault current is a high change rate nonlinear signal, Reference [24] approximates its differentiation using the difference between two points at time k and k + 1, which can result in significant computational errors. To eliminate this error as much as possible, this paper takes the difference between the previous sampling point and the subsequent sampling point at time k, and obtains:

$${\displaystyle \frac{d{i}_1}{dt}}(k)={\displaystyle \frac{i_1(k+1)+i_1(k-1)}{2\Delta t}}$$

(6)

and

$${\displaystyle \int i_3(k)\mathrm{d}t=}\left(i_3(k)+i_3(k+1)\right)\cdot \Delta t/2$$

(7)

where k denotes the k-th sampling point after the fault, and Δt is the sampling interval. After the fault, starting from the k-th sampling point, the equations are valid, and the equations can be organized and represented in matrix form, as follows:

$$\mathit{V}=\mathit{U}\times \left[\begin{array}{c}{R}_1\\ L_1\\ x_c{R}_f/(x_c+R_f)\end{array}\right]$$

(8)

where $\mathit{U}=\left[\begin{array}{ccc}{i}_1(k)& {\displaystyle \frac{d{i}_1}{dt}}(k)& i_3(k)\\ i_1(k+1)& {\displaystyle \frac{d{i}_1}{dt}}(k+1)& i_3(k+1)\\ \dots & \dots & \dots \\ i_1(k+N)& {\displaystyle \frac{d{i}_1}{dt}}(k+N)& i_3(k+N)\end{array}\right]$, $\mathit{V}=\left[\begin{array}{c}{u}_1(k)\\ u_1(k+1)\\ \dots \\ u_1(k+N)\end{array}\right]$, and N is the total number of sampling points after the k-th sampling point. The equation is an overdetermined equation, which can be solved by solving a pseudo-inverse matrix. Essentially, it is the least square (LS) problem for solving overdetermined systems of equations [17,18,19]. By solving the equation, we can obtain:

$$\left[\begin{array}{c}{R}_1\\ L_1\\ x_c{R}_f/(x_c+R_f)\end{array}\right]=({\mathit{U}}^{\mathrm{T}}\mathit{U}{)}^{-1}{\mathit{U}}^{\mathrm{T}}\mathit{V}$$

(9)

Based on the above analysis, the line parameters between terminal A and f can be obtained. When the line parameter information is known, the fault distance can be determined by the proportional relationship between the obtained parameters and the line parameter information. In some cases, the parameter information of the circuit may be unknown, and in this case, the fault distance is calculated by the ratio of the parameters measured at both ends. This paper calculates the fault distance by the proportion of the line reactance obtained from both ends, which is expressed as:

$$x_1={\displaystyle \frac{L_1}{L_1+L_2}}{L}_{AB}$$

(10)

where x₁ is the distance from terminal A to f, L₁ is the measured line reactance at end A, L₂ is the measured line reactance at end B, and L_AB is the total length of line AB.

3.2. DC Lines with CLRs

When installing CLRs at both ends of a DC line, the line is equivalent to a π-type model. Due to the barrier of the CLR, the distributed capacitance of the equivalent line at the line terminal cannot be ignored. The high-frequency transient signals will be generated, resulting in a PTG fault-equivalent circuit, as shown in Figure 4.

According to the relationship between the current and voltage changes on the inductance, the differential calculation of the line current can be obtained by calculating the voltage on the CLR, further eliminating the error in differential calculation. The current differential at sampling point k can be expressed as:

$${\displaystyle \frac{d{i}_1}{dt}}(k)={\displaystyle \frac{u_L(k)}{L_{dc}}}$$

(11)

where L_dc is the size of the CLR, and u_L is the voltage of the CLR. By substituting the Equation (6) into the Equation (11), the parameter information of the faulty circuit can be obtained, thereby obtaining the fault distance. However, due to the presence of current-limiting reactors, the equivalent capacitors C₁ and C₂ at the line ports can lead to high-frequency transient processes in fault voltage and current, resulting in significant errors. Therefore, it is significant to filter the measured fault voltage and current signals to eliminate high-frequency transient signals. This paper utilized a low-pass Butterworth digital filter to filter the measured signal and then used the equation to solve the overdetermined equation system to obtain the fault circuit parameters, thereby obtaining the fault distance.

3.3. Design of Online Fault Location Scheme

The above analysis took the PTG fault as an example, which also applies to PTP faults. For PTP faults, it is necessary to convert the PTG voltages into the PTP voltages, while the rest of the process is similar. The entire fault location process is as follows:

(a)

After satisfying criterion Equation (1), record the fault current data at a higher sampling rate (such as 10 kHz).

(b)

After the faulty line is cutoff, the local IED sends fault-recording data to the opposite end of the faulty line IED’ and receives the recording data sent by IED’. The length of the recorded data starts from fault detection to DCCB, cutting off the faulty line.

(c)

Calculate the parameters of the fault circuit. If there is no CLR, calculate the fault circuit parameters through Equations (6) and (9). If CLR is installed, perform low-pass filtering first, then calculate the fault circuit parameters using Equations (9) and (11).

(d)

Calculate the fault distance. If the line parameters are known, the fault distance can be directly calculated. If the line parameters are unknown, the fault circuit parameters are calculated at both end IEDs, and the fault distance is calculated by Equation (10).

4. Simulation Results

4.1. Simulation System and Parameters

To demonstrate the effectiveness of the proposed fault detection and location scheme, a simulation model of symmetrical bipolar DC distribution was built in PSCAD/EMTDC, as shown in Figure 5, where the dashed box indicates the part mainly used for the case study. Manitoba Hydro developed PSCAD/EMTDC, and PSCAD provides a graphical user interface for EMTDC (electromagnetic transients including DC). PSCAD enables users to construct circuit models flexibly and provides a wide variety of components. The converter is a two-level voltage source converter (VSC), and the DC side is grounded with a clamping capacitor through a small resistor.

During simulation, each converter adopts inner and outer loop decoupling control, with one end (A) set to ±10 kV DC voltage control, and other end set to active power control, transmitting 10 MW rated power. The DC line adopts an AC polyethylene-insulated (XLPE) power cable with a cross-sectional area of 150 mm², model YJV-8.7/10 kV. The specific simulation parameters are shown in

Table 1. The parameters of the simulation system.

Simulation Parameters	Values	Simulation Parameters	Values
DC voltage/kV	±10	DC line length of AB/km	10
AC line voltage/kV	10	Unit resistance/(Ω/km)	0.123
AC reactor/mH	10	Unit reactance/(mH/km)	0.984
DC capacitor/μF	20,000	Unit capacitance/(μF/km)	0.283

.

4.2. Transient Characteristics of DC Faults

(1)

PTG Faults

The change trends of the voltages and currents obtained at terminal A after a positive PTG fault with 1Ω fault resistance are shown in Figure 6. In Figure 6, a PTG fault occurred at t₀ = 0 ms. After about 5 ms, the A-terminal VSC was locked due to overcurrent at t₁ (when the current flowing through the IGBT exceeded 3 kA). After locking, the current flowing through the reverse parallel diode of the A-terminal VSC rapidly increased, as shown in Figure 6c. Therefore, it was necessary for the protection device to quickly cutoff the fault and leave a data length of less than 5 ms for the fault location.

(2)

PTP Faults

A PTG fault occurred at 1 km from the A terminal, and the voltages and currents are shown in Figure 6. After about 3 ms, the VSC was locked due to overcurrent at t₁. From Figure 7a, when t₂ was approximately equal to 10 ms, the DC voltage dropped to zero. At this point, the anti-parallel diode current of the A-end VSC was positive, and the freewheeling current was conducting, causing the fault current to rapidly increase, as shown in Figure 7c, which needs to be avoided.

4.3. Performance Analysis of Fault Detection Scheme

In this paper, a positive PTG fault with a fault resistance of 50 Ω at position F₁ was simulated. After the fault, the current changes at all SMPs on DC bus 1 and bus 2 are shown in Figure 8. At this point, due to the large fault resistance, the amplitude of the fault current was weak. It may be difficult to accurately detect the fault using current amplitude or current change rate methods. From Figure 8, the SMPs R12 and R21 were at the faulty line, the integral values S₁₂ and S₂₁ of the current superposition were both positive, while for the healthy lines R13 and R24 on the same DC bus, the integral values S₁₃ and S₂₄ of the current superposition were both negative, and this feature was utilized to diagnose faults.

(1)

Influence of the Fault Positions

To test the performance of the proposed direction pilot protection scheme at different fault positions, a simulation was conducted, as shown in Figure 5, where F₁ experienced a positive PTG fault with 1 Ω fault resistance, and the positions varied from 1 km to 9 km of cable 1. The change trends of the current superposition calculated at different SMPs on bus 1 and bus 2 are shown in Figure 9.

From Figure 9, it can be observed that the closer the distance to the VSC, the larger the calculated value of the current superposition, but even at the end of the line, its computed value was still far greater than the protection threshold. For the SMPs R13 and R24 of the same DC bus, the calculated current superposition was a value with a smaller amplitude of less than zero. The parallel capacitors of VSCs were closest to the fault point and discharged into the fault point; thus, the fault currents fed into the healthy line were limited. By simulating faults at different positions, it can be verified that the proposed fault protection scheme identified faults at different fault positions, and it did not relay the protection boundary.

(2)

Influence of the Fault Resistances

To test the performance of the proposed directional criterion under different fault resistances, a positive PTG fault occurred at 2 km from the R12, as shown in Figure 5. The fault resistances varied from 0.01 Ω to 100 Ω, and the faults were detected using the proposed scheme, as shown in Figure 10.

The protection results of the SMPs on each line of bus 1 and bus 2 are shown in Figure 10. When the fault resistance was less than 30 Ω, the integral of the current superposition calculated at the SMP in the fault area was positive and significantly decreased with the increase in the fault resistance, while the current superposition calculated at the SMP in the healthy line of the same DC bus was negative; thus, the proposed scheme accurately identified the fault direction. When the fault resistance reached 100 Ω, although the calculated value of the current superposition was small, it was still greater than the set value, indicating that the proposed directional criterion has a high ability to identify fault resistance.

4.4. Results of the Proposed Fault Location Scheme

Taking the example of not installing CLRs at both ends of the line, the fault location process and performance were deeply analyzed.

(1)

Fault Location Process

Due to the limited available data length, 20 recorded data points (i.e., 2 ms data length under a 10 kHz sampling rate) were used for fault location. The reactance at both ends of A and B was calculated, as shown in Figure 11a. Based on the computed reactance values of the fault circuit lines at both ends of A and B, the fault distance was calculated using the Equation (10), as shown in Figure 11b. To demonstrate the performance of the proposed method, the maximum error of the fault distance calculated within 0.5 ms to 1.5 ms after the fault occurred was taken. Meanwhile, to more conveniently describe the location accuracy, the location error rate was defined as:

$$e=\left|{\displaystyle \frac{x_1-{x_1}^{\prime }}{L_{AB}}}\right|\times 100\%$$

(12)

where e is the error rate, x₁ is the calculated fault distance, x₁′ is the actual location of the fault, and L_AB is the total length of the line.

For PTP faults, the fault location process was similar to that of PTG faults, using 20 recorded data points for fault location. Figure 12 shows the location accuracy measured after a PTP fault and a PTP fault, with a 1 Ω fault resistance at different fault positions on the line. From Figure 12, regardless of where the fault occurred on the line, the location error rate was less than 0.5%. The fault location error rate during a fault in the middle of the line was higher than that at both ends, because the equivalent distributed capacitance on both sides of the fault line was relatively large, which caused certain interference with the fault location results. The simulation results verified that the proposed method could achieve online fault location without the need for additional devices and had high accuracy with a low sampling rate.

(2)

Impact of Fault Resistances and Distances

To study the influence of fault resistance and fault distances on the fault location results, a PTG fault was simulated, with different fault resistances occurring at varying positions on the line. The fault location results are shown in Figure 13.

From Figure 13, when the fault resistance was less than 5 Ω, the absolute location error obtained after different fault conditions was less than 70 m. The location accuracy near both ends of the line was more sensitive to resistance changes, resulting in significant errors when the fault resistance was 15 Ω. The location accuracy of the middle section of the line was less sensitive to the fault resistance, but the location error rate was higher than at both ends of the line when the fault resistance was small. The reason is that as the fault resistance increased, the fault current was already weak, and the interference of the distributed capacitance current in the circuit was more obvious. When there was a fault near both ends of the line, the equivalent distributed capacitance on one side was smaller than the equivalent distributed capacitance on the other side, and the impact of distributed capacitance was more pronounced when the fault current was smaller.

(3)

Influence of the Data Length and Sampling Rate

To study the influence of different data lengths on the fault location results, the calculated inductance results at the A terminal were compared at a sampling rate of 10 kHz, and the sampling points were N = 20, 40, and 60 points, respectively. The simulation results are shown in Figure 14: with the increase in sample points, the calculated values were more stable and accurate. In practical environments, since DCCB will quickly cutoff faults, the sampling points obtained are limited.

To study the impact of different sampling rates on the proposed fault location scheme, the fault location accuracy was compared at sampling rates of 5 kHz, 10 kHz, and 20 kHz, and the results are shown in Figure 15. From Figure 15, when the fault resistance was less than 5 Ω, the influence of the sampling rate was relatively small, and high fault location results were achieved. However, when the fault resistance increased, smaller sampling rates were more likely to produce larger location errors. At the same sampling rate of 10 kHz, as the data length increased from 1 ms to 3 ms, the fault location results became more accurate due to the acquisition of more information, but it did not increase nonlinearly. Increasing the data length from 1 ms to 2 ms significantly improved the location accuracy, while the improvement from 2 ms to 3 ms was limited.

(4)

Influence of the Asynchronous Sampling

In practical environments, there may be asynchronous sampling between the sampling signals at both ends. At a sampling rate of 10 kHz, the number of sampling points at both ends of the line that differed due to asynchronous sampling was taken as p = 0, 1, and 2, respectively. The fault location results are shown in Figure 16. As p increased, the location error rate also increased. Due to the large change rate of the transient DC faults’ current, a large location error was caused when p was larger than 2.

Besides, in this paper, the current difference methods of fault location accuracy were compared, and the comparison results are shown in Figure 16. The simulation results verified that the proposed difference method, as in Equation (6), improved the accuracy of fault location results when compared with the traditional methods used in Reference [24].

(5)

Influence of DC Line with CLRs

In the case of installing a CLR at both ends of the line, the time requirement for protection was slightly alleviated, and the data length that could be obtained was longer. To improve the fault location accuracy and reduce the high-frequency transient effects caused by CLRs and distributed capacitors, this paper took N = 30 under a 10 kHz sampling rate. A digital low-pass Butterworth filter was introduced to filter out the influence of high-frequency transient signals. The passband boundary frequency of the low-pass filter was set to 150 Hz, the cutoff frequency was 1550 Hz, and the maximum attenuation coefficient of the stopband was 22.

When a PTG fault with 1 Ω resistance occurred at 3 km from the A terminal, the location results were as shown in Figure 17. In Figure 17a, V_L1 is the voltage on the A-terminal CLR, which generated a high-frequency transient signal due to the presence of distributed capacitance. Figure 17a compares the voltage changes before and after filtering. V_L2 is the voltage value on the B-terminal CLR, and its trend is similar to that on the A terminal, as shown in Figure 17b. Figure 17c shows the fault location results obtained using the proposed scheme. From Figure 17c, there was a significant location error between 0 and 2 ms after the fault occurred. The reason is that the signal fluctuated greatly during this period, and the low-pass filter had a certain impact on the original signal. Therefore, in this paper, fault data after 3 ms were selected for fault location to obtain more accurate results.

4.5. Comparison Results

(1)

Comparison Results of the Fault Detection Scheme

Reference [13] proposed a superimposed current-based unit protection scheme for the DC microgrid. The magnitude of the superimposed current could determine the direction of the fault, but this value was small, especially in the case of high-resistance faults, where the difference in characteristics between internal and external faults was not significant enough. On this basis, in this paper, we used the integration of current superposition to determine the fault direction, which expanded the differences and improved the reliability of protection. To further demonstrate the performance of the proposed fault detection method, PTG faults were simulated at different locations (1, 3, 5, 7, and 9 km) in the simulation system, and the detection results are shown in Figure 18, where S_12P and S_13P represent the protection values of the proposed method, while S_12P′ and S_13P′ are the protection values from Reference [13]. The proposed method had more significant protection differences and could detect faults more reliably.

(2)

Comparison Results of the Fault Location Scheme

In this paper, PTG faults were simulated with 2Ω fault resistances at different locations (1, 3, 5, 7, and 9 km) on a DC line. The comparison results of different fault location methods are shown in

Table 2. Fault location errors with different methods.

Methods	Conditions	Fault Position/km
		1	3	5	7	9
Proposed	N = 10	1.6 m	11.1 m	13.3 m	5.1 m	2.1 m
Reference [19]	10 kHz	41.0 km	28.0 km	30.0 km	17.0 km	41.0 km
	500 kHz	5.0 km	10.0 km	7.5 km	2.5 km	6.5 km
Reference [21]	PTP faults	102.3 m	350.8 m	143.6 m	26.5 m	295.1 m

. For the D-type traveling-wave-based fault location method [19], when the sampling rate was 10 kHz, the fault location error caused by one sampling point error exceeded the total length of the line (10 km). Therefore, a lower sampling rate could not be used for fault location when the line length was short. When the sampling rate increased to 500 kHz, fault location was theoretically feasible. However, due to the presence of DC parallel capacitors, the DC voltage did not undergo sudden changes, resulting in significant errors in the initial fault waveform captured by discrete wavelet transform.

Reference [21] used two sampled signals at different times to solve the equivalent parameters of the fault circuit, thereby obtaining the fault position. The principle of this method is simple: it is prone to interference by relying on the sampling signal at a certain moment. This method has extremely high requirements for signal synchronization sampling, and it can only be applied to PTP faults. In this paper, the LS method was used to solve overdetermined equations, thus reducing the impact of noise and data singularities, and obtaining the highest fault location accuracy.

5. Conclusions

In this paper, a direction pilot protection scheme suitable for complex DC distribution networks was proposed based on the integration of current superposition. Besides, an online fault location scheme based on the least squares method to solve the overdetermined equation was also proposed. The proposed fault detection and location scheme has the following advantages:

(a)

The proposed fault detection scheme applies to complex DC distribution networks and can reliably detect grounding faults with high fault resistances.

(b)

The proposed fault location scheme considers the influence of distributed capacitance and improves the calculation method of the current differential to reduce the fault location error.

(c)

The proposed scheme is a time-domain scheme, does not require a high sampling rate and data length, is suitable for complex networks with multiple sources, and can achieve online fault location, reducing the cost and complexity of the location scheme.

The disadvantage of the proposed scheme is that it requires a communication system, but only needs to transmit the current data of the fault recorder to the opposite end at a certain moment after the fault.

The next step of the work can focus on whether the grounding method of the DC distribution system and the grounding medium of the grounding fault have an impact on the method proposed in this paper.