Research on a Thirteen-Level Switched Capacitor Inverter with Low Switching Loss

Abstract

This paper presents a 13-level switched capacitor inverter with a novel modulation method designed to minimize the number of switches and significantly reduce switching losses. The inverter stands out for its simplicity, requiring only ten semiconductor switches to generate 13 levels. A key feature is the inherent self-voltage balancing of the capacitors, which eliminates the need for additional control mechanisms. The inverter’s unique architecture, comprising high-voltage and low-voltage modules, enables modulation using a hybrid PWM approach that combines step waveform modulation with level-shifted PWM (LS-PWM). This innovative technique dramatically lowers the switching frequency of the high-voltage module’s switches, independent of the carrier frequency, thereby limiting the number of switches in high-frequency operation and achieving substantial reductions in switching losses. This paper provides a detailed analysis of the inverter’s operating modes, voltage-balancing mechanisms, and parameter calculations. The advantages of the topology presented in this paper are demonstrated by comparison. Finally, the simulation and experimental results confirm the practicality and effectiveness of the proposed inverter and its modulation strategy.

1. Introduction

Compared with two- or three-level inverters, multilevel inverters (MLIs) have many advantages, such as less total harmonic distortion (THD), reduced dv/dt stress, and lower electromagnetic interference (EMI) [1]. They have been put into widespread use in photovoltaic power generation [2], motor drive, and electric vehicles [3]. Conventional multilevel inverters include the cascaded H-bridge inverter (CHB) [4], flying capacitor inverter (FC) [5], and neutral point-clamped (NPC) inverter [6]. CHB inverters need numerous DC sources, thus putting strict requirements on the number of dc supplies. FC and NPC inverters suffer from the imbalance in voltage of capacitors, so they need an extra control algorithm to detect and adjust the capacitor voltage. Moreover, these conventional inverters need a large number of switches, diodes, and capacitors to generate more levels [7]. As a result, the production of these converters can be extremely bulky and cost-consuming.

To reduce the number of components and achieve a low switch count, many scholars focus on inverters based on an asymmetrical structure [8,9]. Different from traditional CHB inverters, whose dc sources have the same voltage, asymmetrical inverters employ dc supplies with various voltage values. The basic unit proposed in [8] applies three dc sources, the voltage ratio of which is 1:1:3, thus maximally achieving 11-level output with only eight semiconductor switches. Similar to [8], the topology in [9] uses four dc supplies and 12 switches to generate 17 levels. Compared to a traditional CHB converter, asymmetrical multilevel inverters not only reduce the switch number significantly but also make the output more flexible, whereas it needs a large number of independent sources.

Recently, researchers have paid great attention to inverters based on switched-capacitor (SC) structures since this technique is able to limit the number of input sources. For instance, an extendable inverter based on an SCC unit is proposed in [10]. By replacing dc sources with capacitors, this inverter uses only two sources and 16 switches to generate 13 levels. Similarly, the topology proposed in [11] can also generate 13 levels with two sources. The difference is that the amplitude of two input sources is unequal. Although these two topologies reduce the amount of dc power to some extent, they still require two sources, making them not suitable for single-source occasions. A nine-level inverter for low-voltage applications is introduced in [12]. It has prominent strengths, such as a low switch count and one dc source. However, the capacitor voltage is unable to balance automatically. As a result, extra devices for voltage control are necessary, which makes it uneconomical.

The problem of capacitor imbalance in SC inverter has been handled in [13,14,15]. While [13] charges the capacitors by connecting them in series, the capacitors in [14,15] are charged in parallel. In this way, the inverter can not only acquire self-balancing but also boosting capability. Nevertheless, these topologies embody a back-end H bridge whose four switches have to withstand peak output voltage. Consequently, the total standing voltage (TSV) of these inverters is likely to increase greatly.

In order to reduce the voltage stress, SC inverters without an H bridge have been proposed [16,17,18,19,20]. Structures based on K-type and X-type units are presented in [16,17], respectively. In these two topologies, switches suffering the maximum voltage stress only withstand 2/3 of the peak output voltages. However, the boosting factor of the K-type inverter is low (less than 2), and the X-type topology requires a large number of switches. The topology in [18,19] shares similar characteristics in that they are both based on an NPC and T structure. The switch voltage stress in these two inverters is not higher than V_dc, while the maximum output reaches 1.5V_dc. The topology proposed in [20] shows greater superiority: the maximum voltage stress of all the semiconductor switches does not exceed half of the peak output voltage, which is lower than the ratio for [16,17,18,19].

On the other hand, most SC inverters are modulated by the traditional method. A fundamental frequency method, such as selective harmonic elimination pulse-width modulation (SHEPWM) and nearest level control (NLC), are adopted in [10,11,13,14,15,16,17,18,21,22,23]. These two techniques lead to higher THD and bring difficulties in filter design. Triangular carrier-based methods are conducive to reducing THD. [10,18,19,20,24,25] uses LS-PWM to modulate inverters. However, methods like LS-PWM and phase-shift pulse-width modulation (PS-PWM) result in a large number of switches working in high-frequency states, including switches with high blocking voltage. As a result, this can lead to high switching losses. To improve the performance of the SC inverter, [26,27,28] demonstrates a new hybrid modulation technique that combines LS-PWM and PS-PWM. This hybrid technique dramatically reduces the voltage ripple of capacitors, yet it still makes too many switches work in the high-frequency state.

To solve the abovementioned problems, this paper introduces a 13-level SC inverter. The proposed inverter has the following merits: (a) only 10 switches are needed; (b) self-voltage balance is achieved; (c) no back-end H bridge is required; and (d) triple boost ability is realized. Apart from topology, a novel hybrid PWM combining the low-frequency and high-frequency modulation is proposed. Under this modulation, switches with high blocking voltage all work at low switching frequencies. And the number of high-frequency switches is greatly limited. Thus, the switching loss can decrease dramatically. This inverter can be applied to low-voltage occasions, such as photovoltaic or electric vehicles. Additionally, the proposed topology can also be modulated by traditional modulation, such as NLC or SHEPWM. Therefore, this inverter can also be used in high-frequency occasions such as wireless power transfer (WPT).

In this paper, Section 2 introduces the modes and working circuits of the proposed 13-level inverter. Section 3 demonstrates the proposed hybrid modulation method as well as its application range. Next, Section 4 describes the principles of voltage balance and parameter selection. Section 5 gives the losses analysis and comparison results. Afterwards, Section 6 shows the simulation and experimental results. Finally, conclusions are drawn to summarize the all the works conducted in this research.

2. Working Modes of Proposed Topology

2.1. Structure of Proposed Topology

Figure 1 demonstrates the circuit configuration of the proposed inverter. This inverter consists of a high-voltage module and a low-voltage module. Capacitors C_a1, C_a2, as well as switches S₁, S₁′, and S_a (bidirectional switch), comprise the low-voltage module. Other switches, two diodes, and capacitors C₁ to C₃ form the high-voltage module. The maximum output of the inverter is 3V_dc, thus achieving triple voltage gain. In its steady state, the voltage of capacitors C_a1 and C_a2 is stabilized at V_dc/2, while the other three capacitors (C₁, C₂, and C₃) are maintained at V_dc. The capacitors are self-balanced, so an auxiliary control system for capacitor voltage is not required. It is worthwhile to mention that S₂ and S₅, which are switches without body diode, can be equivalently replaced by a switch with the body diode and a diode connecting in series or a bidirectional switch.

2.2. Working Mode Analysis

The 13-level inverter has 18 different working modes overall. The information of all the modes is listed in

Table 1. Switching state of proposed 13-level inverter.

Group	Mode	S1	Sa	S1′	S2,3,4,5,6	C1	C2	C3	vo
A	3	0	0	1					3Vdc
	2.5	0	1	0	01001	D	D	C	2.5Vdc
	2+	1	0	0					2Vdc
B	2−	0	0	1					2Vdc
	1.5	0	1	0	10011	D	C	N	1.5Vdc
	1+	1	0	0					Vdc
C	1−	0	0	1					Vdc
	0.5	0	1	0	00101	C	N	N	0.5Vdc
	0+	1	0	0					0
D	0−	0	0	1					0
	−0.5	0	1	0	01000	N	N	C	−0.5Vdc
	(−1)+	1	0	0					−Vdc
E	(−1)−	0	0	1					−Vdc
	−1.5	0	1	0	10010	N	C	D	−1.5Vdc
	(−2)+	1	0	0					−2Vdc
F	(−2)−	0	0	1					−2Vdc
	−2.5	0	1	0	00100	C	D	D	−2.5Vdc
	−3	1	0	0					−3Vdc

. Number ‘1’ means the switch is turned on, and ‘0’ means the switch is turned off. In the column of capacitors, ‘C’, ‘D’, and ‘N’ denote charging, discharging, and the isle state, respectively. The switching state for S₆′ is complementary to S₆, so its states are not listed in the table. It is worthwhile to mention that the output of 2V_dc, V_dc, 0, −V_dc, and −2V_dc all correspond to two different modes, marked with ‘+’ and ‘−’, respectively (for example, mode 2+ and 2− both represent the states generating 2V_dc output). Figure 2 presents information about how the circuit works in a positive half cycle. The red curves in Figure 2 represent the load circuit, and the blue ones show the charging circuit of C₁, C₂, and C₃. The positive working states are analyzed as follows:

(1)

Modes 3, 2.5, and 2+: In these three states, switches S₃ and S₆ turn on in the high-voltage module. As S₃ switches on, the diode D₂ is conducted so that the charging loop for C₃ is formed. As for the low-voltage module, S₁′, S_a, and S₁ are switched on in turn to generate 3V_dc, 2.5V_dc, and 2V_dc, respectively.

(2)

Mode 2−, 1.5 and 1+: Similarly, the switching states in the high-voltage module are completely the same, and switches in the low-voltage module are conducted alternately. By turning on S₂ and S₅, the capacitor C₂ can be charged to the input source voltage.

(3)

Mode 1−, 0.5 and 0+: S₄ is turned on in these states and D₁ conducts so that C₁ can be charged to V_dc. As for the low-voltage module, one of three switches is turned on to generate different output levels.

The working principle in the negative half cycle is similar to that in the positive half cycle, so it is not described to avoid repetition.

3. Proposed Modulation Method

In Table 1, it can be seen that the 18 modes are divided into six groups (from A to F). Every group contains three adjacent modes. Coincidentally, in each group, the state of high-voltage module switches (S_{2,3,3,5,6,6′}) are completely the same, and low-module switches are conducted by turns. Due to this special characteristic of the working state, a novel hybrid PWM is designed for this inverter.

Figure 3 demonstrates the principles of modulation as well as the driving signals of each switch. As is shown in this figure, the high-voltage module and low-voltage module use different modulation types and reference signals.

3.1. Step Waveform Modulation for High-Voltage Module

The high-voltage module uses staircase waveform-based modulation, the reference signal of which is v_refh. The mathematical expression of v_refh is as follows:

$$v_{refh}=3M\mathit{sin}(\omega t)$$

(1)

where M is the modulation index and w represents the angular frequency of the output.

As v_refh varies, the switching states of S₂ to S₆ change according to the rules of grouping.

Table 2. Modulation state for high-voltage module.

State	Group	S2,3,4,5,6
vrefh > 2	A	01001
1 < vrefh < 2	B	10011
0 < vrefh < 1	C	00101
−1 < vrefh < 0	D	01000
−2 < vrefh < −1	E	10010
vrefh < −2	F	00100

gives detailed information on this.

3.2. LS-PWM for Low-Voltage Module

For the low-voltage module, the LS-PWM technique is employed. As is illustrated in Figure 3, the switching states of S₁, S₁′, and S_a are determined by comparing the low-voltage module reference signal v_refl and four triangular carrier signals: ±u₁ and ±u₂. The peak-to-peak value of these four carrier signals is 0.5, and the reference signal v_refl can be expressed as Equation (2). The switching signals of S₁, S_a, and S₁′ follow the rules listed in

Table 3. Modulation states for low-voltage module.

State	S1 Sa S1′
vrefl > u2	001
u1 < vrefl < u2	010
0 < vrefl < u1	100
−u1 < vrefl < 0	001
−u2 < vrefl < −u1	010
vrefl < −u2	100

.

According to the switching signals in Figure 3, it can be seen that S₂~S₆ have very low switching frequencies under hybrid modulation. Although S₁, S₁′, and S_a work in a high-switching frequency state, the blocking voltage at the switching action moment for these three switches is only V_dc/2. Therefore, the hybrid modulation method is able to limit the number of high-frequency switches and reduce the switching loss of this inverter significantly.

$$v_{refl}=\left\{\begin{array}{l}{v}_{refh}-2,\begin{array}{cc}& v_{refh}>2\end{array}\\ v_{refh}-1,\begin{array}{cc}& 1<v_{refh}<2\end{array}\\ v_{refh},\begin{array}{cc}& -1<v_{refh}<1\end{array}\\ v_{refh}+1,\begin{array}{cc}& -2<v_{refh}<-1\end{array}\\ v_{refh}+2,\begin{array}{cc}& v_{refh}<-2\end{array}\end{array}\right.$$

(2)

4. Self-Balance Analysis and Capacitance Calculation

4.1. Self-Balance Analysis

The capacitor’s voltage can be self-balanced under the hybrid modulation technique. The voltage balance for C₁, C₂, and C₃ is achieved by connecting them in parallel with the dc source in different working modes (see Figure 2 or Table 1). Thus, they are charged to V_dc periodically.

The balance principle of C_a1 and C_a2 is based on the neutral point current.

Figure 4 presents the information about the balancing circuit of C_a1 and C_a2. i_n represents the current flowing into the neutral point, and i_ca1, i_ca2 are the currents of the two capacitors. Since these two capacitors are connected with V_dc in parallel, the voltage of the two capacitors v_ca1 and v_ca2 must satisfy the following:

$$v_{ca1}+v_{ca2}=V_{dc}$$

(3)

The neutral point current i_n is equal to the output current i_o when S_a turns on and becomes zero in other states. Under hybrid modulation, S_a is switched on when u₁ < v_refl < u₂ or −u₂ < v_refl < −u₁. To simplify the analysis, we supposed that the output current i_o was a sinusoidal wave; under this assumption, the waveform of the neutral point current is demonstrated in Figure 5.

In Figure 5, i_omax denotes the amplitude of the output current. It is clear that the waveform of i_n has a central symmetrical characteristic because the conduction period of S_a in the positive and negative half cycle are completely identical. Therefore, the average value of the neutral point current is zero. It is worthwhile to mention that though the output current may not form a pure sinusoidal waveform, the average value is still zero as long as it has symmetrical characteristics. According to Kirchhoff’s circuit laws (KCL), the relationship between i_n, i_ca1, and i_ca2 can be expressed as follows:

$$i_n+i_{ca1}=i_{ca2}$$

(4)

Therefore, the voltage of C_a1 and C_a2 can meet the following expression:

$$i_n+C_{a1}{\displaystyle \frac{d{v}_{ca1}}{dt}}=C_{a2}{\displaystyle \frac{d{v}_{ca2}}{dt}}$$

(5)

Combining Formulas (3) and (5) and integrating both sides, the voltage fluctuation can be written as follows:

$${\displaystyle {\int }_t^{t+T}{i}_n}dt=-(C_{a1}+C_{a2})[v_{ca1}(t+T)-v_{ca1}(t)]$$

(6)

where T represents the period of the output voltage. Since the average value of i_n is 0, we can finally obtain the following:

$$\left\{\begin{array}{l}{v}_{ca1}(t+T)=v_{ca1}(t)\\ v_{ca2}(t+T)=v_{ca2}(t)\end{array}\right.$$

(7)

which means that the voltage change in C_a1 and C_a2 during one circle is zero.

Therefore, all the capacitors can achieve self-balance under the novel hybrid modulation method.

4.2. Capacitance Calculation

The calculation principles for capacitor parameters are mainly based on the maximum voltage ripple.

Capacitance calculation for the high-voltage module: To ascertain C₁, C₂, and C₃, it is important to figure out their maximum discharging period. In Figure 3, θ₁ and θ₂ are switching angles between different groups and can be calculated as follows:

$${\theta }_i=\arcsin ({\displaystyle \frac{i}{3M}})\begin{array}{cc}& i=1,2\end{array}$$

(8)

where M is the modulation ratio.

For C₁, its discharging states are in groups A and B, so its maximum discharging interval is [θ₁, π−θ₁]. Similarly, the maximum discharging intervals of C₂ and C₃ are [θ₂, π−θ₂] and [π + θ₁, 2π−θ₁], respectively. Of course, when the modulation ratio M is equal to 1, these discharging intervals become the longest. Hence, the maximum voltage ripple for C₁, C₂, and C₃ can be given as follows:

$$\left\{\begin{array}{l}\Delta V_{c1}={\displaystyle \frac{1}{C_1}}{\displaystyle {\int }_{{\theta }_1/2\pi f}^{(\pi -{\theta }_1)/2\pi f}{i}_o(t)}dt\\ \Delta V_{c2}={\displaystyle \frac{1}{C_2}}{\displaystyle {\int }_{{\theta }_2/2\pi f}^{(\pi -{\theta }_2)/2\pi f}{i}_o(t)}dt\\ \Delta V_{c1}={\displaystyle \frac{1}{C_1}}{\displaystyle {\int }_{(\pi +{\theta }_1)/2\pi f}^{(2\pi -{\theta }_1)/2\pi f}{i}_o(t)}dt\end{array}\right.$$

(9)

where ΔV_c1, ΔV_c2, and ΔV_c3 are the maximum voltage ripple of these three capacitors and f is the output frequency. We suppose that the voltage ripple could not exceed 10% of the rated voltage [21]; thus, the selection of capacitance can be given as follows:

$$\left\{\begin{array}{l}{\mathrm{C}}_1\ge {\displaystyle \frac{1}{10\%\times V_{dc}}}{\displaystyle {\int }_{{\theta }_1/2\pi f}^{(\pi -{\theta }_1)/2\pi f}{i}_o(t)}dt\\ C_2\ge {\displaystyle \frac{1}{10\%\times V_{dc}}}{\displaystyle {\int }_{{\theta }_2/2\pi f}^{(\pi -{\theta }_2)/2\pi f}{i}_o(t)}dt\\ C_3\ge {\displaystyle \frac{1}{10\%\times V_{dc}}}{\displaystyle {\int }_{(\pi +{\theta }_1)/2\pi f}^{(2\pi -{\theta }_1)/2\pi f}{i}_o(t)}dt\end{array}\right.$$

(10)

Capacitance calculation for low-voltage module: the current flowing through C_a1 and C_a2 is mainly decided by the neutral point current i_n. According to (4) and (5), the voltage change in C_a1 can be derived as follows:

$$-{\displaystyle \frac{1}{C_{a1}+C_{a2}}}{\displaystyle {\int }_{t_1}^{t_2}{i}_n}dt=v_{ca2}(t)-v_{ca1}(t)$$

(11)

where t₁ and t₂ are two different arbitrary moments.

Therefore, C_a1 has the maximum voltage ripple when the time interval [t₁, t₂] represents one whole positive half cycle of the output current. Considering the symmetrical structure, we choose the same parameters for C_a1 and C_a2. In order to simplify the calculation, it is supposed that C_a1 discharges during the whole positive half cycle of i_o. In this way, the maximum voltage ripple of C_a1 is estimated to be:

$$\Delta V_{ca1}=-{\displaystyle \frac{1}{2C_{a1}}}{\displaystyle {\int }_t^{t+\pi /\omega }\left|i_o\right|}dt=-{\displaystyle \frac{1}{2C_{a1}}}{\displaystyle {\int }_t^{t+\pi /\omega }\frac{3M{V}_{dc}\left|\sin \omega t\right|}{Z_L}}dt=-{\displaystyle \frac{3M{V}_{dc}}{\omega C_{a1}{Z}_L}}$$

(12)

where Z_L is the load at the output side. When M = 1, the voltage ripple reaches the largest value. If the voltage ripple of C_a1 is no more than 10% of its rated voltage [21], the capacitance for C_a1 and C_a2 can be calculated as follows:

$$C_{a1}=C_{a2}\ge {\displaystyle \frac{60}{\omega \left|Z_L\right|}}$$

(13)

Actually, the capacitance of C_a1 and C_a2 can be smaller because their discharging time is shorter than half of one cycle during one period. However, to simplify the calculation complexity, Equation (13) is a suitable way to estimate the capacitance.

5. Loss Analysis and Comparative Study

5.1. Loss Analysis

In most cases, the power losses of an SC inverter are mainly caused by conduction loss, the capacitors’ charging loss, and switching loss.

Conduction Loss: The conduction loss of the inverter results from the parasitic parameters of the conducting components in the load circuit, which includes the forward voltage drop in the diode V_D, the on-resistance of the diode r_D, the on-resistance of the switch r_s and the internal resistance of capacitors r_C. In order to simplify the calculation, we supposed that the same type of components have identical parameters.

Due to the hybrid modulation method, the conduction losses of the high-voltage module and low-voltage module are calculated separately. For the high-voltage module, the energy losses in the periods of groups A, B, or C during one cycle (which are represented by E_conA, E_conB, and E_conC, respectively) are expressed in (14). The energy losses for groups D, E, and F are the same as A, B, and C.

$$\left\{\begin{array}{l}{E}_{conA}={\displaystyle {\int }_{{\theta }_2/\omega }^{(\pi -{\theta }_2)/\omega }{i}_o^2(2r_s+2r_c)dt}\\ E_{conB}={\displaystyle {\int }_{{\theta }_1/\omega }^{{\theta }_2/\omega }{i}_o^2(2r_s+r_c)dt+{\displaystyle {\int }_{(\pi -{\theta }_1)/\omega }^{(\pi -{\theta }_2)/\omega }{i}_o^2(2r_s+r_c)dt}}\\ E_{conC}={\displaystyle {\int }_0^{{\theta }_1/\omega }{V}_D{i}_o+i_o^2(r_s+r_D)dt+{\displaystyle {\int }_{(\pi -{\theta }_1)/\omega }^{\pi /\omega }{V}_D{i}_o+i_o^2(r_s+r_D)dt}}\end{array}\right.$$

(14)

where i_o is the output current. Thus, the conduction losses for the high-voltage module can be calculated as follows:

$$P_{conH}=2f_o(E_{conA}+E_{conB}+E_{conC})$$

(15)

where P_conH represents the conduction loss for the high-voltage module and f_o represents the output frequency.

As for the low-voltage module, it is assumed that the conducting times of S₁, S₁′, and S_a take up 1/4, 1/4, and 1/2 of the whole cycle, respectively. Therefore, the conduction loss for the low-voltage module is expressed as follows:

$$P_{conL}=2\times {\displaystyle \frac{f_o}{4}}{I}_{rms}^2{r}_s+{\displaystyle \frac{f_o}{2}}\times 2I_{rms}^2{r}_s=1.5f_o{I}_{rms}^2{r}_s$$

(16)

where I_rms is the root mean square value of i_o

The total conduction loss P_con is given below:

$$P_{con}=P_{conH}+P_{conL}$$

(17)

Ripple Loss: The ripple loss is mainly caused by the difference between the ideal capacitor voltage and the actual charging voltage. The estimated ripple loss can be given as follows [16]:

$$P_{ripple}=f_o{C}_a{(\Delta V_{ca})}^2+{\displaystyle \frac{1}{2}}{f}_o{\displaystyle \sum _{i=1}^3{C}_i{(\Delta V_{ci})}^2}$$

(18)

where ΔV_C1, ΔV_C2, and ΔV_C3 represent the maximum voltage ripple of C₁, C₂, and C₃ and the capacitance value and voltage ripple of C_a1 and C_a2 are assumed to be C_a and ΔV_Ca.

Switching Loss: Switching loss occurs owing to the time delay when the switch turns on or off. The switching loss of one certain switch P_sw can be calculated using Equation (19) [16]:

$$P_{sw}=f_{sw}{C}_{oss}{V}_b^2$$

(19)

where C_oss represents the parasitic capacitance of the semiconductor switch and V_b represents the blocking voltage of the power switch at the turning on or turning off moment.

Table 4. Switching frequency and blocking voltage of various switches.

Swtiches	Switching Frequency	Blocking Voltage
S1 and S1′	5fo + fc/2	Vdc/2
Sa	fc	Vdc/2
S2 and S5	4fo	Vdc
S3 and S4	3fo	2Vdc, Vdc
S6 and S6′	fo	3Vdc

presents the blocking voltage, switching frequency, as well as the blocking voltage of each semiconductor switch. In the table, f_o represents the output frequency, and f_c represents the carrier frequency.

It is worth mentioning that among the six switching actions of S₃ and S₄ in one output period, two of them have a voltage change of 2V_dc while the voltage changes in the other four is V_dc. This is further verified by experimental results in Section 6.

By adding each switching loss for all the switches in the topology, the total switching loss P_sw-tot can be calculated as follows:

$$P_{sw-tot}={\displaystyle \sum _{all the switches}{P}_{sw}}=(40.5f_o+{\displaystyle \frac{1}{4}}{f}_c)C_{oss}{V}_{dc}^2=(162f_o+2f_c)C_{oss}{V}_{step}^2$$

(20)

where V_step =V_dc/2 represents the minimum step voltage of the output.

5.2. Comparative Study

Quantitative comparison: To show the merits of the proposed inverter, this part compares the proposed topology with other similar inverters [10,11,14,15,21,23,24,27,28,29,30] in terms of the number of dc sources (N_S), switches (N_sw), gate drivers (N_DR), diodes (N_D), capacitors (N_C), levels (N_sw), and the TSV. Considering different boosting abilities, the total standing voltage is calculated as the ratio of the voltage stress of all switches to the minimum step voltage V_step. Additionally, the cost function (CF) used in [27] is adopted to evaluate the overall performance of the proposed inverter. The CF is expressed as shown in Formula (21):

$$CF={\displaystyle \frac{N_{sw}+N_{DR}+N_D+N_C+\alpha TSV}{N_{level}}}\times N_S$$

(21)

where α is the weight coefficient of TSV.

Table 5. Quantitative comparison with similar topology.

Reference	Ns	Nsw	NDR	ND	NC	Nlevel	TSV(×Vstep)	H Bridge	CF
									α = 0.5	α = 1	α = 1.5
[10]	2	16	16	2	4	13	34	No	8.46	11.08	13.69
[11]	2	14	11	0	2	13	39	No	7.15	10.15	13.15
[14]	1	10	8	10	5	13	59	Yes	4.81	7.08	9.35
[15]	1	14	6	6	6	13	48	Yes	4.31	6.25	8
[27]	1	10	10	4	4	13	36	No	3.54	4.92	6.31
[28]	1	12	12	4	3	13	36	No	3.76	5.15	6.53
[21]	2	14	14	2	4	13	36	No	8	10.77	13.54
[24]	1	15	15	0	3	13	35	No	3.88	5.23	6.58
[23]	1	19	18	0	4	13	40	No	4.69	6.23	7.77
[29] (one basic unit)	3	8	8	0	0	17	28	No	5.29	7.76	10.23
[30]	1	10	8	0	4	13	28	No	3	3.84	4.92
Proposed	1	10	8	4	5	13	37	No	3.5	4.92	6.34

gives information about the indexes mentioned above. It is clear that the inverter proposed in [10,11,21] uses two dc sources, and the topology in [29] needs to use three independent sources in one basic unit. Therefore, the CF value in these four papers is higher than the proposed single-source inverters. As for voltage stress, the TSVs of [14,15] are much larger than other inverters because switches in the back-end H bridge withstand the peak output voltage in these two inverters. Among the 13-level inverters, the proposed topology is for the inverter that uses the lowest number of active switches, which is only 10. The CF value of the proposed inverter is almost lower than the other counterparts. The inverter proposed in [30], indeed, has a lower CF value, but it does not have self-balance ability and uses a very complicated method to balance the capacitor voltage, increasing the cost and complexity of the control circuit. Speaking overall, the proposed topology shows superiority over other 13-level inverters.

Switching loss comparison: To highlight the feature of hybrid modulation method, a comparative analysis concerning switching loss with other 13-level inverters using high-frequency modulation is demonstrated in this section. The switching losses of the inverters were all calculated using Equation (19). In order to make the comparison fair, it was assumed that all the switches had the same parasitic capacitance, which was 500 pF. And the amplitude of the output voltage was uniformly set to be 300 V, the output frequency was set as 50 Hz, and the load was set to be 80 Ω of pure resistive load.

Figure 6 illustrates the switching loss of different 13-level inverters when the carrier frequency changes from 2 kHz to 10 kHz. It is shown in Figure 6 that the switching loss of the proposed inverter is the lowest in the whole range. Additionally, the slope of the proposed inverter is lowest, which means that the growth rate of switching loss in the proposed inverter is the slowest as carrier frequency increases.

6. Simulation and Experimental Results

6.1. Simulation Results

The proposed inverter was built in PSIM version 9.1.4.400 to verify the feasibility of the topology and modulation. The input voltage V_dc was set as 100 V. The capacitance for C_a1 and C_a2 was 1500 μF, and C₁, C₂, C₃ were chosen to be 2200 μF. The output frequency was 50 Hz, and the carrier wave frequency was 5000 Hz.

Figure 7 demonstrates the output voltage and current under the pure load condition (80 Ω) and inductive load condition (80 Ω + 50 mH), respectively. In Figure 7a, the amplitude of the output voltage v_o is 296.67 V, which is close to 300 V. Therefore, the triple boosting ability of the inverter is verified. In Figure 7b, the THD of the output voltage and current are 9.822% and 1.546%, respectively. This shows the filtering property of the inductive load.

Figure 8 illustrates the capacitor voltage of the inverter under 80 Ω load. It can be seen that the voltages of C₁, C₂, and C₃ are maintained at 100 V while voltages of C_a1 and C_a2 are maintained at 50 V. Thus, the self-voltage balance ability of the proposed inverter is proved.

6.2. Experimental Results

A 13-level inverter laboratory prototype was built in order to further verify the feasibility of the proposed topology and hybrid modulation method. The experimental setup is shown in Figure 9. TMS320F28335 was chosen as the controller, and TLP250 was selected as the gate driver. The dead time for the complementary signals was set at around 170 ns. The power switches and diodes employed CI47N65 and CI30S65D3L2, respectively. Other experimental parameters are listed in

Table 6. Experimental parameters.

Items	Value
Input voltage Vdc	50 V
Capacitance	2200 μF
Output frequency fo	50 Hz
Carrier wave frequency	10 kHz

. For S₂ and S₅, we use MOSFET with body diode in series with a diode to represent because MOSFET with body diode is more common.

Figure 10 shows the switching signals as well as the drain-source voltage (V_DS) of each semiconductor switch under the hybrid modulation method.

As for the switches S₁ and S₁′, though their maximum voltage stress is V_dc, the blocking voltage before turning on (or after turning off) is only V_dc/2. This can be substantiated by analyzing Figure 10a; for instance, in one of the frequent switching periods, S₁, marked in the figure, the voltage changes in S₁ is only 25 V. Therefore, the blocking voltage of switches in the low-voltage module is V_dc/2, which is always the minimum step voltage. For S₃, it is demonstrated in Figure 10b that among the six switching actions in one period, the blocking voltage of four of them are measured to be 50 V (V_dc), and the remaining two are 100 V (2V_dc). The situation for S₄ is completely the same as S₃. Therefore, the analysis in the switching loss part in Section 4 is verified.

The switching signals and drain-source voltage waveforms in Figure 10 prove that switches in the high-voltage module all work in a low-frequency state under the hybrid modulation method. Therefore, this hybrid modulation limits the number of high-frequency switches and reduces the switching loss significantly.

Figure 11 depicts the output waveforms of the voltage v_o and current i_o under an 80 Ω load. The modulation ratio M was set to unity. The amplitude of the output voltage was 142.8 V, which is lower than the theoretical value because of the conduction forward voltage of the switches and diodes. The root mean square (rms) value of i_o was measured to be 1.27 A. The capacitors’ voltage waveforms, as well as the ripple, are shown in Figure 12. It is clear that the voltages of C_a1 and C_a2 are maintained at 25 V, and C₁, C₂, and C₃ are kept at 50 V, so the self-balance capability of the proposed inverter is verified. The voltage ripple of C_a1 and C_a2 is less than 2 V, and the figure for other three capacitors shows a value less than 2.5 V; hence, all the capacitor voltage ripples are less than 10% of their rated voltage.

Figure 13 depicts the waveforms of the output voltage and current with an 80 Ω + 28 mH load. The peak output of the current is 1.76 A. Thus, this inverter has the ability to drive inductive load.

To explore how the modulation ratio M influences the output, the proposed inverter is tested with M = 0.7, M = 0.5, and M = 0.3 (under an 80 Ω + 28 mH load), respectively. The results are shown in Figure 14. It can be seen that as the modulation ratio reduces, the levels of the inverter decrease. The number of output levels becomes 11, 7, and 5, respectively.

A load change experiment was carried out to examine the transient response of the proposed inverter. Figure 15 illustrates the output waveforms under the condition of a sudden load change from 80 Ω to 280 Ω + 46 mH. It is clearly demonstrated in the figure that at the load change moment, the output voltage is basically uninfluenced while the amplitude of output current dramatically decreases. The RMS values of the current before and after the load change are 1.2698 A and 356.36 mA, respectively. After some time has passed from the load change, i_o becomes a sinusoidal waveform, and the output reaches its steady state again. Therefore, the proposed topology has a good transient response performance under the proposed novel hybrid modulation method.

7. Conclusions

A 13-level inverter, based on an SC technique, is proposed in this paper. The proposed topology has the advantage of a low switch count, self-voltage balance, no back-end H bridge, and triple boosting ability. Owing to its unique switching states, a novel hybrid modulation method can be applied to this inverter. By using the hybrid modulation method, the switches in the high-voltage module all work in low-frequency states, and their switching frequencies are not affected by the frequency of triangular carrier waves. As a result, the switching loss is significantly reduced. The comparison results highlight the merit of the proposed topology and modulation method. And simulation and experimental results verified the feasibility of the proposed inverter. The proposed inverter can be modulated both by HFM and FFM. Therefore, it can be applied in power-frequency occasions such as distributed generation power systems. It can also be used in high-frequency occasions by using FFM, such as a high-frequency AC system or wireless power transfer.