# Optimization-Based Capacitor Balancing Method with Customizable Switching Reduction for CHB Converters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Fundaments and Strategy

#### 2.1. Variables and Constraints

#### 2.2. Transition Commutations

#### 2.3. Objective Function for Switching Losses Reduction

#### 2.4. Integration and Interaction with Other Objectives

#### 2.4.1. Combination with DC-Link Voltage Objective

#### 2.4.2. Combination with DC-Link Ripple Reduction

- If both ${B}_{Akj}$ and ${B}_{Bkj}$ are high (relative to other benefit values), then there is a significant benefit in having a high value of ${U}_{kj}$. In the optimal solution, the module would probably be high-saturated;
- If both ${B}_{Akj}$ and ${B}_{Bkj}$ are low (i.e., if they have a big negative value), then there is a significant benefit in having a low value of ${U}_{kj}$. In the optimal solution, the module would probably be low-saturated;
- If ${B}_{Akj}$ is significantly lower than ${B}_{Bkj}$ (the opposite cannot occur), then there is a significant benefit in setting ${U}_{kj}$ to a particular voltage ${U}_{kj}^{*}$, which depends on the module’s desired active power. The module would probably modulate this voltage ${U}_{kj}^{*}$ through PWM. This third case only occurs when the power control and ripple reduction objective is selected for the corresponding module (${G}_{Pkj}\ne 0$); otherwise, ${B}_{Akj}={B}_{Bkj}$.

- Voltage control only: ${G}_{Vkj}>0;{G}_{Pkj}={G}_{Skj}=0$;
- Voltage control and ripple reduction: ${G}_{Vkj}>0;{G}_{Pkj}0;{G}_{Skj}=0$;
- Power control only (for batteries): ${G}_{Pkj}>0;{G}_{Vkj}={G}_{Skj}=0$;
- Voltage control and switching reduction: ${G}_{Vkj}>0;{G}_{Skj}0;{G}_{Pkj}=0$.

## 3. Materials and Methods

#### 3.1. Materials

#### 3.2. Methods

- Calculate ${B}_{Akj}$ and ${B}_{Bkj}$ as in (22) and (23);
- Obtain ${U}_{kj}$ as follows;

- 4.
- Update ${\delta}_{kj}$ for the next control cycle as in (26).

## 4. Tests and Results

## 5. Discussion

- Modules for reactive power compensation, whose DC-link typically includes only capacitors, can afford a higher ripple. In these modules, ${G}_{Vkj}$ should be relatively high to ensure balance, and ${G}_{Pkj}$ should be left null. ${G}_{Skj}$, which is expected to have a medium value, can be selected according to the affordable extra ripple, possibly using the estimation given by (16);
- Modules connected to photovoltaic panels cannot afford that much ripple. For these modules, ${G}_{Vkj}$ is the most important gain and should have the highest value. As long as the ripple is small, a low value of ${G}_{Skj}$ may be acceptable. If the ripple is unacceptable, then a low value of ${G}_{Pkj}$ may be used instead. It is also possible to leave both ${G}_{Skj}$ and ${G}_{Pkj}$ to 0;
- In modules with ultracapacitors, the DC-link voltage is more stable, but the ultracapacitors can suffer from the current ripple. In this case, ${G}_{Skj}$ must be null to prevent damage. ${G}_{Pkj}$ should be the dominant gain to prevent current ripple and allow the module to respond quickly to power demand. ${G}_{Vkj}$ should have a relatively low value, but it should not be null to prevent the ultracapacitors from discharging over time;
- Finally, modules with batteries are typically controlled using power or current set points instead of voltage set points. ${G}_{Pkj}$ is the appropriate gain for controlling such power or current reference. The other gains should be null.

## 6. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Schematic of the CHB topology. The figure also shows the nomenclature considered in this paper, including the sign criteria and the ordering of the subscripts.

**Figure 3.**General control scheme. The proposed upgrade is applied to the balancing method in the modulation layer.

**Figure 4.**First test results, without switching reduction or power following objectives: (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

**Figure 5.**Second test results, with small gain for switching reduction on all modules (${G}_{Skj}=0.01$): (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

**Figure 6.**Third test results, with greater gain for switching reduction on all modules (${G}_{Skj}=0.1$): (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

**Figure 7.**Fourth test results, with switching penalization on half of the modules (${G}_{Sk2}=0.1$): (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

**Figure 8.**Fifth test results, with ripple penalization on the other half of the modules (${G}_{Pk1}=0.1$): (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

**Figure 9.**Sixth test results, each phase contains one module with ripple penalization (${G}_{Pk1}=0.1$) and another with switching penalization (${G}_{Sk2}=0.1$ ): (

**a**) DC-link voltage ripple (25 V/dv) vs. time (50 ms/div); (

**b**) Modules output voltages for 2.5 grid periods.

Magnitude | Value |
---|---|

Nominal phase-to-phase RMS voltage | 400 V |

Nominal RMS phase current | 30 A |

Type of transistors | IGBT |

Phase inductance (L) | 6 mH |

$\mathrm{Modules}\mathrm{DC}-\mathrm{link}\mathrm{capacitance}({C}_{kj}\forall k,j$) | 4.1 mF |

Modules maximum DC-link voltage | 800 V |

Modulation carrier signal frequency | 2 kHz |

Control frequency | 4 kHz |

Module | Phase 1 | Phase 2 | Phase 3 |
---|---|---|---|

First | Yellow | Green | Purple |

Second | Blue | Red | Orange |

Test | Phase 1 | Phase 2 | Phase 3 | |||
---|---|---|---|---|---|---|

Module 1 | Module 2 | Module 1 | Module 2 | Module 1 | Module 2 | |

1 | 12.5 | 12.5 | 12.5 | 10 | 12.5 | 17.5 |

2 | 15 | 12.5 | 12.5 | 12.5 | 17.5 | 12.5 |

3 | 32.5 | 30 | 30 | 30 | 32.5 | 32.5 |

4 | 15 | 22.5 | 12.5 | 22.5 | 12.5 | 22.5 |

5 | 0 * | 7.5 | 0 * | 7.5 | 0 * | 7.5 |

6 | 3.75 | 15 | 2.5 | 15 | 3.75 | 12.5 |

Test | Phase 1 | Phase 2 | Phase 3 | |||
---|---|---|---|---|---|---|

Module 1 | Module 2 | Module 1 | Module 2 | Module 1 | Module 2 | |

1 | 690 | 1100 | 1200 | 810 | 835 | 875 |

2 | 780 | 740 | 750 | 815 | 960 | 690 |

3 | 820 | 610 | 610 | 770 | 605 | 870 |

4 | 1220 | 200 | 1285 | 190 | 1460 | 200 |

5 | 1980 | 780 | 1960 | 790 | 1990 | 785 |

6 | 1950 | 280 | 1940 | 230 | 1950 | 270 |

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## Share and Cite

**MDPI and ACS Style**

Galván, L.; Gómez, P.J.; Galván, E.; Carrasco, J.M.
Optimization-Based Capacitor Balancing Method with Customizable Switching Reduction for CHB Converters. *Energies* **2022**, *15*, 1976.
https://doi.org/10.3390/en15061976

**AMA Style**

Galván L, Gómez PJ, Galván E, Carrasco JM.
Optimization-Based Capacitor Balancing Method with Customizable Switching Reduction for CHB Converters. *Energies*. 2022; 15(6):1976.
https://doi.org/10.3390/en15061976

**Chicago/Turabian Style**

Galván, Luis, Pablo J. Gómez, Eduardo Galván, and Juan M. Carrasco.
2022. "Optimization-Based Capacitor Balancing Method with Customizable Switching Reduction for CHB Converters" *Energies* 15, no. 6: 1976.
https://doi.org/10.3390/en15061976