# Optimization-Based Capacitor Balancing Method with Selective DC Current Ripple Reduction for CHB Converters

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Fundaments and Strategy

#### 2.1. DC-Link Independent Voltage Control

#### 2.2. Active Power Control and Ripple Reduction

#### 2.3. Complete Linear Optimization Problem

## 3. Materials and Methods

#### 3.1. Materials

#### 3.2. Methods

#### 3.2.1. Proposed Method

- Obtain ${B}_{Akj}$ and ${B}_{Bkj}$ as in Equations (11) and (12), respectively.
- Obtain ${U}_{kj}{}^{*}$ as in Equation (5).
- Obtain ${U}_{Tk}{}^{\prime}$ as in Equation (14).
- Obtain ${U}_{Akj}$ and ${U}_{Bkj}$ by solving the LOP in Equation (16).
- Obtain ${U}_{kj}$ as in Equation (6).

#### 3.2.2. State-of-the-Art-Method

- Select the common-mode voltage.
- Distribute each phase voltage reference among the modules of that phase.

## 4. Tests and Results

#### 4.1. Permanent State

#### 4.2. Response upon a Step Reference

#### 4.3. Effect of the Voltage Gains

#### 4.4. Ripple Reduction

## 5. Discussions and Conclusions

- It can consider different voltage set points for each module, which is useful for maximum power point tracking (MPPT) on photovoltaic applications.
- It can consider power set points for some or all modules. These work better than voltage set points on modules connected to batteries, whose voltage is approximately constant with their energy.
- It can reduce the DC current ripple on some modules. On modules with ultra-capacitors, this can extend the life of the ultra-capacitors.
- It can consider different priorities on some modules, making it more adaptable to converters where modules have different applications.

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Acknowledgments

## Conflicts of Interest

## Nomenclature

Variables Notation, Meaning, and Introduction | ||

Symbol | Meaning | Definition |

${B}_{Akj}$ | Global benefit of increasing ${U}_{Akj}$ towards the total objective function | (11) |

${B}_{Bkj}$ | Global benefit of increasing ${U}_{Bkj}$ towards the total objective function | (12) |

${B}_{PAkj}$ | Benefit of increasing ${U}_{Akj}$ towards the power and ripple objective function | (8) |

${B}_{PBkj}$ | Benefit of increasing ${U}_{Bkj}$ towards the power and ripple objective function | (9) |

${B}_{Vkj}$ | Benefit of increasing ${U}_{kj}$ towards the voltage objective | (4) |

${C}_{kj}$ | DC-Link capacity of the k-th phase j-th module | Figure 1 |

$f$ | Global objective function | (10) |

${f}_{P}$ | Objective function for the power regulation and ripple reduction alone | (7) |

${F}_{V}$ | Function to measure the (pondered) quadratic DC-Link voltage deviation | (1) |

${f}_{V}$ | Objective function for DC-Link voltage regulation alone | (3) |

${G}_{Pkj}$ | Power and ripple gain for the k-th phase j-th module | (8) and (9) |

${G}_{Vkj}$ | Voltage regulation gain for the k-th phase j-th module | (1) |

${i}_{\alpha}{i}_{\beta}$ | Power-invariant α and β components of the phase currents ^{2} (^{2} The sign criteria from Figure 1 is selected for the voltages and currents there defined.) | |

${i}_{d}{i}_{q}$ | Power-invariant d and q components of the phase currents ^{2} (^{2} The sign criteria from Figure 1 is selected for the voltages and currents there defined.) | |

${i}_{k}$ | Current of the k-th phase ^{2} (^{2} The sign criteria from Figure 1 is selected for the voltages and currents there defined.) | Figure 1 |

$j$ | Subscript ^{1} indicating the module inside the phase, $j\in \left\{1,2,3\dots N\right\}$ (^{1} Subscripts other than $j$ and $k$ do not represent any numerical values.) | |

$k$ | Subscript ^{1} indicating the phase, $k\in \left\{1,2,3\right\}$ (^{1} Subscripts other than $j$ and $k$ do not represent any numerical values.) | |

$L$ | Phase inductance | Figure 1 |

$N$ | Number of modules on each phase | |

${p}_{k}^{*}$ | Balance power reference for the k-th phase ^{3} (^{3} ${p}_{k}^{*}$ and ${v}_{0}$ belong to the method from [28] and are introduced on Section 3.2.2.) | |

${P}_{kj}$ | Actual active power received by the k-th phase j-th module | |

${P}_{kj}{}^{*}$ | Desired active power received by the k-th phase j-th module | |

${U}_{Akj}$ | Positive output voltage deviation of the k-th phase j-th module from ${U}_{kj}{}^{*}$ | (6) |

${U}_{Bkj}$ | Negative output voltage deviation of the k-th phase j-th module from ${U}_{kj}{}^{*}$ | (6) |

${U}_{kj}$ | Voltage output selected for the k-th phase j-th module ^{2} (^{2} The sign criteria from Figure 1 is selected for the voltages and currents there defined.) | Figure 1 |

${U}_{kj}{}^{*}$ | Voltage output for the k-th phase j-th corresponding to its desired power | (5) |

${U}_{Tk}{}^{*}$ | Total voltage reference for the k-th phase given by the current regulator | |

${U}_{Tk}{}^{\u2019}$ | ${U}_{Tk}{}^{*}$ after discounting the voltage corresponding to the desired power | (14) |

${v}_{0}$ | Zero-sequence voltage ^{3} (^{3} ${p}_{k}^{*}$ and ${v}_{0}$ belong to the method from [28] and are introduced on Section 3.2.2.) | (17) |

${V}_{Gk}$ | Voltage ^{2} of the grid k-th phase (^{2} The sign criteria from Figure 1 is selected for the voltages and currents there defined.) | Figure 1 |

${V}_{kj}$ | Actual DC-Link voltage of the k-th phase j-th module | Figure 1 |

${V}_{kj}{}^{*}$ | Desired DC-Link voltage of the k-th phase j-th module |

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**Figure 1.**Scheme of the CHB topology. The figure also shows the nomenclature considered in this paper, including the sign criteria and the ordering of the subscripts.

**Figure 3.**General control scheme. The proposed method as well as the state-of-the-art alternative belong in the modulation layer.

**Figure 5.**DC-Link voltage ripple: (

**a**) proposed method; (

**b**) state-of-the-art alternative. The plots show voltage (25 V/div) vs. time (10 ms/div).

**Figure 6.**Modules output: (

**a**) proposed method; (

**b**) state-of-the-art alternative. The plots show 2.5 grid periods.

**Figure 7.**DC-Link voltage dynamics upon set point swap at 5 kVAr: (

**a**) proposed method; (

**b**) state-of-the-art alternative. The plots show voltage (25 V/div) vs. time (50 ms/div).

**Figure 8.**DC-Link voltage dynamics upon set point swap at 9 kVAr: (

**a**) proposed method; (

**b**) state-of-the-art alternative. The plots show voltage (25 V/div) vs. time (20 ms/div).

**Figure 9.**DC-Link voltage dynamics upon set point swap at 1 kVAr: (

**a**) proposed method; (

**b**) state-of-the-art alternative. The plots show voltage (25 V/div) vs. time (100 ms/div).

**Figure 10.**DC-Link voltage dynamics upon a reference step with different voltage gains: (

**a**) gain by phase; (

**b**) gain by module. The plots show voltage (25 V/div) vs. time (50 ms/div).

**Figure 11.**Modules DC-Link voltage when reducing ripple. The plot shows voltage (25 V/div) vs. time (50 ms/div).

Parameter | Value | Parameter | Value |
---|---|---|---|

Nominal phase-to-phase voltage | 400 V | Type of transistors | IGBT |

Nominal RMS phase current | 30 A | Maximum DC-Link voltage | 800 V |

Phase inductance (L) | 6 mH | DC-Link capacitance (C_{kj}) ^{1} | 4.1 mF |

Control frequency | 4 kHz | Modulation carrier frequency | 2 kHz |

^{1}All DC-Links have the same capacitance.

Module | Phase 1 | Phase 2 | Phase 3 |
---|---|---|---|

First | Yellow | Green | Purple |

Second | Blue | Red | Orange |

Method | Phase | Harmonic Amplitude (%) | THD (%) | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|

2nd | 3rd | 4th | 5th | 6th | 7th | 8th | 9th | 10th | 11th | |||

Proposed method | 1st | 1.0 | 1.1 | 0.8 | 2.7 | 0.4 | 1.4 | 0.3 | 0.2 | 0.2 | 0.5 | 3.6 |

2nd | 1.1 | 1.0 | 0.9 | 2.1 | 0.4 | 1.6 | 0.3 | 0.2 | 0.2 | 0.5 | 3.4 | |

3rd | 0.9 | 1.2 | 0.8 | 2.7 | 0.3 | 1.5 | 0.2 | 0.2 | 0.2 | 0.4 | 3.6 | |

State-of-the-art alternative | 1st | 1.0 | 1.0 | 0.8 | 3.0 | 0.4 | 0.9 | 0.3 | 0.2 | 0.2 | 0.3 | 3.6 |

2nd | 1.1 | 1.0 | 0.7 | 2.8 | 0.4 | 1.1 | 0.3 | 0.2 | 0.2 | 0.4 | 3.5 | |

3rd | 0.8 | 0.9 | 0.7 | 2.8 | 0.4 | 1.0 | 0.2 | 0.2 | 0.2 | 0.2 | 3.4 |

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## Share and Cite

**MDPI and ACS Style**

Galván, L.; Gómez, P.J.; Galván, E.; Carrasco, J.M.
Optimization-Based Capacitor Balancing Method with Selective DC Current Ripple Reduction for CHB Converters. *Energies* **2022**, *15*, 243.
https://doi.org/10.3390/en15010243

**AMA Style**

Galván L, Gómez PJ, Galván E, Carrasco JM.
Optimization-Based Capacitor Balancing Method with Selective DC Current Ripple Reduction for CHB Converters. *Energies*. 2022; 15(1):243.
https://doi.org/10.3390/en15010243

**Chicago/Turabian Style**

Galván, Luis, Pablo Jesús Gómez, Eduardo Galván, and Juan Manuel Carrasco.
2022. "Optimization-Based Capacitor Balancing Method with Selective DC Current Ripple Reduction for CHB Converters" *Energies* 15, no. 1: 243.
https://doi.org/10.3390/en15010243