# A Dual Rising Edge Shift Algorithm for Eliminating the Transient DC-Bias Current in Transformer for a Dual Active Bridge Converter

^{*}

## Abstract

**:**

## 1. Introduction

**No need for any measurements or parameter values:**Solutions presented in [20,21,22,23,24,26,28] incorporate relatively complex formulas, including input and output voltage measurement values and/or equivalent inductance values. This raises the computational burden of the algorithm and makes it possibly vulnerable to measurement noises and parameter identification errors (as described in [21]). Solutions presented in [25,27] do not posses this drawback, which also leads to relatively simple calculation formulas;**Power flow reversal functionality:**One of the most important advantages of the DAB topology is the bi-directional power flow capability. Hence, it is very important that the DC-bias current cancellation algorithm supports this functionality; otherwise, the full potential of the converter features cannot be utilized. Among the analyzed solutions, only [21,23,24] present experimental proofs of such a functionality. The authors of [27] also claim it, but it was not supported with experimental results;**Settling within the first half of the switching cycle during transients:**From the closed loop voltage control point of view, it is advantageous that the current waveforms (and hence, also the power flow level) settle to their steady-state as fast as possible. The algorithm presented in [20] needs several switching cycles to settle. The authors of [21,22,23,24,27] claim a settling time of one switching cycle. Only solutions provided in [25,26] provide a settling of the current waveforms within the first half of the switching cycle;**Update and calculation once per switching cycle:**Some of the algorithms, i.e., [20,21,25], require an update of pulse width modulation (PWM) control values and/or algorithm calculations twice per switching cycle. This is disadvantageous, especially when the algorithm is implemented on a microcontroller. The reason is that it requires two invocations of the interrupt service routine per switching cycle. With all the other solutions, i.e., [22,23,24,26,27,28], it is sufficient to perform the modulation-algorithm-related calculations only once per switching cycle. Thanks to this, these algorithms can be executed in the same interrupt service routine as the overlaying voltage control algorithm. Hence, these interrupts do not need to be nested, which is obviously a convenient feature for implementation;**No asynchronous operation:**This point relates to only two solutions. The algorithm presented in [24] requires an injection of an additional half switching cycle with zero voltage during power flow reversal. The solution proposed in [27] incorporates an injection of such a zero voltage period (which also has a variable duration based on the requested amount of power flow value) between each consecutive switching cycle. It introduces an asynchronous operation of the converter. With solution [24], it occurs only occasionally during power flow reversal, so its impact is not severe. On the other hand, the impact on the operation of a converter controlled with an algorithm presented in [27] is significant. Such an asynchronous operation introduces either asynchronous sampling (if it is bounded with a switching cycle) or de-synchronization of sampling in relation to switching cycle. In both situations, it makes it very hard to analyze the dynamics of such an asynchronous system. Hence, a closed loop control system synthesis can become a relatively tedious task;**Dead-time compensation:**All the analyzed solutions are derived based on the so-called simplified lossless converter model. As described in [23], this model neglects an influence of the converter blanking times (often referred to as dead times) on the converter operation. For this reason, every algorithm which does not take this effect into account is unable to perfectly compensate the DC-bias current. On the other hand, the remaining compensation error was quantified in [23], and it appears to be reasonably small enough to simply accept it. Nevertheless, the authors of [21,23] decided to introduce an additional module to their base algorithms, which compensates the dead-time related effects. These solutions are based on an analytical model of the dead-time influence on current waveforms.

## 2. Materials and Methods

#### 2.1. Steady-State Operation—Double-Sided Single Phase Shift (DSSPS) Modulation

#### 2.2. Dynamic Operation—Dual Rising Edge Shift (DRES) Algorithm

- reduced, if ${D}_{S2}\ge 0$ and $\Delta {D}_{S}\ge 0$,
- extended, if ${D}_{S2}\ge 0$ and $\Delta {D}_{S}<0$,
- extended, if ${D}_{S2}<0$ and $\Delta {D}_{S}\ge 0$,
- reduced, if ${D}_{S2}<0$ and $\Delta {D}_{S}<0$.

## 3. Results

^{TM}. The control algorithm was implemented on the microcontroller TMS320F28379D from Texas Instruments

^{TM}. The control interface presented in Figure 6 was designed by the authors’ research team.

^{TM}using the P5205A, TCP0020A, and TCP0030A probes. In order to provide the possible stable test conditions, input terminals of the converter were connected with output terminals and supplied from a laboratory DC power supply, TDK-Lambda GEN 600-2.6. A schematic of this connection is shown in Figure 7. Thanks to the setup used, the energy transmitted through the DAB converter flows in a closed loop, and the power supply only needs to cover a power demand for the losses. In order to provide comparability of the results obtained in different test scenarios, all the tests were carried out at the same voltage level of 100 V. This particular value was chosen in order not to exceed the maximal allowed current for the current probes during the most extreme test case (i.e., the power flow reversal with deactivated compensation algorithm).

## 4. Discussion

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

AC | Alternating Current |

DAB | Dual Active Bridge |

DC | Direct Current |

DRES | Dual Rising Edge Shift (algorithm) |

DSSPS | Double-Sided Single Phase Shift (modulation) |

ePWM | Enhanced Pulse Width Modulator (microcontroller peripheral) |

FE | Falling Edge |

FPGA | Field Programmable Gate Array |

PWM | Pulse Width Modulation |

RE | Rising Edge |

SST | Solid State Transformer |

SPS | Single Phase Shift (modulation) |

TPS | Triple Phase Shift (modulation) |

## Appendix A. Details of the Software Implementation

^{TM}. The general flowchart of this solution is shown in Figure A1. The PWM signals controlling the gate drivers of the transistors are generated using the enhanced pulse width modulator (ePWM) peripheral of the microcontroller [31]. Each PWM module of this peripheral can generate both the basic and negated signal. In the presented solution, each module (see ePWM1, ePWM2, ePWM3, and ePWM4 in Figure A1) controls one half-bridge of the converter. The basic signals control the upper-side transistors, and the negated signals control the lower-side transistors in each branch (compare the transistor markings ${Q}_{1}\cdots {Q}_{8}$ in Figure 1a and Figure A1). The gate drivers used work in a standard logic, i.e., the transistor is switched on if the corresponding PWM signal is in a high state.

^{TM}, i.e., Code Composer Studio (8.1.0) [32]. The control algorithm is implemented in an interrupt service routine, which is triggered at the beginning of each switching cycle. An exact timing diagram is shown in Figure A2.

**Table A1.**Configuration of bit operations performed by each ePWM module at counter = CMPA and counter = CMPB events.

Event | ePWM1 | ePWM2 | ePWM3 | ePWM4 |
---|---|---|---|---|

counter = CMPA (at count-up) | SET | CLEAR | SET | CLEAR |

counter = CMPB (at count-down) | CLEAR | SET | CLEAR | SET |

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**Figure 2.**Chosen waveforms during a steady-state operation of DAB for forward (left column) and reverse (right column) power flow direction: (

**a**) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (

**b**) the voltage across the equivalent circuit inductor, (

**c**) the primary-side (black) and secondary-side (blue) transformer currents.

**Figure 3.**Waveforms during a dynamic change of the phase shift from ${D}_{S1}=0.05$ to ${D}_{S2}=0.25$ (first two plots), and from ${D}_{S1}=0.25$ to ${D}_{S2}=0.05$ (last two plots)

**without a compensation algorithm**: (

**a**,

**c**) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (

**b**,

**d**) the primary-side transformer current calculated during transient process (red) and steady-state operation (black).

**Figure 4.**Waveforms during a dynamic change of the phase shift from ${D}_{S1}=0.05$ to ${D}_{S2}=0.25$ (first two plots), and from ${D}_{S1}=0.25$ to ${D}_{S2}=0.05$ (last two plots)

**with DRES compensation algorithm**: (

**a**,

**c**) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (

**b**,

**d**) the primary-side transformer current calculated during transient process (red) and steady-state operation (black).

**Figure 5.**Block diagram of the proposed algorithm: ${D}_{S}$ is a phase shift value; $\Delta {D}_{S}$ is a change of phase shift value between the current and the previous switching cycle; ${t}_{corr}^{*}$ is a correction time; ${t}^{*}$ are the resulting time instants of the rising (RE) and falling (FE) voltage edges for the primary-side (${H}_{1}$) and secondary-side (${H}_{2}$) bridges.

**Figure 8.**Experimental results during a step change of the phase shift ${D}_{S}$ from value 0 to $0.25$ and then back from $0.25$ to 0: (

**a**) without a compensation algorithm, (

**b**) with DRES compensation algorithm.

**Figure 9.**Experimental results during a step change of the phase shift ${D}_{S}$ from value 0 to $-0.25$ and then back from $-0.25$ to 0: (

**a**) without a compensation algorithm, (

**b**) with DRES compensation algorithm.

**Figure 10.**Experimental results during a step change of the phase shift ${D}_{S}$ from value $-0.25$ to $0.25$ and then back from $0.25$ to $-0.25$: (

**a**) without a compensation algorithm, (

**b**) with DRES compensation algorithm.

**Figure 11.**Experimental results during a linear frequency sweep of the phase shift ${D}_{S}$ with an amplitude of 0.25 and a frequency changing from 0 kHz to 5 kHz: (

**a**) without a compensation algorithm, (

**b**) with DRES compensation algorithm.

Solution | Meas. & Parameter Free | No Conditional Branches | Power Flow Reversal | Settl. in Half Cycle | Update and Calc. Once per Cycle | No Asynch. Operation | Dead-Time Compensation |
---|---|---|---|---|---|---|---|

[20] | − | + | − | − | − | + | − |

[21] | − | + | + | − | − | + | + |

[22] | − | + | − | − | + | + | − |

[23] | − | − | + | − | + | + | + |

[24] | − | − | + | − | + | − | − |

[25] | + | + | − | + | − | + | − |

[26] | − | + | − | + | + | + | − |

[27] | + | − | + * | − | + | − | − |

[28] | − | $+/-$ ** | − | − | + | + | − |

This paper/Dual Rising Edge Shift Algorithm | + | + | + | + | + | + | − |

Name | Symbol | Value | Unit |
---|---|---|---|

Switching frequency | ${f}_{swt}$ | 40 | kHz |

Commutation blanking time | ${T}_{dead}$ | $0.5$ | $\mathsf{\mu}\mathrm{s}$ |

Drain-Source on-state resistance of MOSFETs | ${R}_{DSon}$ | 25 | $\mathrm{m}\Omega $ |

Inductance of the equivalent circuit | ${L}_{eq}$ | $136.7$ | $\mathsf{\mu}\mathrm{H}$ |

Inductance of the auxiliary inductor | ${L}_{aux}$ | $117.7$ | $\mathsf{\mu}\mathrm{H}$ |

Input and output capacitance | ${C}_{1},\phantom{\rule{3.33333pt}{0ex}}{C}_{2}$ | 200 | $\mathsf{\mu}\mathrm{F}$ |

Transformer turns ratio | ${n}_{t}$ | $7/4$ | − |

Transformer magnetizing inductance | ${L}_{\mu}$ | $2.4$ | mH |

Primary-side transformer leakage inductance | ${L}_{\sigma 1}$ | $9.5$ | $\mathsf{\mu}\mathrm{H}$ |

Secondary-side transformer leakage inductance | ${L}_{\sigma 2}$ | $3.1$ | $\mathsf{\mu}\mathrm{H}$ |

Primary-side transformer resistance | ${R}_{1}$ | $21.6$ | $\mathrm{m}\Omega $ |

Primary-side transformer resistance | ${R}_{2}$ | $12.4$ | $\mathrm{m}\Omega $ |

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**MDPI and ACS Style**

Gierczynski, M.; Grzesiak, L.M.; Kaszewski, A.
A Dual Rising Edge Shift Algorithm for Eliminating the Transient DC-Bias Current in Transformer for a Dual Active Bridge Converter. *Energies* **2021**, *14*, 4264.
https://doi.org/10.3390/en14144264

**AMA Style**

Gierczynski M, Grzesiak LM, Kaszewski A.
A Dual Rising Edge Shift Algorithm for Eliminating the Transient DC-Bias Current in Transformer for a Dual Active Bridge Converter. *Energies*. 2021; 14(14):4264.
https://doi.org/10.3390/en14144264

**Chicago/Turabian Style**

Gierczynski, Michal, Lech M. Grzesiak, and Arkadiusz Kaszewski.
2021. "A Dual Rising Edge Shift Algorithm for Eliminating the Transient DC-Bias Current in Transformer for a Dual Active Bridge Converter" *Energies* 14, no. 14: 4264.
https://doi.org/10.3390/en14144264