A Dual Rising Edge Shift Algorithm for Eliminating the Transient DC-Bias Current in Transformer for a Dual Active Bridge Converter

: This paper deals with a well-known problem of the transient DC-bias current occurring during a phase shift transition in dual active bridge (DAB) DC/DC converters. This phenomenon, if not compensated, can cause damage to the converter or deteriorate its performance. One aim of this paper is to present a solution which allows for the elimination of the undesired transient DC-bias component in current waveforms. This solution is the dual rising edge shift (DRES) compensation algorithm. It provides a very simple implementation and fast settling time within the ﬁrst half of a switching period. Moreover, the solution is independent on any measurements or system parameter values. It is based on the double-sided single phase shift (DSSPS) modulation, which is described in detail along with a converter model in steady-state. Then, the mechanisms leading to the transient DC-bias are explained, and the compensation algorithm is derived. The performance of the algorithm has been tested using a laboratory prototype. A comprehensive set of tests, involving rapid step changes in power ﬂow and frequency sweep, are provided. Finally, the features of the proposed algorithm are brieﬂy discussed.


Introduction
The dual active bridge (DAB) is a very versatile DC/DC converter topology.It allows for bidirectional power flow, galvanic isolation, and both buck and boost functionality.This operational flexibility, together with a high efficiency and a high-power density, makes it an attractive solution for a very wide range of applications [1], e.g., power conversion in DC grids, solid-state transformers (SST), automotive applications, energy storage systems, and aerospace applications.
The foundations of this topology were established around the late 1980s and early 1990s [2][3][4].Unfortunately, at this time, the power electronics technology was not mature enough to enable the realization of DAB converters with acceptable efficiencies [5].Thus, extensive research in this field was delayed for almost two decades since the primal release of the DAB concept.This correlated with advances in power electronic devices and magnetic materials, which were crucial to make DAB converters suitable for high-powerdensity power conversion systems [5].
An occurrence of the DC-bias current in DAB converters is a well-known and widely documented fact [11,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28].This phenomenon can lead to a saturation of the auxiliary inductor or the transformer magnetic circuit, which in turn can cause a serious fault of power electronic devices due to an overcurrent [11].It can also lead to an emergency shut down and/or rise of power losses in different parts of the system.Eliminating of the DC-bias current is thus one of the most important issues to be solved in order to design a DAB converter of industrial quality.From this point of view, it is also preferred to apply algorithmic-based solutions to this problem over hardware-based ones, as they are more cost-effective and do not require an over-dimensioning of the system elements, i.e., magnetic cores and power electronic devices.
It is also important to distinguish between two different types of the discussed problem: a steady-state DC-bias current and a transient DC-bias current.Both of them have slightly different origins; thus, the countermeasures needed to eliminate them have to be of a different nature, too.
The steady-state DC-bias current is primarily caused by some imperfections in hardware, which lead to asymmetries in the AC voltage waveforms produced by both bridges.These asymmetries can be caused by differences in turn-on and turn-off times of semiconductor switches, propagation times of gate control signals, voltage drop characteristics of semiconductor devices, etc.There are several solutions allowing this type of DC-bias to be mitigated that are reported in the literature [14][15][16][17][18][19].All of them are based on a measurement of the current averaged over at least one switching cycle, which in turn limits an effectively realizable bandwidth of the DC-bias elimination process.
On the other hand, an occurrence of the transient DC-bias current is inherently connected with an applied control scheme.Most of the modulation strategies developed for the DAB converters are primarily designed based on a steady-state operation analysis.In an ideal case, they ensure a zero volt-time product over a switching period but only during a steady-state operation.Applying the same voltage waveforms during a transition process does not ensure this premise anymore, causing some serious rise of the current when a transferred power is changed.This rise occurs relatively quickly (within a fraction of a switching period); therefore, the only way to avoid it is to apply countermeasures a priori to its occurrence.Thus, the reported solutions to this problem focus mainly on an appropriate modification of the SPS modulation scheme during the transition process [20][21][22][23][24][25][26][27][28] (the solution presented here is based on the same idea).
In [20,21], model predictive controllers are proposed.They rely on current and voltage measurements, as well as on some system parameter values.The authors of [22,23] propose shifting three voltage edges based on an a priori calculation.One of the solutions given in [24] incorporates a single rising voltage edge shift based on two voltage measurements, but power flow reversal functionality has not been presented.The second solution given in the same paper possesses this functionality, but it uses a much more complex dual phase shift (DPS) control, including a zero voltage state.It also requires an injection of a zero voltage for a half cycle during the power flow reversal.In [25], the authors propose a measurement-free solution, where four switching angles are adjusted, and the control variables are updated twice per switching cycle.Other solutions using a zero voltage injection are also known, but the power flow reversal operation is either not presented [26], or it needs a tedious procedure incorporating a change of the switching cycle duration [27].In [28], four different solutions are analyzed.They are based on manipulating various pairs of voltage waveform edges.Algorithm calculations require two voltage measurements, and the power flow reversal functionality has not been demonstrated.
The literature also reports some attempts to solve the transient DC-bias problem using the much more complex triple phase shift (TPS) modulation [29,30].The solution presented in [29] introduces an additional time period of various duration between switching cycles every time the power flow value is changed.This algorithm is hardly applicable on microcontrollers and probably imposes the usage of an FPGA device.The algorithm from [30] is very complex: it requires measurement-based complex calculations and switching between operational modes.Additionally, it was developed only for a positive power flow direction.
An algorithm proposed in this paper is an alternative to the above-mentioned solutions [20][21][22][23][24][25][26][27][28].It is an extension of the SPS modulation scheme, allowing for the elimination of a transient DC-bias current in transformer windings.This solution incorporates an appropriate shift of the rising edges for both primary-and secondary-side AC voltages during transition process.The calculation formula is very simple and does not require any measurements or system parameter values.
All the algorithms presented in [20][21][22][23][24][25][26][27][28] have different strengths and weaknesses.Based on the detailed analysis of them, the authors identified some positive features, which can be used to compare their usefulness.Thus, the potentially best algorithm should have the following features:

•
No need for any measurements or parameter values: Solutions presented in [20][21][22][23][24]26,28] incorporate relatively complex formulas, including input and output voltage measurement values and/or equivalent inductance values.This raises the computational burden of the algorithm and makes it possibly vulnerable to measurement noises and parameter identification errors (as described in [21]).Solutions presented in [25,27] do not posses this drawback, which also leads to relatively simple calculation formulas; • No conditional branches: Algorithms presented in [23,24,27] use conditional branches, which raises the complexity of implementation.Other solutions, i.e, [20][21][22]25,26], do not need them.Lack of conditional-based algorithm execution is an advantage for implementation; • Power flow reversal functionality: One of the most important advantages of the DAB topology is the bi-directional power flow capability.Hence, it is very important that the DC-bias current cancellation algorithm supports this functionality; otherwise, the full potential of the converter features cannot be utilized.Among the analyzed solutions, only [21,23,24] present experimental proofs of such a functionality.The authors of [27] also claim it, but it was not supported with experimental results; • Settling within the first half of the switching cycle during transients: From the closed loop voltage control point of view, it is advantageous that the current waveforms (and hence, also the power flow level) settle to their steady-state as fast as possible.The algorithm presented in [20] needs several switching cycles to settle.The authors of [21][22][23][24]27] claim a settling time of one switching cycle.Only solutions provided in [25,26] provide a settling of the current waveforms within the first half of the switching cycle; • Update and calculation once per switching cycle: Some of the algorithms, i.e., [20,21,25], require an update of pulse width modulation (PWM) control values and/or algorithm calculations twice per switching cycle.This is disadvantageous, especially when the algorithm is implemented on a microcontroller.The reason is that it requires two invocations of the interrupt service routine per switching cycle.With all the other solutions, i.e., [22][23][24][26][27][28], it is sufficient to perform the modulation-algorithmrelated calculations only once per switching cycle.Thanks to this, these algorithms can be executed in the same interrupt service routine as the overlaying voltage control algorithm.Hence, these interrupts do not need to be nested, which is obviously a convenient feature for implementation; • No asynchronous operation: This point relates to only two solutions.The algorithm presented in [24] requires an injection of an additional half switching cycle with zero voltage during power flow reversal.The solution proposed in [27] incorporates an injection of such a zero voltage period (which also has a variable duration based on the requested amount of power flow value) between each consecutive switching cycle.
It introduces an asynchronous operation of the converter.With solution [24], it occurs only occasionally during power flow reversal, so its impact is not severe.On the other hand, the impact on the operation of a converter controlled with an algorithm presented in [27] is significant.Such an asynchronous operation introduces either asynchronous sampling (if it is bounded with a switching cycle) or de-synchronization of sampling in relation to switching cycle.In both situations, it makes it very hard to analyze the dynamics of such an asynchronous system.Hence, a closed loop control system synthesis can become a relatively tedious task; • Dead-time compensation: All the analyzed solutions are derived based on the socalled simplified lossless converter model.As described in [23], this model neglects an influence of the converter blanking times (often referred to as dead times) on the converter operation.For this reason, every algorithm which does not take this effect into account is unable to perfectly compensate the DC-bias current.On the other hand, the remaining compensation error was quantified in [23], and it appears to be reasonably small enough to simply accept it.Nevertheless, the authors of [21,23] decided to introduce an additional module to their base algorithms, which compensates the dead-time related effects.These solutions are based on an analytical model of the dead-time influence on current waveforms.
For clarity, all the above-mentioned features are presented in tabular form in Table 1.For comparison, the features of the algorithm presented in this paper are shown in the last row.It can be identified that this algorithm combines almost all the possible advantages of the other solutions with only one exception, i.e., it does not provide compensation of the dead-time related effects.

Update and Calc. Once per Cycle
No Asynch.Operation This paper is organized as follows: after this introductory part, Section 2.1 explains the operation of the proposed algorithm in steady-state.Section 2.2 analyzes mechanisms leading to the transient DC-bias current phenomenon and introduces the proposed compensation algorithm.Experimental results are given in Section 3.They are discussed in Section 4. Finally, the presented content is summarized in Section 5.

Steady-State Operation-Double-Sided Single Phase Shift (DSSPS) Modulation
An operation of the converter in steady-state is analyzed first.The basic DAB circuit is shown in Figure 1a where: Q 1 . . .Q8 are transistors of the MOSFET type; V 1 and V 2 are the primary-and the secondary-side DC voltages (V), which are assumed constant during a steady-state operation; v H1 (t) and v H2 (t) are the AC voltages of primary-and secondaryside H-bridges (V); i L1 (t) and i L2 (t) are the primary-and secondary-side transformer currents (A); L aux is an inductance of the auxiliary inductor (H); and n 1 and n 2 are numbers of turns at primary and secondary transformer sides.It is a common practice to describe the operation of a DAB converter with a simplified equivalent circuit shown in Figure 1b [10][11][12].The same approach is used here for a derivation of the presented algorithm.In this model, both H-bridges are replaced with ideal voltage sources; the transformer is assumed as ideal with only series leakage inductances (magnetizing inductance is neglected); all parasitic resistances are neglected; and secondary side quantities are referred to the primary side of the transformer.With all the above assumptions, the equivalent DAB circuit can be described with following equations: where v , H2 (t) is the secondary-side AC voltage referred to the primary side of the transformer (V); L eq is an equivalent circuit inductance, which is referred to the primary side (H); L σ1 and L σ2 are the primary-and secondary-side series leakage inductances of the transformer (H); L σ2 is secondary-side leakage inductance referred to the primary side (H); n t is the turns ratio of the transformer; and v L (t) is voltage across the equivalent circuit inductor (V).
In SPS modulation, both H-bridges are controlled with a constant duty cycle of 50%, and power flow is controlled by adjusting the phase shift between the resulting square wave AC voltages.In this paper, the phase shift D S is expressed in units of time normalized by a switching period: where t * is a normalized time; t is an absolute time (s); and T swt is a switching period (s).
With such a definition, the value D s = 0.25 corresponds to a phase shift angle of 90 • (see Figure 2a).The phase shift D S can be then defined as: where ϕ is the phase shift expressed in degrees ( • ).The basic SPS algorithm description does not unambiguously define how exactly the switching instants should be placed in time (relative to the switching period).This modulation scheme thus leaves some freedom of choice for implementation, but this decision can be crucial for a dynamic operation of the converter.The solution presented here is a variation of the double-sided single phase shift (DSSPS) modulation scheme [22].It assumes that phases of both primary-and secondary-side voltage waveforms are adjusted in such a way that they are shifted symmetrically with regard to the center of the switching cycle.With such a definition, time instants of rising and falling voltage edges for both bridges (primary H 1 and secondary H 2 ) can be calculated as follows: The rising voltage edge for the bridge H 1 (8) occurs when the transistors Q 1 , Q 4 are being switched ON and the transistors Q 2 , Q 3 are being switched OFF (see Figure 1a for numeration of each transistor).The falling voltage edge (10) occurs when the transistors Q 1 , Q 4 are being switched OFF and the transistors Q 2 , Q 3 are being switched ON.It is analogous for the H 2 bridge.The rising voltage edge (9) occurs when the transistors Q 5 , Q 8 are being switched ON and the transistors Q 6 , Q 7 are being switched OFF.The falling voltage edge (11) occurs when the transistors Q 5 , Q 8 are being switched OFF and the transistors Q 6 , Q 7 are being switched ON.
The resulting AC voltage waveforms for both power flow directions have been presented in Figure 2a.Based on them, a voltage across the equivalent circuit inductor can be determined with (5) (Figure 2b).Solving Equation ( 5) and assuming a symmetry of the current waveforms in steady-state, the expressions for instantaneous values of the current i L1 (t) at the beginning of a switching cycle (I 0 ), as well as at switching instants (I 1 and I 2 ), can be determined as [12]: ) where I N is a base current (A); f swt is a switching frequency (Hz); and k u is a voltage gain of the converter.With Equations ( 1) and ( 12)-( 16), the waveforms of both transformer currents during the steady-state operation are fully defined.

Dynamic Operation-Dual Rising Edge Shift (DRES) Algorithm
In this Section, the dynamic DAB operation is analyzed using the same simplified equivalent circuit as in the steady-state.It is assumed that the dynamics of changes in the interface voltages V 1 and V 2 is negligibly slow relative to a switching cycle duration.Hence, these voltages are considered constant in the analysis.
In Figure 3, waveforms during a step change of the phase shift D S are presented.In the first switching cycle, the phase shift equals D S1 , and in the second cycle it rapidly changes to D S2 .The plots (a) and (b) correspond to a positive change of the phase shift (expressed as ∆D S = D S2 − D S1 ).This means that the transmitted power rises.On the other hand, the plots (c) and (d) correspond to an opposite situation (negative ∆D S and drop in the transmitted power).In both situations, the phase shift values are positive, so all the plots depict a case of the forward power flow direction.
The waveforms of the primary-side transformer currents, which are presented in Figure 3b,d, were calculated in two different ways.The first waveform (plotted in red) was calculated by solving Equation ( 5) continuously, assuming that the current at the beginning of the switching cycle equals the current at the end of the previous cycle.The second waveform (plotted in black) corresponds to the steady-state model presented in the previous section.As the instantaneous current values at the beginning and at the end of the switching cycle depend on the phase shift value in steady-state, the resulting waveforms are discontinuous.
As the equivalent DAB circuit consists of only an inductor and voltage source, the current slopes during a transient process are the same as in a steady-state, but instantaneous current values at the beginning of a switching period are different.Thus, a change in the phase shift introduces a DC-bias current.Its value is equal to a difference in the initial current values calculated for the different phase shift values as follows: Hence, both a sign and a value of the DC-bias current depend on a change of the phase shift between two switching periods.The above discussion was carried out based on the simplified DAB model, but in practice, there exist some parasitic resistances in the circuit.Hence, in reality, the DC-bias decays exponentially with time, as the magnetic energy stored in inductances is being dissipated at these resistances.It can be clearly observed based on the experimental results presented in Section 3.
The basic idea of the algorithm proposed in this paper is to appropriately manipulate time instants of rising voltage edges for both bridges during a transition process.Hence, a proposed name for this algorithm is the dual rising edge shift (DRES) compensation algorithm.This manipulation, if done correctly, can compensate the mechanisms leading to the transient DC-bias current and prevent it from occurring.
For the sake of clarity, let us call a time interval between the rising voltage edges the 'dominant interval'.This term should point out that a current slope in this interval is always greater than in the adjacent intervals (as the equivalent inductor voltage v L (t) in this interval is the sum of the primary-and secondary-side peak voltages).Let us also observe that the shifting of the rising voltage edges causes a reduction or an elongation of the dominant interval duration at the expense of the adjacent intervals' duration.As the current slope in the dominant interval is always greater than in adjacent ones, lengthening of this interval introduces a positive DC-bias current.On the other hand, shortening of this interval introduces a negative DC-bias current.The direction of the corrective shifts for rising edges should thus be chosen in such a way that it introduces a DC-bias with an opposite direction to the effect of the phase shift change described with (17).The appropriate direction of the shifts (meeting this rule) is marked with reference arrows in Figure 3b,d.
It should be noted that the above analysis was carried out only for the forward power flow direction.The same reasoning should be repeated for the reverse power flow direction.The conclusions of such an analysis are that depending on the situation, the dominant interval duration should be: Incorporating this into the modulation algorithm results in following formulas for the time instants of particular voltage edges: where t * corr (k) is a correction time; ∆D S (k) is a change of phase shift value between the current and the previous switching cycle; and k is a number of the switching cycle, in which the calculated control values are applied.
Expressions for time instants of the falling edges remained unchanged in comparison to the basic modulation algorithm-compare expressions (10) and (11) with (20) and (21).The only change occurs in the first two equations, i.e., (18) and (19), because the rising voltage edges should be appropriately shifted by an amount of the correction time t * corr .According to Equations ( 22)-( 24), the sign of the correction time should be the same as the direction of the phase shift change between switching cycles.Together with expressions (18) and (19), this assures that the duration of the dominant interval is properly reduced or extended according to the rules given a few paragraphs prior.For a positive phase shift value (D S (k) > 0), the rising voltage edge for the H 1 bridge leads to the rising voltage edge for the H 2 bridge.Hence, injection of the correction time according to ( 18) and ( 19) brings both rising edges closer to each other (H 1 is delayed and H 2 is sped up), and the dominant interval duration is reduced.For a negative phase shift value (D S (k) < 0), the situation is the opposite.The rising edge of the H 2 bridge voltage occurs first, and the same operation (at positive phase shift change) moves both rising edges away from each other.Hence, the dominant interval duration is extended.The same reasoning can be repeated for a negative change direction of the phase shift (∆D S (k) < 0).
An operation of this algorithm is presented in Figure 4.In order to allow for an easy comparison, the waveforms were calculated for the same cases as in Figure 3 correction time t * corr was chosen in such a way that the transient current waveforms (red) converge to their counterparts calculated with the steady-state model, Equations ( 12)-( 16).
The last missing part of the compensation algorithm is a formula for the correction time calculation.In order to derive it, let us observe that in steady-state, an instantaneous current value in the middle of the switching cycle is the same as at the beginning of the cycle, but with an opposite sign (see values −I 0 (D S2 ) in Figure 4b,d).Hence, a correction time should be calculated in such a way that the instantaneous current value in the transient process equals −I 0 (D S2 ) in the middle of the switching cycle.The instantaneous current in the middle of the switching cycle during transience can be expressed as: ) ) where ∆ 1 , ∆ 2 , and ∆ 3 are the current increases in consecutive time intervals, where the current is piece-wise linear.Equating the ( 25) with a target instantaneous value of −I 0 (D S2 ) (see Equation ( 12)) and solving the obtained equation with regard to the correction time results in: Repeating this calculation for an opposite power flow direction leads to an exact same formula, which ends the derivation of the compensation algorithm.It should be noted that Equation (29) meets the conditions (23) and (24) imposed on the sign of the correction time.Hence, Equation ( 29) can be implemented directly without any additional conditional statements.
The block diagram of the proposed algorithm is shown in Figure 5.It can be clearly seen that the computational overhead due to the compensation algorithm is pretty minimal.The simplicity of the whole modulation algorithm allows it to be implemented on any modern microcontroller owning a PWM peripheral.
It should also be mentioned that the proposed algorithm was derived based on the same simplified DAB model as the solutions presented in [20][21][22][23][24][25][26][27][28].Hence, the performance of all the algorithms (including the one presented here) is limited by the simplifying assumptions described in Section 2.1.In particular, parasitic resistances and an effect of commutation blanking times (which are present in a real system) can deteriorate the precision of the used model [23].the DRES compensation algorithm . Block diagram of the proposed algorithm: D S is a phase shift value; ∆D S is a change of phase shift value between the current and the previous switching cycle; t * corr is a correction time; t * are the resulting time instants of the rising (RE) and falling (FE) voltage edges for the primary-side (H 1 ) and secondary-side (H 2 ) bridges.

Results
The feasibility of the proposed solution was tested experimentally.The laboratory setup is shown in Figure 6, and the system parameters are listed in Table 2.Both H-bridges were built based on the SiC-based MOSFET power modules CCS050M12CM from CREE TM .The control algorithm was implemented on the microcontroller TMS320F28379D from Texas Instruments TM .The control interface presented in Figure 6  The details of the implementation are described in Appendix A. The measurements were carried out with the MSO58 oscilloscope from Tektronix TM using the P5205A, TCP0020A, and TCP0030A probes.In order to provide the possible stable test conditions, input terminals of the converter were connected with output terminals and supplied from a laboratory DC power supply, TDK-Lambda GEN 600-2.6.A schematic of this connection is shown in Figure 7. Thanks to the setup used, the energy transmitted through the DAB converter flows in a closed loop, and the power supply only needs to cover a power demand for the losses.In order to provide comparability of the results obtained in different test scenarios, all the tests were carried out at the same voltage level of 100 V.This particular value was chosen in order not to exceed the maximal allowed current for the current probes during the most extreme test case (i.e., the power flow reversal with deactivated compensation algorithm).The first three tests are designed to demonstrate system behavior during step changes in the phase shift value D S .Each test covers two steps.During the test presented in Figure 8, the transmitted power changes from zero (D S = 0) to the maximal value in the forward direction (D S = 0.25), and then back to zero.
The test presented in Figure 9 is analogous to the previous one, but the maximal power flows in the reverse direction (D S = −0.25).The third test (Figure 10) incorporates the most extreme possible step changes, i.e., from the maximal power flowing in the reverse direction (D S = −0.25) to the maximal power in the forward direction (D S = 0.25), and then back in the reverse direction.All the tests were conducted twice: with the deactivated (plots (a)) and activated (plots (b)) DRES compensation algorithm.
An additional test was conducted in order to prove the applicability of the DRES algorithm in closed-loop control systems.In such applications, the phase shift value is changed continuously with various dynamics by a controller.These conditions can be indirectly simulated using a frequency sweep test.The test circuit is exactly the same as for the previous cases (see Figure 7).The phase shift waveform D S has the shape of a sine function, with a constant amplitude of 0.25 and a variable frequency rising linearly with time from 0 kHz to 5 kHz.This allows the system behavior under many different frequencies to be covered in a single test.The results of such a test are presented in Figure 11.

Discussion
Let us analyze the system behavior without the compensation algorithm first (see Figures 8a, 9a and 10a).It is clearly visible that the transient DC-bias current occurs in both transformer currents (i.e., i L1 and i L2 ) and decays exponentially with time.This behavior was explained in Section 2.2 and fully matches with the theory.It should be emphasized that the peak current values during the transient processes are much higher than in the steady-state, which is the main motivation to compensate the DC-bias.
It is also clearly visible that with the compensation algorithm activated (see Figures 8b, 9b and 10b)), the system behavior is drastically improved.Peak current values during the transients are reduced to almost the same values as in the steady-state.Hence, the feasibility of the proposed solution is positively verified during all the possible types of the step changes, including the reversal of power flow direction with extreme values.
The results of the frequency sweep test are similar (see Figure 11).It can be observed that without DC-bias compensation (Figure 11a), the current envelope rises with frequency.After the activation of the compensation algorithm, this behavior is improved (Figure 11b).The current envelopes are constant and the peak values are comparable to the ones obtained in the steady-state.In the authors' opinion, these results are satisfactory and can serve as a final proof of the algorithm's viability.
The presented algorithm has many advantages.The proposed implementation is very comprehensive and does not need any conditional based changes, as opposed to the solutions presented in [23,24,27].It is also based on a very simple formula, which is independent on the voltage measurements or the equivalent inductance value (as opposed to [20][21][22][23][24]28]).Hence, it is robust against measurement noises and parameter identification errors.It also provides a very fast settling time within the first half of the switching cycle (as opposed to [20][21][22][23][24]27,28]).The power reversal functionality was demonstrated as well (which is not the case for [20,22,25,26,28]).

Conclusions
An algorithm for eliminating the transient DC-bias current in the transformer for DAB converters was presented.First, a steady-state modulation scheme was introduced.It is a relatively rare variation of the SPS modulation, which assumes that both primaryand secondary-side voltage waveforms are changed symmetrically during the transition process.Next, the operation of the converter during a transient process was analyzed.Based on this analysis, the DRES compensation algorithm was proposed and derived.It incorporates an appropriate manipulation of the time instants for the rising voltage edges.
The performance of the proposed solution was comprehensively tested with a laboratory prototype.The feasibility of the algorithm was proven based on all six possible types of step changes in power flow, including the reversal of power flow direction.These step tests were performed for the most extreme possible phase shift values.Additionally, a frequency sweep test was conducted.Based on this, it was indirectly proven that the algorithm can be also applied in closed-loop control systems.
The main advantage of the presented solution is the extreme simplicity of the implementation.This can clearly be seen based on the exemplary implementation presented in Appendix A. In comparison with other solutions (see Section 4 for details), it does not need any system parameters or measurements, although it offers the best of their combined functionality (bi-directional power flow, including reversal and fast settling time within a half switching cycle).Hence, the presented solution is a promising alternative to all the mentioned proposals from the literature.The counters of each ePWM module are synchronized with each other and configured in the count up-down mode.This means that the counter first counts up from zero to a target value, and then it counts back down to zero.The target counter value is set to 1250, so one switching period lasts for 2500 clock ticks.The PWM generation clock runs with a frequency of 100 Mhz, which results in a switching period of 25 µs (40 kHz).When the calculations performed by a control code run in the interrupt service routine are finished, the calculated values for the PWM control are first stored in the so-called shadow registers.These values are moved into the active PWM control registers first at the beginning of the next switching cycle.This is needed because the PWM setup should not change during a switching cycle.
The PWM signals for each module are generated based on two events: the counter reaches the CMPA value at counting up or the counter reaches the CMPB value at counting down.The values CMPA and CMPB can be set independently for each ePWM module, and which bit operations should be performed at each event can also be flexibly configured.The configuration used is shown in Table A1.Hence, the task of the modulation algorithm is to actually calculate values CMPA and CMPB for each ePWM module.It is performed within the 'setPwm_SPSMOD' function (see Figure A1).The requested phase shift value D S,req is calculated by an application software module (described later in this section) and passed to this function via the 'PwmSPSMod' structure as variable 'PhShftNrmlzd' (a definition of this structure is shown in Figure A3).The code of the modulation algorithm, including the DRES algorithm for a DC-bias current cancellation, is shown in Figure A4.This code performs mathematical operations described with Equations ( 18)- (24) and shown in the block diagram in Figure 5.The value 625 written to both the CMPA and CMPB registers of each module corresponds to a switching time of t * = 0.25 for a rising voltage edge and t * = 0.75 for a falling voltage edge of each bridge.These values should be treated as an initial setup corresponding to a phase shift value equal to zero.If the occurrence of a rising edge for either of the bridges should be shifted to the left on the time axis, the corresponding phase shift value (expressed in clock ticks) should be subtracted from the value 625 and written in the CMPA register.If the occurrence of a falling voltage should be shifted to the left, an opposite operation should be done, i.e., the corresponding phase shift value should be added to the value 625 and written in the CMPB register.This is performed in lines 79-83 of the function code (see Figure A4).
The modulation function is invoked within an application code, which allows a requested phase shift signal of various waveform types to be generated (see generation block in Figure A1).During the experimental tests presented in Section 3, the rectangular wave and frequency sweep options were used.Parts of the code for this function generator are shown in Figures A5 and A6.

Figure 2 .
Figure 2. Chosen waveforms during a steady-state operation of DAB for forward (left column) and reverse (right column) power flow direction: (a) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (b) the voltage across the equivalent circuit inductor, (c) the primaryside (black) and secondary-side (blue) transformer currents.

Figure 3 .
Figure 3. Waveforms during a dynamic change of the phase shift from D S1 = 0.05 to D S2 = 0.25 (first two plots), and from D S1 = 0.25 to D S2 = 0.05 (last two plots) without a compensation algorithm: (a,c) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (b,d) the primary-side transformer current calculated during transient process (red) and steady-state operation (black).

Figure 4 .
Figure 4. Waveforms during a dynamic change of the phase shift from D S1 = 0.05 to D S2 = 0.25 (first two plots), and from D S1 = 0.25 to D S2 = 0.05 (last two plots) with DRES compensation algorithm: (a,c) AC voltages of the primary-side (black) and secondary-side (blue) bridges, (b,d) the primary-side transformer current calculated during transient process (red) and steady-state operation (black).

Figure 6 .
Figure 6.View of the laboratory setup.

Figure 7 .
Figure 7. Schematic of a circuit used for the experiments.

Figure 8 .
Figure 8. Experimental results during a step change of the phase shift D S from value 0 to 0.25 and then back from 0.25 to 0: (a) without a compensation algorithm, (b) with DRES compensation algorithm.

Figure 9 .
Figure 9. Experimental results during a step change of the phase shift D S from value 0 to −0.25 and then back from −0.25 to 0: (a) without a compensation algorithm, (b) with DRES compensation algorithm.

Figure 10 .
Figure 10.Experimental results during a step change of the phase shift D S from value −0.25 to 0.25 and then back from 0.25 to −0.25: (a) without a compensation algorithm, (b) with DRES compensation algorithm.

Figure 11 .
Figure 11.Experimental results during a linear frequency sweep of the phase shift D S with an amplitude of 0.25 and a frequency changing from 0 kHz to 5 kHz: (a) without a compensation algorithm, (b) with DRES compensation algorithm.

Figure A3 .
Figure A3.Definition code of the structure used for the modulation algorithm control.

Figure A4 .
Figure A4.Code of the modulation algorithm.

Figure A5 .
Figure A5.Code for a rectangular wave generator of the phase shift signal.

Figure A6 .
Figure A6.Code for a frequency sweep generator of the phase shift signal.

Table 1 .
Comparison of different solutions for the DC-bias cancellation problem.

Table 2 .
Selected parameters of the laboratory prototype.

Table A1 .
Configuration of bit operations performed by each ePWM module at counter = CMPA and counter = CMPB events.