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Article

A Comprehensive Loss Model and Comparison of AC and DC Boost Converters

1
Lawrence Berkeley National Laboratory, Department of Building Technologies Urban Systems, Berkeley, CA 94720, USA
2
Department of Electrical Engineering and Computer Science, Washington State University, Vancouver, WA 99163, USA
3
National Renewable Energy Laboratory, Building Energy Science Group, Golden, CO 80401, USA
*
Author to whom correspondence should be addressed.
Energies 2021, 14(11), 3131; https://doi.org/10.3390/en14113131
Received: 19 April 2021 / Revised: 22 May 2021 / Accepted: 24 May 2021 / Published: 27 May 2021
(This article belongs to the Special Issue Direct Current (DC) Distribution Grids and Microgrids)

Abstract

:
DC microgrids have become a prevalent topic in research in part due to the expected superior efficiency of DC/DC converters compared to their AC/DC counterparts. Although numerous side-by-side analyses have quantified the efficiency benefits of DC power distribution, these studies all modeled converter loss based on product data that varied in component quality and operating voltage. To establish a fair efficiency comparison, this work derives a formulaic loss model of a DC/DC and an AC/DC PFC boost converter. These converters are modeled with identical components and an equivalent input and output voltage. Simulated designs with real components show AC/DC boost converters between 100 W to 500 W having up to 2.5 times more loss than DC/DC boost converters. Although boost converters represent a fraction of electronics in buildings, these loss models can eventually work toward establishing a comprehensive model-based full-building analysis.

1. Introduction and Motivation

1.1. AC and DC Converters

DC microgrids have become a hot topic in research with the spread of internally-DC loads, solar generation, and battery storage. The total system efficiency is expected to improve from eliminating conversions between AC and DC. Previous works have compared the losses in AC and DC microgrids [1,2,3,4,5,6,7,8]. In typical commercial buildings, the modeled savings with DC varied from 2% [1] to as much as 19% [8], depending on the modeled converter efficiency and the respective voltage levels. Gerber et al. [3] conducted a side-by-side AC and DC building simulation with a parametric sweep of solar and storage capacity. The simulation showed that AC buildings suffer the most loss from low-power AC/DC converters [3]. For example, AC/DC LED drivers can achieve up to 94% efficiency, whereas DC/DC LED drivers are typically at least 98% [4].
These previous works all had a major shortcoming: the converter loss models were limited to efficiency curves or peak efficiencies from product data sheets. Product data vary considerably with component quality and manufacturer. An accurate study would require a substantial number of efficiency curves to establish typical operating efficiencies for each class of device. DC products are far less common than AC, and reliable efficiency data are even more rare. In addition, these works compare AC and DC systems that have different network voltages (e.g., comparing 120 Vrms AC to 380 V DC). As converters are generally more efficient at higher voltage [3], it is unclear whether DC systems are inherently more efficient or are simply analyzed at a higher voltage.
This work is part of an effort to improve upon past full-building efficiency studies. It aims to replace modeled or simulated efficiency curves with a rigorous math-based converter loss model. In particular, this paper extends [9] to develop a formulaic model that can theoretically compare the efficiency and losses in equivalent AC (AC/DC PFC) and DC (DC/DC) boost converters. Such a normalized comparison can improve previous system-level studies and help to quantify the energy benefits of DC. While boost converters only account for a fraction of power converters in a building, this work presents a modeling method that can be extended to compare other types of converters, ultimately allowing a full-building loss analysis. This loss model is entirely equation-based and easy for engineers to apply in other types of academic and industrial projects.

1.2. Boost Converters

DC boost converters step-up the input DC voltage to a higher output DC voltage. AC boost converters, shown in Figure 1, step-up the input sinusoid and ensure unity power factor through a power factor correction (PFC) controller. Today’s standards mandate PFC in most loads [10], and as such, AC boost converters are now present in many loads including EV charging, HVAC, heat-pump water heating, refrigeration, and data centers. This work models losses in the following components: the input inductor (L), the switch (Q), the boost diode (D), and the output capacitor (C). The AC boost converter has an additional loss component, the diode bridge (B). The model assumes a converter with (a) continuous conduction mode operation, (b) an input current that is in-phase with the input voltage, and (c) no voltage ripple at the output. This work develops two boost converter models: the simple model, and the model with ripple. The latter accounts for ripple current at the input, making it more accurate but more complex.
Previous works derive loss models for DC [11,12,13,14] and AC PFC [15,16,17,18,19,20,21,22,23] boost converters. However, none of these models establish the necessary analytic framework for a side-by-side AC to DC comparison. Many previous works use a basic model for switching loss and neglect loss in the input diode bridge and output capacitor. This is the first work to develop a formulaic loss comparison between converters with identical components and an equivalent input and output voltage. These models calculate a complete loss analysis from the input voltage, output voltage, output power, and parasitic values easily found in component data sheets. DC converters have generally been known to be more efficient, but this work quantifies the exact difference in loss.
There are two main forms of loss in a converter: conduction loss and switching loss. Conduction loss models are derived in Section 2 and Section 3 and switching loss models are derived in Section 4 and Section 5. Core loss is not modeled; it can be significant in some types of converters, but is negligible for continuous conduction boost converters with relatively small ripple [23,24,25,26]. Finally, the authors of Section 6 describe the model validation through simulation and experiment, and the authors of Section 7 show how the model can be used to calculate the loss in AC and DC boost converters. For a quick reference to all the loss model formulae, see in Appendix A.1, Appendix A.2, Appendix A.3 and Appendix A.4.

2. Deriving Conduction Loss Models

Conduction loss occurs when the components conduct current and mostly impacts the converter efficiency at high power. When the switch turns on, the inductor is charged by a current path through the bridge, inductor, and switch, shown in Figure 1. When the switch turns off, the inductor discharges through the bridge, inductor, and boost diode. The output capacitor acts as a filter for the output power to the load.
For each component X, this work calculates the average conduction loss, P X , c o n d , by solving for the component’s RMS and average current. For the inductor ( I L , r m s ), switch ( I Q , r m s ), and capacitor ( I C , r m s ), the average resistive loss is
P X , c o n d = R X I X , r m s 2 ,
with R L as the inductor copper resistance, R Q as the switch on-state resistance, and R C as the capacitor ESR. The average diode loss of the boost diode ( I D , r m s , I D , a v g ) and bridge diodes ( I B , r m s , I B , a v g ) is modeled as a constant forward-biased diode drop V X and a linearized series resistance R X :
P X , c o n d = V X I X , a v g + R X I X , r m s 2 .
The authors of Section 2 and Section 3 derive the model for each P X , c o n d , and the resulting formulae are organized in Appendix A.2.
Each I X , r m s and I X , a v g can be calculated with an integration of the component’s current waveform. For the AC boost converter in Figure 2, these currents are functions of the low-frequency AC angle, θ , and the high-frequency switching period T. At the switching time scale, θ is approximately constant as shown in Figure 3. Thus, the model presents an independent two-stage integration: first of the instantaneous current, i ( θ , t ) , from t = 0 to T , and then of the switching-period-RMS, i r m s , t ( θ ) , from θ = 0 to π . The total RMS current through component X is
i X , r m s , t ( θ ) = 1 T 0 T i X 2 ( θ , t ) d t
I X , r m s = 1 π 0 π i X , r m s , t 2 ( θ ) d θ .
For the DC boost converter, θ = 0 is constant, thus I X , r m s = i X , r m s , t ( θ ) .
As shown in Figure 3, the component currents appear as triangles at the switching timescale, and the geometric methods shown in Figure 4 can be employed to integrate over the switching period, T. The currents for the inductor and bridge diode appear as a zero-centered bilateral triangle, Δ B , whose average and RMS are
Δ a v g , t B = 0
Δ r m s , t B ( A ) = A 2 3 ,
where the triangle’s peak-to-peak height, A, is shown in Figure 4. For the elevated right triangle, Δ R ,
Δ a v g , t R ( B , D ) = B D
Δ r m s , t R ( A , B , D ) = D 2 3 A 2 + 12 B 2 ,
where A is the triangular section’s height, B is the elevation of the triangle’s midpoint, and D is the fraction of time that the component is active. All of the component currents are derived from either Δ B or Δ R . For the simple model, inductor-current ripple is ignored, thus A = 0 .
Finally, some RMS calculations can be simplified by leveraging the orthogonality of waveforms. If i 1 ( t ) is orthogonal to i 2 ( t ) and i ( t ) = i 1 ( t ) + i 2 ( t ) , then
I r m s = I r m s , 1 2 + I r m s , 2 2 .

3. Conduction Loss Component Currents

3.1. Input and Duty Cycle

This research establishes a comparison between AC and DC boost converters subject to an equivalent power and voltage level. Both converters are modeled with an identical constant output power P o and output voltage V o . The AC and DC input voltage and current are, respectively,
v i , A C ( θ ) = V p k s i n ( θ )
i r e f , A C ( θ ) = I p k s i n ( θ ) = 2 P o V p k s i n ( θ )
v i , D C = V p k
i r e f , D C = P o V p k .
The comparison considers the peak AC input, V p k , as an appropriate equivalent DC input as most application-relevant specifications relate to V p k (e.g., switch stress, breakdown voltage, safety, and insulation). For the DC converter, v i and i r e f are constant and do not depend on θ . For the purpose of deriving component currents, the loss model assumes P i n = P o (i.e., 100% efficiency), which yields simple but accurate formulae for most boost converters [15,16].
The switching duty cycle for the switch, δ Q , and the boost diode, δ D , can be separately expressed as
δ Q ( θ ) = 1 v i ( θ ) V o
δ D ( θ ) = v i ( θ ) V o ,
and are useful in calculating (5)–(8).
The following subsections explain the calculations of the RMS and average of each component current. Final expressions for the simple model are shown in Table A1. Final expressions for the model with ripple are shown in Table A2 and Table A3.

3.2. Inductor Current

Simple Model: When ripple is ignored, i L = i r e f , and i L , r m s is calculated as the RMS of the sinusoidal i r e f .
Model with Ripple: Inductor ripple is geometrically represented as a bilateral triangle. On the switching timescale, the peak-to-peak inductor current ripple is
Δ i L , p p ( θ ) = v i ( θ ) δ Q ( θ ) f L .
The RMS of Δ i L , p p ( θ ) is solved from (4) and (6) as
Δ i L , r m s , t ( θ ) = Δ r m s B A = Δ i L , p p ( θ )
Δ I L , r m s = 1 π 0 π i L , r m s , t 2 ( θ ) d θ .
Figure 2 clearly shows the total inductor current, i L ( θ , t ) , to be the sum of i r e f ( θ ) and Δ i L ( θ , t ) . Given (14) and (16), these waveforms are orthogonal, and can be combined through (9) as
I L , r m s = I r e f , r m s 2 + Δ I L , r m s 2 .

3.3. Diode Bridge Current

Simple Model: The inductor and diode bridge are in series, thus i B ( θ , t ) = i L ( θ , t ) and I B , r m s = I L , r m s . I B , a v g is calculated as the average of the sinusoidal i r e f ( θ ) .
Model with Ripple: A bilateral triangle has an average of zero regardless of the ripple. Thus, I B , a v g is the average of i r e f ( θ ) .

3.4. Switch Current

Simple Model: During δ Q ( θ ) , the inductor current flows through the switch. Both the simple and ripple models integrate Δ r m s , t R . For the simple model,
I Q , r m s , t ( θ ) = Δ r m s , t R ( A = 0 , B = i r e f ( θ ) , D = δ Q ( θ ) ) .
Model with Ripple: Evaluating (20) with A = Δ i L , p p ( θ ) accounts for inductor current ripple.

3.5. Boost Diode Current

Both boost diode models can leverage the analysis in Section 3.4 with D = δ D ( θ ) to solve the RMS current. The average current is indifferent to inductor current ripple, and is calculated from Δ a v g , t R .

3.6. Capacitor Current

The boost diode current is split between the capacitor and load, i.e., i D ( θ , t ) = i C ( θ , t ) + P o V o . In both models, these orthogonal currents combine via (9) as
I C , r m s = I D , r m s 2 P o V o 2 .

4. Switching Loss in the Switch (Q)

Switching loss most impacts a converter’s low-load efficiency and occurs when the switch and diode toggle state between conducting and blocking. Instantaneous switching loss is determined on the switching time scale, and expressed as a function P X , s w , y y ( θ ) . For average switching loss:
P X , s w , y y = 1 π 0 π P X , s w , y y ( θ ) d θ .
This section derives the switching loss models for hard switching, P Q , s w , h s , and switch output capacitance, P Q , s w , c . The resulting formulae are organized in Appendix A.3. Although past works have rigorously characterized switching loss [27,28], their models rely on complex nonlinear equations and self-measured parasitics. This section presents a simple but accurate model based on parasitics easily found in data sheets.

4.1. Hard-Switching Loss

The switch has two states: blocking or conducting, with zero current or zero voltage, respectively. However, during a transition, the switch briefly experiences a simultaneous non-zero current, i D S , and voltage drop, v D S , across its drain-source terminals. The overlap of this non-zero voltage and current causes switching loss.
Figure 5 and Figure 6 show the voltage and current waveforms for the boost converter, which is characterized by inductive switching as described in [29,30]. When the switch turns on, the i D S must rise to its final value, I D S , m a x , before v D S can fall to zero. When it turns off, v D S must rise to V D S , m a x before i D S can fall. The overlap between i D S and v D S is the energy lost per cycle, which can be geometrically calculated. Although the overlap can be reduced by snubbing, this work models the worst-case hard-switched boost converter.
The loss calculation requires knowledge of the rise and fall times of the voltage and current: T V R , T V F , T I R , and T I F . These durations are heavily influenced by the gate drive, gate resistance R G , and gate input capacitance C I S S . The gate drive is modeled as a step function with amplitude V G S , m a x . R G includes both the internal device resistance and external drive resistance. C I S S is defined by the gate-source ( C G S ) and the gate-drain ( C G D ) capacitances as
C I S S = C G S + C G D = C G S + C R S S .
Calculation of the rise and fall times begins with an understanding of how the gate driver charges the input capacitances in Figure 7 through the various stages of switching. When the switch turns on:
  • The gate driver charges C G S . The gate voltage, v G S , increases to the gate-threshold voltage, V T H .
  • The gate driver continues to charge C G S . v G S continues to increase as i D S rises to I D S , m a x .
  • The gate driver now discharges C G D . v G S remains constant at the gate-plateau voltage, V G P , as v D S falls to near-zero.
When the switch turns off:
4.
The gate driver discharges C G S . v G S decreases to V G P .
5.
The gate driver charges C D S . v G S remains constant at V G P as v D S rises to V D S , m a x .
6.
The gate driver discharges C G S . v G S decreases to V T H and i D S falls to near-zero.
The durations of these six phases can each be solved as a simple R-C circuit, following the appropriate charging paths in Figure 7. During T 1 and T 2 , the gate current charges C G S , and v G S follows the typical negative-exponential curve of an R-C circuit. During T 3 , v G S is constant, thus injecting a constant current into C G D and causing V D S to fall linearly. The turn-on phase timings are
T 1 = R G C I S S ln V G S , m a x V G S , m a x V T H
T 2 = R G C I S S ln V G S , m a x V G S , m a x V G P T 3 = T V F = R G C G D V D S , m a x V G S , m a x V G P
R G Q G D , 0 V D S , 0 V D S , m a x V G S , m a x V G P .
Similarly, the gate current discharges C G S during T 4 and T 6 , and charges C G D during T 5 . The turn-off phase timings are
T 4 = R G C I S S ln V G S , m a x V G P
T 5 = T V R = R G C G D V D S , m a x V G P R G Q G D , 0 V D S , 0 V D S , m a x V G P
T 6 = T I F = R G C I S S ln V G P V T H .
Although Figure 7 suggests calculating T 3 and T 5 from C G D , in practice C G D actually varies considerably with v D S [29,31,32]. As such, it is recommended instead to express T 3 and T 5 as a function of the gate charge, Q G D , that is drained from C G D during T 3 and added during T 5 . The datasheet often lists Q G D at a specific test point with gate-charge Q G D , 0 corresponding to drain-source voltage V D S , 0 .
As shown in Figure 5 and Figure 6, T I R = T 2 T 1 , T V F = T 3 , T V R = T 5 , and T I R = T 6 . In addition, T 1 is turn-on delay and T 4 is the turn-off delay. Expressions for the the rise and fall timings are summarized in Table A5 (Appendix A.3).
The energy lost over the turn-on and turn-off region of overlap is generally calculated as
E Q , s w , h s = 1 2 V D S , m a x I D S , m a x T
where T is either the turn-on time T O N = T I R + T V F or the turn-off time T O F F = T V R + T I F . V D S , m a x and I D S , m a x depend on the circuit and model. For the simple boost converter model,
P Q , s w , h s ( θ ) = V O I r e f ( θ ) f 2 ( T O N + T O F F ) ,
and for the boost converter model with ripple,
P Q , s w , h s ( θ ) = V o f 2 ( I r e f ( θ ) Δ i L , p p ( θ ) 2 T O N + I r e f ( θ ) + Δ i L , p p ( θ ) 2 T O F F ) .
The average hard-switching loss can be derived from Table A5 and (22), (31) and (32). Formulae for the hard-switching loss models are shown in Table A6 (Appendix A.3).

4.2. Output-Capacitance Loss

Every switching cycle, the switch’s parasitic equivalent output capacitance, C o s s , stores charge and discharges through the on-resistance. This loss is derived from the energy stored on the capacitor every cycle [24]:
P Q , s w , c = 1 2 C o s s V o 2 f .

5. Switching Loss in the Diode (D)

This section derives the switching loss models for diode reverse recovery, P D , s w , r r , and junction capacitance, P D , s w , c . The resulting formulae are organized in Appendix A.4.

5.1. Reverse Recovery Loss

The boost diode’s reverse recovery occurs when the diode switches from conducting to blocking. As the diode becomes reverse biased, the depletion-layer’s charge is injected into the system as the reverse-recovery current, and causes loss in both the diode and switch. The reverse-recovery current, shown in Figure 8, is approximated as a triangular function characterized by the peak reverse-recovery current, I r r , and the reverse-recovery time segments, T a and T b , which sum to the total reverse-recovery time T r r [33,34,35]. The diode’s reverse-recovery transient is also determined by its forward current, I F , prior to switching, and the slope of its switching current, d I D d t , where
d I D d t = I r r T a .
In addition, the reverse-recovery charge, Q r r , is the area of the triangle and can be approximated as
Q r r = T r r I r r 2 .
Tables and charts in data sheets will often provide some combination of I r r , I F , T r r , d I D d t , and Q r r , but these data are usually constrained to a specific operating point. In order to derive a reverse-recovery model that holds over a wide operating range, the diode’s intrinsic characteristics must be quantified. These include the diode’s softness or snappiness factor, S, where
S = T b T a .
In addition, the forward-biased charge coefficient, K Q , can be approximated as
Q F = K Q I F Q r r ,
as the junction’s stored forward-biased charge, Q F , is approximately equal to reverse-recovery charge, Q r r , that is ejected upon switching [33]. As such, S and K Q can be calculated from a datasheet using these formulae:
S = T r r , 0 d I D , 0 d t I r r , 0 1
K Q = I r r , 0 T r r , 0 2 I F , 0 ,
where the “0” indicates that each value is pulled from the datasheet and has only been measured at a specific operating point.
The diode model uses S and K Q to estimate the reverse-recovery characteristics I r r , T a , and T b at any arbitrary operating point:
I r r = 2 d I D d t K Q I F 1 + S
T a = I r r d I D d t
T b = S T a .
These formulae require knowledge of I F and d I D d t for the given power converter. For the simple boost converter model, I F = i L ( θ , t ) = I r e f ( θ ) . For the boost converter model with ripple, I F = I r e f ( θ ) Δ i L , p p 2 , which must be greater than zero in continuous conduction mode. In either case, d I D d t = I F T I R , where T I R is the switch’s current rise time previously defined in Table A5.
The energy lost per switching cycle is geometrically calculated from Figure 9 as
E Q = V D S I r r 2 T a + I r r 4 T b
E D = V R I r r 4 T b
P D , r r ( θ ) = ( E Q + E D ) f ,
where V D S = V R = V O for a boost converter [36]. As it happens, S falls out of the equation, and only K Q need be solved.
The average reverse-recovery loss power can be derived from (22) and (45). Equation (22) yields a simple result for the DC boost converter, shown in Table A7. However, the AC boost converter’s expressions simplify to a non-integrable form, which can be closely approximated by a second-order Taylor series:
A s i n ( θ ) + B s i n 2 ( θ ) A + B ( θ π 2 ) 2 ( A + 2 B ) 4 A + B .
The AC converter’s reverse-recovery loss model uses (46) to derive the results shown in Table A7 (Appendix A.4).

5.2. Junction-Capacitance Loss

The diode’s parasitic junction capacitance, C j , discharges when the diode switches from blocking to conducting. This capacitance results from the parallel-plate characteristics of the insulating depletion layer and the conducting P and N regions. Similar to (33), the capacitive loss is carried by the switch and is modeled as [24]
P D , s w , c = 1 2 C j V o 2 f .

6. Model Validation

This work uses both simulation and experiment to validate the boost converter loss models.

6.1. Simulation Validation

Conduction loss is validated via a PSIM 11.1.5 transient simulation over a single AC cycle. The modeled ideal boost converter either has an AC PFC or a DC controller, and operates at V p k = 170 V, V o = 350 V, and P o = 250 W. The simulated component currents are all within 0.5% of the simple model and 0.1% of the model with ripple.
This work uses LTSpice to validate the switching loss in the MOSFET as the PSIM level 2 simulation models do not account for the change in C D S with V D S . The STP8NM60 MOSFET is simulated in LTSpice with and without a 10 Ω gate-driver resistance. The simulation is run with V I N = 170 V, V O = 335 V, and P o = 775 W. Measurements of the rise and fall times are taken from the 10% to 90% levels. The simulated switching loss is within 9% of the simple model and 15% of the model with ripple. The discrepancy is mostly from the way in which LTSpice models the hard-switching overlap.
This work attempted to use the PSIM level 2 diode model to validate the diode reverse-recovery loss because LTSpice does not properly model T b [37]. Simulations were performed in a standard inductively-switched 400 V reverse recovery test rig, with d I D d t parametrically swept from 200 A/µs to 1000 A/µs and I F swept from 2 A to 10 A. This work compares the both the model and simulation to the highly-detailed datasheet curves for a LQA08TC600 and RFNL5TJ6S diode. As it happens, the model’s estimate of I r r and T r r was actually better than that of the simulation. The modeled diode calculated I r r with 9–13% error, and T r r with 10–14% error. The simulation calculated I r r with 22–71% error, and T r r with 11–22% error.

6.2. Experimental Validation

This work uses the DC boost converter prototype in Figure 10 as an experimental validation. The converter’s components and lab equipment are listed in Table 1. This work focuses on validating the full end-to-end efficiency, which extends the previous component current validation [9]. The converter is operated in DC/DC mode with duty cycle of 50%; input of 24 V, 48 V, and 96 V; and output current swept from 0–2 A. The results in Figure 11 show a decent consistency between the experiment and model, with an efficiency difference of at most 3.4%. The model slightly under-estimates the loss at high current, indicating possible unaccounted resistive parasitics in the PCB and measurement equipment.

7. Efficiency Comparison of AC vs. DC

This work compares AC and DC boost converters through a parametric analysis that applies parasitics from the components in Table 1 to the modeling formulae in Appendix A.1, Appendix A.2, Appendix A.3 and Appendix A.4, and sweeps the output power from 50 W to 500 W and the output voltage from 200 V to 400 V. The resulting modeled efficiency curves in Figure 12 illustrate how these models allow for a direct converter loss comparison. The AC boost converter may have up to 2.5 times the loss of its DC equivalent over the given output power and voltage range. Figure 13 presents a loss analysis that reveals the switch as the primary source of loss for this particular set of components.

8. Conclusions and Future Work

Past research compares the full-building efficiency between AC and DC systems, but these modeled systems rarely have equivalent voltage levels and power electronics. This work focuses specifically on comparing an AC/DC PFC and DC/DC boost converter. It develops a rigorous formulaic loss model, and validates this model via simulation and experiment. The loss model and simulation were compared over a range of values, and matched within 0.5% for conduction loss and 15% for switching loss. The loss model and experiment were compared for a DC/DC boost converter and found to match within 3.4%. A parametric loss analysis of modeled converters in the range of 200 to 400 V and 50 to 500 W shows AC/DC PFC boost converters to have up to 2.5 times the loss of DC/DC boost converters.
This study is part of a larger research effort to rigorously compare AC and DC buildings. While this study validates the efficiency benefits of DC/DC boost converters, there are many other types of power converters that can be developed in future work. A full-building efficiency study should at least develop two more converter loss models: (a) a flyback converter that represents small loads such as electronics and lighting, and (b) a half-bridge inverter that represents microgrid equipment such as solar and battery inverters. Future work would also study the variance in component parasitics to determine the most representative efficiency curve for each class of converter. An analysis of other methods of operation such as soft switching and discontinuous conduction mode may also prove valuable. These improvements can all work toward creating an accurate full-building energy model.

Author Contributions

Conceptualization, D.L.G. and F.M.; methodology, D.L.G.; software, D.L.G.; validation, D.L.G., O.A.G. and J.P.; formal analysis, D.L.G.; investigation, D.L.G. and F.M.; resources, R.E.B., W.F. and S.M.F.; data curation, D.L.G.; writing—original draft preparation, D.L.G.; writing—review and editing, O.A.G., S.M.F. and J.P.; visualization, D.L.G.; supervision, F.M., R.E.B., W.F. and S.M.F.; project administration, R.E.B., W.F. and S.M.F.; funding acquisition, R.E.B., W.F. and S.M.F. All authors have read and agreed to the published version of the manuscript.

Funding

This research and the APC was funded by U.S. Department of Energy (DOE) grant number DE-AC02-05CH11231 and DE-AC36-08GO28308.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

This work was authored in part by Lawrence Berkeley National Laboratory, operated for the U.S. Department of Energy (DOE) under Contract No. DE-AC02-05CH11231, and in part by the National Renewable Energy Laboratory, operated by Alliance for Sustainable Energy, LLC, for the DOE under Contract No. DE-AC36-08GO28308. Funding was provided by the DOE Assistant Secretary for Energy Efficiency and Renewable Energy Building Technologies Office Emerging Technologies Program. The views expressed in the article do not necessarily represent the views of the DOE or the U.S. Government. This work is supported through the U.S. China Clean Energy Research Center, Building Energy Efficiency (CERC-BEE) program and the Energy Design and Scoping Tool for DC Distribution Systems. The authors would like to thank their other team members and collaborators who have participated in related DC research and work to further the industry.

Conflicts of Interest

The authors declare no conflict of interest.

Appendix A

Appendix A.1. Model Equations

This work models conduction (cond) and switching (sw) losses in the following components: the input inductor (L), the output capacitor (C), the switch (Q), and the boost diode (D). The AC boost converter also has a diode bridge (B). The total converter loss is
P l o s s = P L , c o n d + P B , c o n d + P C , c o n d + P Q , c o n d + P Q , s w , h s + P Q , s w , c + P D , c o n d + P D , s w , r r + P D , s w , c

Appendix A.2. PX,cond: Conduction Loss

The component current formulas are shown in Table A1, Table A2 and Table A3 for the simple model and model with ripple, respectively. These component currents are used to determine the conduction loss power, P X , c o n d , as shown in Table A4.
Table A1. Component currents in the simple model.
Table A1. Component currents in the simple model.
ParameterAC PFC Model FormulaDC Model Formula
I L , r m s
I B , r m s
2 P o V p k P o V p k
I B , a v g 4 π P o V p k
I Q , r m s P o V o V p k 2 V o 16 3 π V p k P o V o V p k V o V p k
I D , r m s 4 3 π P o V o V p k P o V o V p k
I D , a v g P o V o P o V o
I C , r m s P o V o V p k 16 3 π V o V p k P o V o V p k V o V p k
Table A2. AC PFC component currents model with ripple.
Table A2. AC PFC component currents model with ripple.
ParameterModel Formula
I L , r m s
I B , r m s
576 π L 2 P o 2 V o 2 f 2 + 12 π V o 2 V p k 4 64 V o V p k 5 + 9 π V p k 6 12 2 π L V o V p k f
I B , a v g
I Q , r m s 2880 π L 2 P o 2 V o 3 f 2 7680 L 2 P o 2 V o 2 V p k f 2 + 60 π V o 3 V p k 4 480 V o 2 V p k 5 + 135 π V o V p k 6 128 V p k 7 12 10 π L V o 3 2 V p k f
I D , r m s 3840 L 2 P o 2 V o 2 f 2 + 80 V o 2 V p k 4 45 π V o V p k 5 + 64 V p k 6 12 5 π L V o 3 2 V p k f
I D , a v g P o V o
I C , r m s 3840 L 2 P o 2 V o 2 f 2 720 π L 2 P o 2 V o V p k f 2 + 80 V o 2 V p k 4 45 π V o V p k 5 + 64 V p k 6 12 5 π L V o 3 2 V p k f
Table A3. DC component currents model with ripple.
Table A3. DC component currents model with ripple.
ParameterModel Formula
I L , r m s
I B , r m s
12 L 2 P o 2 V o 2 + T 2 V o 2 V p k 4 2 T 2 V o V p k 5 + T 2 V p k 6 2 L V o V p k 3
I B , a v g
I Q , r m s V o V p k 12 L 2 P o 2 V o 2 + T 2 V o 2 V p k 4 2 T 2 V o V p k 5 + T 2 V p k 6 2 L V p k 3 V o 3
I D , r m s 12 L 2 P o 2 V o 2 + T 2 V o 2 V p k 4 2 T 2 V o V p k 5 + T 2 V p k 6 2 L 3 V o 3 V p k
I D , a v g P o V o
I C , r m s V o V p k 12 L 2 P o 2 V o + T 2 V o V p k 4 T 2 V p k 5 2 L 3 V o 3 V p k
Table A4. Conduction loss, P X , c o n d .
Table A4. Conduction loss, P X , c o n d .
ParameterModel Formula
P L , c o n d I L , r m s 2 R L
P B , c o n d I B , a v g V B + I B , r m s 2 R B
P Q , c o n d I Q , r m s 2 R Q
P D , c o n d I D , a v g V D + I D , r m s 2 R D
P C , c o n d I C , r m s 2 R C

Appendix A.3. PQ,sw,hs and PQ,sw,c: Hard Switching and Output Capacitance Loss

Switch timings are organized in Table A5. Final formulae for the hard switching loss, P Q , s w , h s , are given in Table A6, noting that T O N = T I R + T V F and T O F F = T V R + T I F . A negative-value result may imply the converter is not in continuous conduction mode. The switch output capacitance loss, P Q , s w , c , is
P Q , s w , c = 1 2 C o s s V o 2 f .
Table A5. Switch rise and fall timings.
Table A5. Switch rise and fall timings.
TimingFormula
T I R R G C I S S ln V G S , m a x V T H V G S , m a x V G P
T V F R G Q G D , 0 V D S , 0 V D S , m a x V G S , m a x V G P
T V R R G Q G D , 0 V D S , 0 V D S , m a x V G P
T I F R G C I S S ln V G P V T H
Table A6. Hard-switching loss, P Q , s w , h s .
Table A6. Hard-switching loss, P Q , s w , h s .
ModelAverage Loss Power
AC PFC (simple) 2 P o V o f T o f f + T o n π V p k
DC (simple) P o V o f T o f f + T o n 2 V p k
AC PFC (ripple) 16 L P o T o f f V o f + 16 L P o T o n V o f + 4 T o f f V o V p k 2 π T o f f V p k 3 4 T o n V o V p k 2 + π T o n V p k 3 8 π L V p k
DC (ripple) 2 L P o T o f f V o f + 2 L P o T o n V o f + T o f f V o V p k 2 T o f f V p k 3 T o n V o V p k 2 + T o n V p k 3 4 L V p k

Appendix A.4. PD,sw,hs and PD,sw,c: Diode Reverse Recovery and Junction Capacitance Loss

Formulae for the boost diode reverse recovery loss, P D , s w , r r , are given in Table A7, given that
K Q = I r r , 0 T r r , 0 2 I F , 0 .
A complex-value result may imply the converter is not in continuous conduction mode. The diode junction capacitance loss, P D , s w , c , is
P D , s w , c = 1 2 C j V o 2 f .
Table A7. Diode reverse recovery loss, P D , s w , r r .
Table A7. Diode reverse recovery loss, P D , s w , r r .
ModelAverage Loss Power
AC PFC (simple) K Q P o V o f 48 π 2 24 2 V p k
DC (simple) K Q P o V o f V p k
AC PFC (ripple) K Q V o f 4 π 2 L P o V o f + 192 L P o V o f 48 V o V p k 2 + π 2 V o V p k 2 2 π 2 V p k 3 + 48 V p k 3 48 2 L V p k 4 L P o V o f V o V p k 2 + V p k 3
DC (ripple) K Q V o f 2 L P o V o f V o V p k 2 + V p k 3 2 L V p k

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Figure 1. The modeled AC boost converter. The DC boost converter does not have a diode bridge (B).
Figure 1. The modeled AC boost converter. The DC boost converter does not have a diode bridge (B).
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Figure 2. The inductor current i L ( θ , t ) tracks a reference input current I r e f ( θ ) = I p k s i n ( θ ) .
Figure 2. The inductor current i L ( θ , t ) tracks a reference input current I r e f ( θ ) = I p k s i n ( θ ) .
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Figure 3. On the switching timescale, θ is approximately constant. The inductor current, i L ( θ , t ) , passes through the switch (green) during δ Q ( θ ) , and the boost diode (orange) during δ D ( θ ) .
Figure 3. On the switching timescale, θ is approximately constant. The inductor current, i L ( θ , t ) , passes through the switch (green) during δ Q ( θ ) , and the boost diode (orange) during δ D ( θ ) .
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Figure 4. On the switching timescale, a bilateral triangle, Δ B , (left) can model the current through the inductor and bridge diode. This triangle is not necessarily isosceles. An elevated right triangle, Δ R , (right) can model the current through the switch and boost diode.
Figure 4. On the switching timescale, a bilateral triangle, Δ B , (left) can model the current through the inductor and bridge diode. This triangle is not necessarily isosceles. An elevated right triangle, Δ R , (right) can model the current through the switch and boost diode.
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Figure 5. Switch turn-on transient.
Figure 5. Switch turn-on transient.
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Figure 6. Switch turn-off transient.
Figure 6. Switch turn-off transient.
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Figure 7. Parasitics circuit describing the switch switching-loss mechanism.
Figure 7. Parasitics circuit describing the switch switching-loss mechanism.
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Figure 8. Diode reverse-recovery loss waveforms.
Figure 8. Diode reverse-recovery loss waveforms.
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Figure 9. Diode and switch current and voltage waveforms for the boost converter. Note that for the boost converter, V R = V D S = V O and I F = I D S = i r e f Δ i L , p p at the time of transition.
Figure 9. Diode and switch current and voltage waveforms for the boost converter. Note that for the boost converter, V R = V D S = V O and I F = I D S = i r e f Δ i L , p p at the time of transition.
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Figure 10. DC boost converter experimental validation prototype.
Figure 10. DC boost converter experimental validation prototype.
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Figure 11. Comparison between experiment and model. Duty cycle is 50%.
Figure 11. Comparison between experiment and model. Duty cycle is 50%.
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Figure 12. These efficiency curves are the result of a parametric analysis of AC and DC boost converters. The AC converters have slightly higher switching loss and much higher conduction loss than their DC counterparts.
Figure 12. These efficiency curves are the result of a parametric analysis of AC and DC boost converters. The AC converters have slightly higher switching loss and much higher conduction loss than their DC counterparts.
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Figure 13. A loss analysis and itemized loss breakdown. The bar segments represent the percent loss (loss power divided by input power) that occurs in each component. Each pair of bars compares the loss in the AC (left) and DC (right) boost converters. The converters were modeled with an input voltage V p k = 170 V and an output voltage V o = 250 V.
Figure 13. A loss analysis and itemized loss breakdown. The bar segments represent the percent loss (loss power divided by input power) that occurs in each component. Each pair of bars compares the loss in the AC (left) and DC (right) boost converters. The converters were modeled with an input voltage V p k = 170 V and an output voltage V o = 250 V.
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Table 1. Components in DC Boost Prototype.
Table 1. Components in DC Boost Prototype.
ComponentIdentification Number
InductorPremo PFCA500-8H
Diode BridgeDiodes Inc. GBU804
SwitchSTMicroelectronics STP9NK60Z
Boost DiodePower Integrations LQA08TC600
Capacitor (2×)TDK Electronics B43544A6477M000
DC Power SupplyChroma 62024P-600-8
Electronic LoadChroma 63802
Revenue-Grade DC MeterAccuEnergy AcuDC 243-600V-A1-P2-C-D
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Gerber, D.L.; Musavi, F.; Ghatpande, O.A.; Frank, S.M.; Poon, J.; Brown, R.E.; Feng, W. A Comprehensive Loss Model and Comparison of AC and DC Boost Converters. Energies 2021, 14, 3131. https://doi.org/10.3390/en14113131

AMA Style

Gerber DL, Musavi F, Ghatpande OA, Frank SM, Poon J, Brown RE, Feng W. A Comprehensive Loss Model and Comparison of AC and DC Boost Converters. Energies. 2021; 14(11):3131. https://doi.org/10.3390/en14113131

Chicago/Turabian Style

Gerber, Daniel L., Fariborz Musavi, Omkar A. Ghatpande, Stephen M. Frank, Jason Poon, Richard E. Brown, and Wei Feng. 2021. "A Comprehensive Loss Model and Comparison of AC and DC Boost Converters" Energies 14, no. 11: 3131. https://doi.org/10.3390/en14113131

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