Stacked Buck Converter: Current Ripple Elimination Effect and Transient Response

Abstract

To balance the cost and volume when applying a low output current ripple, the power supply design should be able to eliminate the current ripple under any duty cycle in medium and high switching frequencies, and considerably reduce filter volume to improve power density. A stacked buck converter was eventually selected after reviewing the existing solutions and discussing their advantages and disadvantages. A stacked buck converter is used as a basis to propose the transient response and output current ripple elimination effect, boundary limit control method, and low output ripple dead time modulation method to make individual improvements. The principle, mathematical derivation, small-signal model, and compensator design method of the improvement method are presented in detail. Moreover, simulation results are used to mutually verify the correctness and effectiveness of the improvement method. A stacked buck converter with 330-V input, 50-V output, and 1-kW output power was implemented to verify the effect of the low output current ripple dead time modulation. Experimental results showed that the peak-to-peak value of the output current ripple was reduced from 2.09 A to 559 mA, and the RMS value was reduced from 551 mA to 91 mA, thereby effectively improving the output current ripple.

1. Introduction

With the development of technology, batteries have been extensively used in daily life. Batteries are used in electric vehicles [1,2,3], wearable devices, and large energy storage systems [4,5,6]. Therefore, the efficiency, life, and reliability of batteries are becoming increasingly critical. A battery management system (BMS) [7,8,9] is widely used to improve the utilization of batteries. Apart from preventing overcharge and over-discharge of batteries, BMS diagnoses and analyzes battery life and health status by recording battery-related data and residual capacity to optimize their overall performance.

One of the standard test methods for batteries’ usable capacity is the coulomb measurement method [10,11]. This method is used to calculate the current value flowing into or out of batteries and integrates the current value over time to determine the number of coulombs flowing through. This method can accurately estimate the available battery capacity. In battery capacity measurement, the accuracy of voltage and current measurements is related to the final calculation error. To achieve an accurate battery capacity calculation, the battery charging current must be accurately measured. The current ripple elimination mechanism is particularly important to prevent the output current ripple from causing measurement errors and reduce the volume of the output capacitor to increase power density.

Standard current ripple elimination techniques are mainly divided into three categories. The first category uses multi-phase buck converters in parallel and alternately switched with one another [12,13]. Through the sum of the current ripples of different phases, the final synthesized overall output current can reduce the total ripple amount and period, thereby increasing the equivalent current ripple frequency to reduce the capacitance of the output capacitor. However, the combined current ripples with this approach can only cancel each other under a specific duty cycle and number of parallel connections, thereby achieving an ideal current ripple elimination effect. Moreover, the use of multiple units in parallel increases the circuit cost and layout area, and the current sharing between multiple converters also requires additional control [14,15], thereby increasing the overall complexity. The second category uses coupled inductors to generate reverse ripple current [16,17]. The coupled inductor automatically generates the reverse ripple current, and the current ripple cancellation function can be achieved under any duty cycle. However, this cancellation function is fundamentally a fourth-order LC filter [18], which is based on filtering to obtain the characteristics of low output current ripple. A converter’s output current filtering capability and transient response often have opposite design indicators when designing a fourth-order LC filter. To achieve a superior filtering effect, the inductance value of the filter should be increased, which directly reduces the transient response speed of the converter. Therefore, the converter’s transient response will be fundamentally limited in the application of low current ripple output. The third category uses a stacked architecture [19,20], which utilizes the complementary operation of the upper and lower switches of the two bridge arms to superimpose the two arms’ inductor currents. In this way, the output inductor current ripple can be canceled under any switching duty cycle. This architecture can accelerate the rising or falling slope of the overall output current when both arms are turned on simultaneously on the upper or lower bridge switch, thereby improving the transient response. However, the literature [19,20] has only extensively discussed complementary switching signals. Moreover, these studies have not focused on the dead time of the upper and lower bridge switching signals in practical applications and the parasitic capacitance of switching elements. Consequently, the current ripple elimination effect is affected. The RC delay control method proposed in the pattern [21] improves the transient response by increasing a converter’s transient response. However, this method has flaws. After the feedback compensator is saturated, the area where the switching signals of the two arms overlap simultaneously cannot be generated, and the ability to increase the transient response is lost. On the basis of the preceding literature discussion, this study proposes a low output ripple dead time modulation and boundary limit control methods to improve the stacked buck converter’s output current ripple elimination effect and increase the transient response.

The remainder of this paper is structured as follows. Section 1 presents the research background and introduction. Section 2 reviews the two architectures proposed in the literature [16,17] and briefly describes their operating principles. Thereafter, the coupling mutual inductance form is converted into a fourth-order LC filter form [18]. The fourth-order filter is used to illustrate why the output current ripple filtering ability and transient response cannot be considered. Section 3 reviews the stacked buck converter [19] and explains its operation and current ripple elimination principle. Moreover, this section uses the perspective of large signals to describe the fastest response speed that the converter can provide when the signals overlap simultaneously. Section 4 reviews the RC delay control method [21] and explains its limitations. Thereafter, this restriction is used as a basis to propose a new type of control method called the boundary limit control method. Section 4 also explains its principle and uses simulation to verify the effect of the boundary limit control method. Section 5 presents the influence of the switching dead time and switching parasitic capacitance of the stacked buck converter on the current ripple elimination effect and proposes a mathematical analysis of the principle. The dead time modulation method and formulation of the modulation variables are verified using mathematical derivation and simulation to confirm the feasibility and effectiveness of this modulation method. Section 6 organizes the small-signal model of the coupled-inductor stacked buck converter. The small-signal model contains the small-signal model under the general two-arm switch complementary operation and boundary limit control method to design closed-loop compensation. Lastly, simulations are used to show the transient response of the system under different compensators. Section 7 implements a sample circuit. This section likewise measures the effect of the switching dead time modulation method on the current ripple elimination ability. Lastly, Section 8 summarizes this research.

2. Review of the Two Architectures and the Process of Converting Them to a Fourth-Order LC Filter

Figure 1 shows the circuit architecture and operation sequence diagram of the Ripple Current Cancellation Circuit (RCCC) [16]. The entire architecture includes a blocking capacitor C_b, coupled inductor, primary side magnetizing inductance L₁, secondary side equivalent leakage inductance L₂, and the primary and secondary turns ratio of 1:N.

From the steady-state volt-second balance of the equivalent leakage inductance L₂, the voltage on C_b can be deduced to equal the output voltage V_out. If C_b and C_out are assumed to be sufficiently large to disregard the voltage ripple on the capacitor, then the equations for i_L1, i_L2, and i₃ can be derived as follows:

$$\frac{d{i}_{L1}}{dt}=\frac{v_{SW}-V_{out}}{L_1},$$

(1)

$$\frac{d{i}_{L2}}{dt}=-N\frac{L_1}{L_2}\frac{d{i}_{L1}}{dt},$$

(2)

$$\frac{d{i}_3}{dt}=-N\frac{d{i}_{L2}}{dt}.$$

(3)

To satisfy the ripple of the output current to zero amperes, the equation should be as follows:

$$\frac{d{i}_{L1}}{dt}+\frac{d{i}_{L2}}{dt}+\frac{d{i}_3}{dt}=0.$$

(4)

By substituting Equations (1)–(3) into Equation (4), the relational equation can be derived as follows:

$$N^2-N+\frac{L_2}{L_1}=0.$$

(5)

From Equation (5), N can be obtained as follows:

$$N=\frac{1}{2}\pm \sqrt{\frac{1}{4}-\frac{L_2}{L_1}}.$$

(6)

When N satisfies Equation (6) in the RCC architecture, the output current can obtain the best elimination effect.

Figure 2 shows the circuit architecture diagram and operation sequence diagram of the three-terminal LL-LC network for current ripple cancellation (LL-LC) [17]. The entire LL-LC architecture includes a blocking capacitor C_b, coupled inductor, primary self-inductance L₁, secondary side self-inductance L₂, and a mutual inductance M between the primary side and secondary side winding, and an external inductor L₃.

Figure 2 also shows that through the operating interval when switches Q₁ and Q₂ are turned on, Equations (7) and (8) can be respectively written as follows:

$$(L_2+M)\frac{d{i}_{L2}}{dt}+(L_1+M)\frac{d{i}_{L1}}{dt}=V_{in}-V_{out},$$

(7)

$$(L_2+M)\frac{d{i}_{L2}}{dt}+(L_1+M)\frac{d{i}_{L1}}{dt}=-V_{out}.$$

(8)

According to Kirchhoff’s Current Law (KCL) and Kirchhoff’s Voltage Law (KVL), the following two equations can be obtained:

$$i_{L2}=i_{L1}+i_{L3},$$

(9)

$$(L_1+M)\frac{d{i}_{L1}}{dt}-(L_3-M)\frac{d{i}_{L3}}{dt}=V_{Cb}-V_{out}.$$

(10)

In a steady-state operation, the average voltage across the inductor is zero. Hence, the voltage across V_Cb is equal to the output voltage V_out. Assuming that the C₃ capacitor is sufficiently large, its ripple can be disregarded. Equation (10) can be rewritten as follows:

$$(L_1+M)\frac{d{i}_{L1}}{dt}-(L_3-M)\frac{d{i}_{L3}}{dt}=0.$$

(11)

When the inductance designed by L₃ is equal to the mutual inductance M, the current change of i_L1 in Equation (11) must be zero to satisfy this equation. Hence, i_L1 can achieve the function of eliminating the current ripple.

RCCC and LL-LC can achieve zero current ripple output under the condition that the voltage ripple on the blocking capacitor is disregarded, and the ideal winding turns ratio and external inductance are ideally matched. However, this conclusion must be established on the fact that voltage ripple on blocking capacitor C_b is minimal, and C_b is simplified as a constant voltage source. In addition, the capacitance value is finite, given the blocking capacitor in the actual circuit. Given that the voltage ripple on the blocking capacitor must be considered, the two architectures’ actual effects on the elimination of the output current ripple should be re-discussed. A review of the circuit structure diagram of RCCC shows that the primary side inductance is equivalent to the secondary side, and the name of the capacitor and inductance is changed, as shown in Figure 3a. Furthermore, Figure 3b shows that the RCCC equivalent circuit diagram of the transformer model changed to the T equivalent model.

To make a conversion between the transformer and T-type equivalent models, the three nodes marked on the transformer in Figure 3 must be described, and the impedance of any two nodes should be observed. Hence, the following three equations can be obtained:

$$L_a+L_b=\frac{L_m}{N^2},$$

(12)

$$L_b+L_c=L_m+L_{lk},$$

(13)

$$L_a+L_c=\left(1-\frac{1}{N}\right)\left(\frac{N-1}{N}{L}_m\right)+L_{lk}.$$

(14)

Equations (12)–(14) show that L_a, L_b, and L_c can be derived as follows:

$$L_a=\frac{-L_m(N-1)}{N^2},$$

(15)

$$L_b=\frac{L_m}{N},$$

(16)

$$L_c=L_m-\frac{L_m}{N}+L_{lk}.$$

(17)

In rewriting Equation (5), set L₁ = N⁻²L_m, L₂ = L_lk, then:

$$N^2-N+\frac{N^2{L}_{lk}}{L_m}=0.$$

(18)

The following equation is obtained when Equation (18) is substituted into Equation (17):

$$\begin{array}{l}{L}_c=L_m-\frac{L_m}{N}+L_{lk}\\ =\frac{L_m}{N^2}\left(N^2-N+\frac{N^2{L}_{lk}}{L_m}\right)\\ =0.\end{array}$$

(19)

From the result of Equation (19), L_c in the T-type model will become zero. The entire RCCC circuit will be converted into an LCLC fourth-order filter architecture, as shown in Figure 4.

Using the same method, the coupled inductor in LL-LC is converted to a T-type model, as shown in Figure 5.

To make a conversion between the transformer and T-type equivalent models, the three nodes marked on the transformer in Figure 5 are described, and the impedance of any two nodes is presented. Thus, the following three equations can be obtained:

$$L_a+L_b=L_1+L_2+2M,$$

(20)

$$L_b+L_c=L_1,$$

(21)

$$L_a+L_c=L_{{}_2}.$$

(22)

Equations (20)–(22) show that L_a, L_b, and L_c can be deduced as follows:

$$L_a=L_2+M,$$

(23)

$$L_b=L_1+M,$$

(24)

$$L_c=-M.$$

(25)

Comparing the design in Equations (11) and (25), when L₃ = M, then:

$$\begin{array}{ll}{L}_3+L_c& =M-M\\ & =0.\end{array}$$

(26)

The result of Equation (26) indicates that if the design conditions of LL-LC are met, then L_c and L₃ in the T model will cancel each other out to zero. Furthermore, the entire LL-LC circuit will be converted into an LCLC fourth-order filter architecture, as shown in Figure 6.

Two things can be learned in comparing the results of the conversion of RCCC and LL-LC into an equivalent fourth-order LCLC filter in Figure 4 and Figure 6. First, if the specific design conditions are met, then RCCC and LL-LC are essential fourth-order LCLC filters. Second, the ratios of L_a and L_b in the two equivalent fourth-order LCLC filters are not the same, but both have the function of current ripple filtering.

Given a fourth-order filter structure, the final filtering result of the output current ripple is determined by two aspects: (1) amount of ripple of the L_a inductor current and (2) ripple split ratio of L_b and C_b. To achieve an excellent current ripple filtering result, the inductance value of L_a should be considerably increased to reduce the inductance and capacitance values required by the current sharing circuit composed of L_b and C_b. Therefore, to pursue an excellent current ripple filtering effect for a fourth-order filter, the component value of the filter should be increased. However, such a design inevitably reduces the transient response of the converter.

3. Review of the Stacked Buck Converter

Figure 7 shows the circuit structure and operation sequence diagram of the stacked buck converter [19]. Q₁, Q₂, and L_s, and C_S and C_P in Figure 7 constitute the first group of bucks, where Q₁ and Q₂ are collectively called P-arms. Moreover, Q₃, Q₄, L_P, and C_P form the second group of buck converters, among which Q₃ and Q₄ are collectively called the S-arms. The i_P current provides energy for the load, and the i_S current provides a reverse ripple current to cancel the ripple of the i_P current.

Compared to the two architectures reviewed in Section 2, the stacked buck converter’s main idea is not to use a fourth-order filter to suppress the output current ripple. Therefore, substantial capacitance and inductance values are not required to suppress the output current ripple well. Therefore, the stacked buck converter can use a smaller inductor and capacitance value to achieve the same current ripple suppression effect. In other words, the stacked buck converter essentially has better transient response performance.

The duty cycle of Q₃ as D_P is defined. Given that the inductance L_P satisfies the volt-second balance in the steady-state, V_out = D_PV_in can be obtained from the second group of buck converters. V_out + V_Cs = V_in(1 − D_P) can be obtained from the first group of buck converters. Moreover, we can deduce that V_Cs = V_in(1 − 2D_P).

When Q₂ and Q₃ are turned on, the current change slopes of i_P and i_S are respectively expressed as follows:

$$\begin{array}{ll}\frac{d{i}_P}{dt}& =\frac{L_P(V_P-V_{out})+M(V_S-V_{Cs}-V_{out})}{L_P{}^2-M^2}\\ & =\frac{L_P{V}_{in}(-D_P)+M{V}_{in}(D_P)}{(L_P+M)(L_P-M)},\end{array}$$

(27)

$$\begin{array}{ll}\frac{d{i}_S}{dt}& =\frac{M(V_P-V_{out})+L_S(V_S-V_{Cs}-V_{out})}{L_S{}^2-M^2}\\ & =\frac{M{V}_{in}(-D_P)+L_S{V}_{in}(D_P)}{(L_S+M)(L_S-M)}.\end{array}$$

(28)

When L_P = L_S = L, Equations (27) and (28) are added to obtain the following equation:

$$\begin{array}{ll}\frac{d{i}_P}{dt}+\frac{d{i}_S}{dt}& =\frac{V_P+V_S-2V_{out}-V_{Cs}}{L-M}\\ & =\frac{V_{in}+0-2D_{P}Vin-V_{in}(1-2D_P)}{L-M}\\ & =0.\end{array}$$

(29)

Evidently, Equation (29) is zero and does not contain the variable of the duty. The preceding derivation indicates that the cascaded buck converter can eliminate current ripples under any duty cycle. The stacked buck converter’s output current ripple elimination mechanism cancels the output current ripple by generating currents with opposite slopes from two sets of inductors. Such characteristics can ideally design the inductance value arbitrarily without affecting the output current ripple’s cancellation effect. To achieve an ideal current ripple elimination effect, the voltages of C_S and C_P should approximate the ideal voltage source. However, the transient response of the converter, in this case will have a detrimental effect.

If V_Cp is set as an ideal voltage source, then V_Cs is a variable capacitor voltage. Accordingly, V_P + V_S = V_in because the two arm switches are entirely complementary.

A review of Equation (29) indicates that if the slope of change of i_P + i_S is desired to be positive, then the voltage of V_Cs should be less than (1 − D_P)V_in, which is below the steady-state value of the steady V_Cs voltage. That iss, when the C_S capacitance is low, the voltage of V_Cs is considerably susceptible to the i_S current, and the overall transient response of the converter is improved. However, this design concept will increase the ripple of V_Cs and reduce the effect of the current ripple elimination.

Compared with the fourth-order filter architecture, the stacked buck converter can use the upper or lower switches of the P and S arms to be turned on simultaneously to increase the transient response. Moreover, there is no need to deliberately reduce the capacitance of the C_S capacitor to sacrifice the current ripple elimination effect in exchange for the transient response speed. Review Equation (29) again, and substitute the V_P and V_S of Equation (29) into the input voltage V_in, representing that the upper bridge switches of the P- and S-arms are turned on. V_Cp and V_Cs are regarded as ideal voltage sources, and the rate of change of i_P + i_S is as follows:

$$\frac{d{i}_P}{dt}+\frac{d{i}_S}{dt}=\frac{V_{in}+V_{in}-2D_{P}Vin-V_{in}(1-2D_P)}{L-M}.$$

(30)

If V_P and V_S are substituted into the ground level, then the lower bridge switches representing the P- and S-arms are turned on. Moreover, V_Cp and V_Cs are regarded as ideal voltage sources, and the rate of change of i_P + i_S is as follows:

$$\frac{d{i}_P}{dt}+\frac{d{i}_S}{dt}=\frac{0+0-2D_{P}Vin-V_{in}(1-2D_P)}{L-M}.$$

(31)

Equations (30) and (31) show that although V_Cs and V_Cp are constant voltage sources, the total inductor current change rate when the numerators of these equations are not zero can still be based on the control signal. Hence, V_P = V_S = V_in or V_P = V_S = 0 to achieve the rising or falling slope. Moreover, the design of L and M can adjust the magnitude of the change slope. By simultaneously turning on the upper or lower switches of the two arms, the stacked buck converter can retain the current ripple elimination characteristics and meet transient response needs.

4. Boundary Limit Control Method

The description in Section 3 indicates that the stacked buck converter should be synchronized with the upper or lower bridge switches of the P- and S-arms to meet the transient response requirements.

To achieve this control interval, the literature [21] has indicated that adding an RC delay circuit to the feedback compensation output V_EA of the original complementary controller can easily and simultaneously manufacture the upper and lower bridge switches of the P- and S-arms. The conduction period can improve the transient response. Figure 8a,b shows complementary and RC delay controllers, respectively. Duty_P is the driving signal of the P-arm upper bridge switch Q₃, and Duty_S is the driving signal of the S-arm upper bridge switch Q₁.

Figure 9 illustrates the operation sequence diagram of the RC delay type controller. When the output load increases, the compensator output V_EA changes from steady-state operation to positive saturation V_{EA_sat}, which is the operation sequence diagram of V_EA relative to PWM in this changing interval. Figure 9 can be divided into three regions. Region I is the steady-state operation area, region II is the transient operation area, and region III is the saturation area. In region I, V_EA and V_{EA_Delay} can be regarded as the same signal, and Duty_P and Duty_S can be regarded as ideal complementary signals because the system reaches a steady-state. The output current ripple elimination mechanism is often operational. In region II, the output loading is increasing. The V_EA voltage begins to increase owing to the feedback system. V_EA and V_{EA_Delay} can no longer be regarded as the same signal because of the RC delay circuit, and the voltage amplitude V_EA is greater than V_{EA_Delay}. Therefore, Duty_P and Duty_S in region II have a duty overlap area, and the length of this area depends on the voltage difference between V_EA and V_{EA_Delay.} Duty overlap enables the converter to increase transient response. However, given that the system output voltage cannot stabilize immediately, the V_EA and V_{EA_Delay} voltages reach positive saturation and enter region III. In this region, the overlapping area of Duty_P and Duty_S disappears, returning to the general complementary operation, which significantly reduces the rising slope of the overall output current. However, the output load should receive energy at this time. Such an operation behavior further prolongs the time required for the output voltage to stabilize, and the depth of the output voltage undershoot increases. Therefore, the RC delay type control method cannot effectively adjust the converter’s output when the compensator reaches saturation.

Given the lack of RC delay control, this study proposes a boundary limit control method suitable for stacked buck converters. Apart from accelerating the transient response, the boundary limit control method is not limited by the saturation of the compensator. Figure 10 shows a schematic of the boundary limit control method. The control principle aims to set the upper and lower limits of V_EA, and the limit value is fixed at the steady-state V_EA and take a settable boundary to generate a feedback compensation output V_{EA_Limit}.

Figure 11 shows the switch and control signal under the boundary limit control method. In region I, V_EA and V_{EA_Limit} maintain the same voltage because the system reaches a steady-state, and Duty_P and Duty_S maintain complementary operations. In region II, V_EA increases owing to an increase in load. When V_EA deviates from the steady-state V_EA value and the set limit boundary, the V_EA voltage is maintained, and V_{EA_Limit} is limited by the upper and lower limits. The result is the voltage difference between V_EA and V_{EA_Limit}, thereby making the duty of the P- and S-arm switches have an overlapping interval. In region III, although V_EA reaches positive saturation, the P- and S-arm switch signals maintain an overlapping interval because V_{EA_Limit} is limited, thereby continuously increasing the transient response of the system.

Figure 12 and Figure 13 show the simulation results of the complementary and boundary limit controllers for the transient response. The system architecture diagram, circuit parameters, and compensator parameters are shown in

Table 1. Circuit parameters.

Symbols	Parameter Names	Specifications
fsw	Switching frequency	100 kHz
Vin	Input voltage	330 V
Vout	Output voltage	48 V
L	Self-inductance	40 μH
M	Mutual inductance	30 μH
CS	Blocking capacitance	200 μF
ESRCs	Blocking capacitance series resistance	30 mΩ
CP	Output capacitance	150 μF
ESRCp	Output capacitance series resistance	10 mΩ
RL	Load Resistance	2.5 Ω
RSseq	S-arm loop series equivalent impedance	10 mΩ
RSpeq	P-arm loop series equivalent impedance	10 mΩ
Coss	Parasitic capacitance of the Q1 to Q4 switches	300 pF

, and Equation (56), respectively. The load resistance switches from R_L = 2.5 Meg Ω to R_L = 2.5 Ω at t = 70 mS, and switches from R_L = 2.5 Ω to 2.5 Meg Ω again at t = 120 mS. Figure 12 and Figure 13 show that both control methods can achieve the effect of eliminating current ripples in the steady-state. Regarding the performance of the overshoot and undershoot of the output voltage, the boundary limit control method was superior to the complementary control method. Using the boundary limit control method to replace the complementary control method, the overshoot performance of the output voltage decreased from 417 mV to 361 mV, and the undershoot performance decreased from 370 mV to 324 mV.

5. Dead Time Modulation Method for Low Output Ripple

The output current ripple cancellation effect of the stacked buck converter in the existing system is affected by the actual dead time between the lower bridge switches. Hence, a necessary step is to understand the origin of the steady-state voltage value on the C_S capacitor and the relationship between the voltage on the C_S capacitor and the cancellation effect of the output current ripple.

Figure 14 shows the equivalent circuit diagram redrawn by converting the coupled inductor in Figure 7a into a T-type model and unifying the symbols with L_S = L_P = L.

To immediately understand and analyze the impact caused by dead time, the discussion of the circuit mode is limited to the idea that the output load condition is sufficiently large to make the current of i_P constantly above zero.

To simplify the analysis, V_out and V_Cs can be regarded as fixed DC voltages by assuming that the capacitances of C_P and C_S are sufficiently large. In the dead time, the inductor L-M’s current change is small to be regarded as a constant current source. The switch’s parasitic capacitance C_oss is fixed and does not change with the voltage across it. Moreover, the turn-on voltage drop of the body diode of the switch is disregarded as 0 V.

First, the steady-state voltage value of V_Cs is derived with an ideal stacked buck converter. Given that the switching signals are entirely complementary, the node voltages V_P and V_S have only two states: State 1, V_S = V_in, V_P = 0; and State 2, V_S = 0, V_P = V_in. Solving V_Cs for these two states, the derivation process is as follows.

State 1, V_S = V_in, V_P = 0, according to KCL and KVL, the equation can be written as follows:

$$i_S(s)=\frac{s^{-1}\left(V_{in}\hspace{0.17em}-v_A-V_{Cs}-V_{out}\right)}{s\left(L-M\right)},$$

(32)

$$i_P(s)=\frac{s^{-1}\left(0\hspace{0.17em}+v_A-V_{out}\right)}{s\left(L-M\right)},$$

(33)

$$v_A(s)=\left[i_S(s)-i_P(s)\right]M.$$

(34)

Substituting Equations (32) and (33) into Equation (34) can solve for v_A, and rename v_A in state 1 to v_A1. The resulting equation is as follows:

$$v_{A1}(s)=\frac{s^{-1}\left(V_{in}-V_{{}_{Cs}}\right)}{\frac{L-M}{M}+2}.$$

(35)

State 2, V_S = 0, V_P = V_in, according to KCL and KVL, the equation can be written as follows:

$$i_S(s)=\frac{s^{-1}\left(0\hspace{0.17em}-v_A-V_{Cs}-V_{out}\right)}{s\left(L-M\right)},$$

(36)

$$i_P(s)=\frac{s^{-1}\left(V_{in}\hspace{0.17em}+v_A-V_{out}\right)}{s\left(L-M\right)},$$

(37)

$$v_A(s)=\left[i_S(s)-i_P(s)\right]M.$$

(38)

Substituting Equations (36) and (37) into Equation (38) can solve for v_A, and rename v_A in state 2 to v_A2. The resulting equation is as follows:

$$v_{A2}(s)=\frac{s^{-1}\left(-V_{in}-V_{{}_{Cs}}\right)}{\frac{L-M}{M}+2}.$$

(39)

The steady-state indicates that the inductance M must satisfy the volt-second balance to write Equation (40), where V_A1 and V_A2 are the DC voltage levels obtained by the inverse Laplace conversion of v_A1 and v_A2, respectively, as follows:

$$V_{A1}(1-D_P)+V_{A2}{D}_P=0.$$

(40)

Substituting Equations (35) and (39) into Equation (40) after the inverse Laplace transformation, we obtain the following equation:

$$\frac{1}{\frac{L-M}{M}+2}\left[\left(V_{in}-V_{Cs}\right)\left(1-D_P\right)+\left(-V_{in}-V_{Cs}\right)D_P\right]=0.$$

(41)

Thereafter, solving Equation (41) can obtain V_Cs as follows:

$$V_{A1}(1-D_P)+V_{A2}{D}_P=0.$$

(42)

A review of Equation (29) indicates that when V_P + V_S − V_Cs = 2D_PV_in must be satisfied (i.e., when V_Cs = (1 − 2D_P)V_in), the slope of i_P + i_S will be zero. In an ideal stacked buck converter, the relationship of Equation (29) is satisfied because the switching signals are completely complimentary. Hence, the output current ripple elimination behavior can be ideally achieved. However, in practical applications, the upper and lower bridge switches inevitably contain a dead time. Thus, the stacked buck converter’s current ripple elimination effect should be re-discussed.

Figure 15 shows an operation sequence diagram of a stacked buck converter with conventional dead time. Dead time is fixed, and four switches are turned off simultaneously. The operation sequence diagram in Figure 15 can be divided into three sections: switch conduction section (t₀~t₁, t₂~t₃) and two different dead times (t₁~t₂, t₃~t_0+T).

The action sequence diagram shows that the ripple slope of i_P + i_S rises in the conduction interval of the two switches. In the two switch dead time intervals, the ripple slope change phenomenon of i_P + i_S is different, but both make i_P + i_S present an equivalent falling slope. Moreover, the voltage amplitude of V_Cs is slightly lower than (1 − 2D_P)V_in.

The following discussion focuses on the three intervals to explain the behavior of the current ripple slope change of i_P + i_S. To make the waveform more convenient for discussion, the two dead time intervals of t₁~t₂ and t₃~t_0+T in Figure 15 are enlarged, leaving the V_P and V_S node voltage waveforms v_P and v_S, which are redrawn as Figure 16.

First, we discuss the dead time interval (t₁~t₂).

When t = t₁, all switches are off. Given that i_P > 0, the current will automatically flow through the body diode of Q₄ after switch Q₄ is turned off. The v_P voltage is maintained at 0 V until Q₃ is turned on at t = t₂ and the v_P voltage increases vertically from 0V to V_in. Given that i_S > 0, after Q₁ is turned off, the i_S current charges and discharges the C_oss of Q₁ and Q₂. The initial value of the current is the peak value of the i_S current. When the v_S voltage decreases to 0 V, the body diode of Q₂ turns on, clamping v_S to 0 V. When t = t₁, Q₂ turns on and Vs continues to maintain 0 V.

Given that the current of is in the dead time is regarded as a fixed value, the voltage of v_S decreases linearly. The v_S discharge falling interval is taken as half of its falling time, and the equivalent v_S waveform v_{S equivalent} can be drawn. From the equivalent v_S waveform, there is evidently a duty cycle D_a1 between t = t₁ and t = t₂, and its equivalent v_P and v_S are 0 V.

From Equation (29), the slope of i_P + i_S is controlled by v_P + v_S − 2V_out − v_Cs. When v_Cs is equal to (1 − 2D_P)V_in, and v_P + v_S is V_in, the current ripple offset can be achieved. However, in the dead time t = t₁~t₂ interval, except that v_Cs is slightly lower than (1 − 2D_P)V_in, and v_P + v_S is smaller than V_in. Given that v_P + v_S − 2V_out − v_Cs < 0, the change slope of i_P + i_S during the entire dead time interval is negative.

Second, we discuss the dead time interval (t₃~t_0+T).

When t = t₃, all switches are off. Given that i_P > 0, after the switch, Q₃ is turned off, the peak current of i_P charges and discharges the C_oss of Q₃ and Q₄. When the v_P voltage drops to 0 V, the body diode of Q₄ turns on and clamps v_P to 0 V. When t = t_0+T, Q₄ turns on, and v_P continues to maintain 0 V.

Note that the peak direct current of i_P will change with load conditions. Thus, v_P’s discharge slope will become rapid as load increases.

Given that i_S < 0 after Q₂ is turned off, the peak current of is charges and discharges C_oss of Q₁ and Q₂. When the v_S voltage rises to V_in, the body diode of Q₁ is turned on, clamping v_S to V_in; and when t = t_0+T, Q₁ is turned on and v_S continues to maintain V_in. Moreover, given that the average current of i_S is zero in the steady-state, the positive and negative peak currents of i_S are equal in magnitude. Therefore, the time for the v_S voltage in the dead time t = t₃~t_0+T to rise from 0 V to V_in is the same as the time for the v_S voltage to fall from V_in to zero in the dead time t = t₁~t₂.

Given that the currents of i_P and i_S in the dead time are regarded as fixed values, v_S and v_P change voltages linearly. If half of the time of the voltage linear change of v_P and v_S, then the equivalent waveforms of v_S and v_P, v_{S equivalent} and v_{P equivalent} can be drawn. From the equivalent v_S and equivalent v_P waveforms, it can be observed that there is a duty period D_a2 between time t₃ and t_0+T, and the equivalent v_P and v_S are both 0 V.

The slope of i_P + i_S is controlled by v_P + v_S − 2V_out − v_Cs. When v_CS is equal to (1 − 2D_P)V_in and v_P + v_S is V_in, the current ripple cancellation can be achieved. However, in the dead time t = t₃~t_0+T, except that v_Cs is slightly lower than (1 − 2D_P)V_in, v_P + v_S = V_in after the body diodes of Q₁ and Q₄ are turned on. Therefore, in the dead time interval’s front and back zone, given that v_P + v_S − 2V_out − v_Cs > 0, the slope of change of i_P+i_S rises slightly. However, the equivalent v_P and v_S waveforms shows a D_a2 equivalent duty cycle, and the v_P and v_S are both 0 V. The resulting falling slope of i_P + i_S is considerably larger than the other slight rising slopes. Hence, the overall i_P+i_S change continues to decrease in the dead time interval from t = t₃~t_0+T.

Lastly, we discuss the switch conduction interval (t₀~t₁, t₂~t₃):

The previous two dead time intervals show equivalent duty cycles D_a1 and D_a2. Hence, v_P and v_S are both 0 V. We define a new equivalent duty cycle D_A, where D_A = D_a1+D_a2. Given the converter’s new state, the previous derivation of v_A and V_Cs should be imitated and V_Cs voltage amplitude under the D_A duty cycle should be derived. From Figure 14, we can deduce that the circuit equation of the circuit state under the D_A duty cycle is as follows.

State 3, V_S = 0, V_P = 0, according to KCL and KVL, the equations can be written as follows:

$$i_S(s)=\frac{s^{-1}\left(0\hspace{0.17em}-v_A-V_{Cs}-V_{out}\right)}{s\left(L-M\right)},$$

(43)

$$i_P(s)=\frac{s^{-1}\left(0\hspace{0.17em}+v_A-V_{out}\right)}{s\left(L-M\right)},$$

(44)

$$v_A(s)=\left[i_S(s)-i_P(s)\right]M.$$

(45)

Substituting Equations (43) and (44) into Equation (45) can solve for v_A, and rename v_A in state 3 to v_A3 as follows:

$$v_{A3}(s)=\frac{s^{-1}\left(-V_{{}_{Cs}}\right)}{\frac{L-M}{M}+2}.$$

(46)

According to the steady-state, the volt-second balance of the inductance M can be written as Equation (47), where V_A1, V_A2, and V_A3 are the DC voltage levels obtained by the inverse Laplace transformation of v_A1, v_A2, and v_A3, respectively:

$$V_{A1}(1-D_P-D_A)+V_{A2}{D}_P+V_{A3}{D}_A=0.$$

(47)

Substituting Equations (35) and (39) into Equation (40) after the inverse Laplace transformation can be obtained as follows:

$$\frac{1}{\frac{L-M}{M}+2}\left[\left(V_{in}-V_{Cs}\right)\left(1-D_P-D_A\right)+\left(-V_{in}-V_{Cs}\right)D_P+\left(-V_{Cs}\right)D_A\right]=0.$$

(48)

Thereafter, solving (48) can obtain the modified equation of V_Cs as follows:

$$V_{Cs}=\left(1-2D_P-D_A\right)V_{in}.$$

(49)

From Equation (49), when D_A > 0, V_Cs will be lower than (1 − 2D_P)V_in. Although in the conduction interval (t₀~t₁, t₂~t₃), v_P + v_S = V_in, Equation (29) still cannot be established. Hence, the slope of i_P + i_S remains positive, and the ripple cannot be eliminated correctly.

This study proposes a dead time modulation method for low output ripple based on the preceding theoretical analysis. The modulation method is shown in Figure 17. Changing the timing of the on and off of the Q₃ switch can achieve the effect of low output ripple.

The dead time modulation method for low output ripple aims to adjust the equivalent v_P and v_S waveforms to complement each other. Therefore, the Q₃ switch is turned on in advance and turned off later. Figure 17 shows that the equivalent v_P and v_S can be completely complementary through the dead time modulation method.

The minimum switching dead time (t₂-t₁, t₃~t_0+T) of the remaining switches and the time of T_e1 and T_e2 can be obtained through the following design steps.

Step 1, design the minimum switch dead time.

The dead time t₁~t₂ and t₃~t_0+T interval must be sufficiently long to enable the completion of the voltage transition of v_P and v_S in the dead time. Hence, the minimum switching dead time must be longer than the maximum voltage transition time of v_P and v_S. The longest transition time occurs when the S-arm switch is turned off, and the time required for the S-arm C_oss capacitor to charge and discharge through the peak current of i_S. The peak current of i_S, I_{S_pk}, can be derived from the V_A1 obtained by the inverse Laplace transformation Equation (35), the ideal V_Cs in Equation (42), and duty cycle D_P:

$$I_{S\_pk}=\frac{\left(V_{in}-V_{A1}-V_{Cs}-V_{out}\right)\left(1-D_P\right)T_S}{2\left(L-M\right)},$$

(50)

where T_s is the switching period.

The voltage waveform conversion time of v_S can be derived as follows:

$$T_{S\_tran}=\frac{2C_{oss}\cdot V_{in}}{I_{S\_PK}}$$

(51)

Therefore, the minimum switching dead time must be designed to be longer than T_{S_tran}.

Step 2, design the trigger time of T_e1:

Figure 17 shows that the time of T_e1 is half of T_{S_tran}. The time of T_e1 will not change with the output load and is a fixed value. It is written as an equation as follows:

$$T_{e1}=\frac{T_{S\_tran}}{2}.$$

(52)

Step 3, design the T_e2 delay closing time:

Figure 17 shows that the time of T_e2 is jointly determined by T_{S_tran} and the time when v_P transition from V_in to 0 V. When Q₃ is off, the peak current of i_P charges and discharges the C_oss of the upper and lower bridge switches of the P-arm. Thus, the transition time of the v_P voltage is as follows:

$$T_{P\_tran}=\frac{2C_{oss}\cdot V_{in}}{I_{P\_PK}},$$

(53)

where I_{P_PK} is the output load current I_O plus I_{S_PK}, and its current value changes with load conditions.

Thereafter, the delayed closing time T_e2 is as follows:

$$T_{e2}=\frac{T_{S\_tran}-T_{P\_tran}}{2}.$$

(54)

Figure 18 and Figure 19 show the simulation results of the output current ripple of the stacked buck converter under the conventional dead time and low output ripple dead time modulation. The system architecture diagram and system parameters are shown in Figure 27 and Table 1, respectively. Moreover, R_L = 10 Ω, and the dead time is set to 100 nS, T_e1 = 32.67 nS, and T_e2 = 20.34 nS. Figure 18 and Figure 19 show that with the conventional dead time simulation results, the peak-to-peak value of the output current ripple is 2.4 A and the RMS value of the current ripple is 745 mA. Given that simulation results of the low output ripple dead time modulation, the peak-to-peak output current ripple decreases to 443.53 mA, and the RMS value of the current ripple is 15.78 mA. Note that the dead time modulation method of the low ripple output can significantly reduce the amount of current ripple. The result is consistent with the theoretical analysis.

6. Small-Signal Model and Compensation Design

The small-signal model of the independent inductor cascaded buck converter has been proposed in the literature [22]. Its small-signal model is extended to a coupled-inductor stacked buck converter, as shown in Figure 20. In particular, R_Sseq and R_Speq are the total series resistance on the series path, and the resistance value is the sum of the on-resistance of the power switch and resistance of the inductor winding. Furthermore, ESR_CS and ESR_CP are the equivalent series resistances of the C_S and C_P capacitors, respectively.

To verify the accuracy of the small-signal model and determine the disturbance transfer function G_dv of duty to v_out under different load conditions, the circuit parameters are shown in Table 1. R_L is substituted into 2.5 Meg Ω and 2.5 Ω. Using the actual circuit operation and small-signal model, we use the simulation software to run the individual G_dv Bode diagrams, respectively G_{dv_circuit} and G_{dv_model}, as shown in Figure 21. Moreover, Figure 21 shows that G_{dv_circuit} and G_{dv_model} are consistent with each other, which proves the correctness of the small-signal model. Moreover, the worst case is when RL = 2.5 Meg Ω. Therefore, the compensator should be designed under the converter’s no-load condition. Given that G_{dv_circuit} is consistent with G_{dv_model}, the following articles will use G_dv notation to represent the disturbance transfer function of duty to v_out, where G_dv = G_{dv_model} = G_{dv_circuit}.

When considering the use of boundary limit control, the stacked buck converter’s small-signal model within the boundary-limited interval should be discussed. Given that the S-arm’s duty disturbance in the boundary-limited interval is 0, the small-signal model in the boundary control interval can ground the S-arm’s duty disturbance in Figure 20. This result becomes the small-signal model of the stacked buck converter of the coupled inductance forms in the boundary limit interval. The model is shown in Figure 22.

Substitute the R_L of Figure 22 into 2.5 Meg Ω, plot the disturbance transfer function G_{dv_bd} of duty to v_out in the boundary control interval, and place it in Figure 23 together with the G_dv in Figure 21 for comparison. Figure 23 shows that the Bode plots of G_dv and G_{dv_bd} are extremely different regardless of the changes in gain and phase. Such characteristics will make it challenging to design the compensator with one compensator while satisfying the two closed loops’ high-frequency bandwidth and stability.

If the compensator’s design aims to satisfy G_dv and G_{dv_bd}, then the easiest method is to reduce the closed-loop bandwidth. Therefore, the first compensator example’s design parameters are shown in Equation (55), using single-pole compensation. Figure 24 shows the closed-loop gain under the first type of compensator, where T_v = G_dvC_ompType1 and T_{v_db} = G_{dv_bd}C_ompType1. Note that T_v and T_{v_bd} are stable and contain sufficient gain and phase margins. However, the closed-loop bandwidth is extremely narrow.

$$Com{p}_{Type1}(s)=\frac{2\pi \cdot 10}{330}\frac{1}{s}.$$

(55)

As the boundary control mode will eventually return to the ordinary operation mode, and G_dv is used as the basis for the final system stability, the second type of compensator design concept aims to design only for G_dv and disregard the stability of G_{dv_bd}. The design parameters of the second type of compensator are shown in Equation (56). Figure 25 shows the closed-loop gain using the second type of compensator, where T_v = G_dvC_ompType2 and T_{v_db} = G_{dv_bd}C_ompType2. Note that only the closed-loop gain of G_dv is stable, while the closed-loop gain of G_{dv_bd} has insufficient GM and PM in two places. Although the closed-loop bandwidth of G_dv is increased, the system has unstable factors in the boundary limit control mode.

$$Com{p}_{Type2}(s)=\frac{\left(1+\frac{s}{2\pi \cdot 800}\right)\left(1+\frac{s}{2\pi \cdot 800}\right)}{\left(1+\frac{s}{2\pi \cdot 5}\right)\left(1+\frac{s}{2\pi \cdot 14k}\right)\left(1+\frac{s}{2\pi \cdot 16k}\right)}.$$

(56)

Figure 26 compares the simulation results of the system transient response of the first and second compensators. The load resistance is switched from R_L = 2.5 Meg Ω to R_L = 2.5 Ω when R_L is t = 70 mS. When t = 120 mS, the load resistance is switched from R_L = 2.5 Ω to 2.5 Meg Ω again. Figure 26 shows that the transient response of the first type of compensator is considerably slow, the boundary limit mode is not triggered, and the system is stable but takes a long time to reach the steady-state. However, the transient response of the second type of compensator has a short recovery time. It triggers the boundary limit mode. Hence, the performance of undershoot and overshoot is better, the output voltage is stabilized for a short time, and the system returns to stability in the general operation mode. Figure 26 shows that with the second type of compensator, the system can eventually return to stability even though T_{v_db} has unstable factors.

7. Implementation Verification Results

To verify the effectiveness of the low ripple dead time modulation method proposed in this study, a prototype circuit is actually made for verification. Figure 27 shows the implementation circuit diagram. Table 1 presents the implementation circuit parameters. The dead time modulation parameters are full load as an example, using the modulation parameters when R_L = 2.5 Ohm. The relevant parameters are shown in

Table 2. Dead time modulation parameters.

Symbols	Parameter Names	Specifications
Tdead time	Dead time	100 ns
Te1	The time difference between Q4 switch off and Q3 switch on	32.67 ns
Te2	The time difference between Q2 switch off and Q3 switch off	28.37 ns

.

Figure 28 shows the waveforms of v_P, v_S, i_P, and i_S, using the conventional dead time and low output ripple dead time modulation with R_L = 2.5 Ω. Figure 28a shows that using the conventional dead time stacked buck converter, the i_P and i_S current waveforms both show a steep falling slope in the dead time interval, and it is expected that the current ripple of i_P + i_S cannot be accurately cancellate. Moreover, Figure 28b shows that the stacked buck converter using the low output ripple dead time modulation, the current waveforms of i_P and i_S present a reverse slope in the dead time interval, and the current ripple of the entire switching cycle presents a complete triangle wave. It can be expected to accurately cancellate the current ripple of i_P + i_S.

Figure 29 shows waveforms of v_P, v_S, i_P + i_S(AC), and i_o, using the conventional dead time with R_L = 2.5 Ω. Figure 29 shows that using the conventional dead time stacked buck converter, in the dead time interval (t₁~t₂, t₃~t_0+T), because v_P + v_S < Vin, the current ripple of i_P + i_S has a steep falling slope.

Figure 30 shows waveforms of v_P, v_S, i_P + i_S(AC), and i_o, using the low output ripple dead time modulation with R_L = 2.5 Ω. Figure 30 shows that using the low output ripple dead time modulation, in the dead time interval (t₁~t₂, t₃~t_0+T), since the equivalent voltage of the switching node voltage is complementary, the ripple of i_P + i_S can be minimized. Because the switching node’s voltage has switching noise, and the parasitic capacitance C_oss of the switch will change the capacitance value with the difference of the cross voltage, the calculated T_e1 and T_e2 are different from the time required on the existing system. Therefore, the current ripple elimination effect in practice is not as good as the simulation result. However, it can be seen from the actual measurement results that the ripple of i_P + i_S has been greatly reduced, and the maximum peak to peak amount comes from the switching noise rather than the operation interval where v_P and v_S voltage overlap.

Figure 31 shows the waveforms of v_P, v_S, i_P, and i_S, using the conventional dead time and low output ripple dead time modulation with R_L = 2.5 Ω. Figure 31a shows that using the conventional dead time stacked buck converter, the peak-to-peak ripple current of i_P + i_S is 2.09 A, and its RMS value is 551 mA. Moreover, Figure 28b shows that the stacked buck converter using the low output ripple dead time modulation has a peak-to-peak ripple current of i_P + i_S of 559 mA and its RMS value is 91 mA. The implementation results show that the use of the low output ripple dead time modulation can significantly reduce the current ripple of i_P + i_S.

8. Conclusions

This study aims to apply low output current ripple, comprehensively discuss existing solutions, and review their advantages and disadvantages. To save the volume of the converter and increase the transient response of the system at medium switching frequencies, a stacked buck converter was eventually selected to meet the requirements of eliminating current ripples under any duty cycle and reducing the inductance of magnetic components. Individual improvements were made to enhance the transient response and current ripple elimination function.

In terms of increasing transient response, this research proposes a boundary limit control method to replace the existing RC delay control method. The proposed method avoids the specific shortcoming that the RC delay control method cannot accelerate transient response after the compensator is saturated. Simultaneously, the small-signal model of the coupled-inductor stacked buck converter is derived. A complete description of the closed-loop compensation design under the boundary limit control method is also provided with the simulation results as support.

In terms of the current ripple elimination function, a low output ripple dead time modulation is proposed to correct the ripple elimination effect that is reduced owing to the dead time. The theoretical derivation of the dead time modulation method is properly explained in this research. The simulation and actual results show that the low output ripple dead time modulation can significantly improve the output current ripple elimination effect under the conventional dead time modulation method.