A Family of Single-Stage, Buck-Boost Inverters for Photovoltaic Applications

Abstract

This paper introduces a family of single-stage buck-boost DC/AC inverters for photovoltaic (PV) applications. The high-gain feature was attained by applying a multi-winding tapped inductor, and thus, the proposed topologies can generate a grid-level AC output voltage without using additional high step-up stages. The proposed topologies had a low component count and consisted of a single magnetic device and three or four power switches. Moreover, the switches were assembled in a push-pull or half/full-bridge arrangement, which allowed using commercial low-cost driver-integrated circuits. In this paper, the operation principle and comparison of the proposed topologies are presented. The feasibility of the proposed topologies was verified by simulations and experimental tests.

1. Introduction

The continuous development of distributed photovoltaic (PV) power generation systems arouses much interest in MIEs/MICs, also known as microinverters. Unlike the string inverters using series-connected PV panels to achieve a high voltage, microinverters are designed to directly connect a single PV panel with a low voltage to the grid while providing an individual MPPT and, in turn, avoiding mismatch losses within the PV array. The “plug-and-play” feature of the microinverter allows the incorporation of PV modules of different types into a single array, also facilitating its future expansion and maintenance. To some extent, the labor cost can also be reduced.

In practice, the low DC voltage produced by the PV module (e.g., 20–30 V) and the relatively high AC voltage of the utility (e.g., 230 V RMS) imply that a high step-up DC-DC stage followed by a regular inverter is required. Such a straightforward scheme is referred to as the two-stage approach and is quite popular due to its ease of implementation and control. Yet, the two-stage solution is costly and the efficiency is reduced. The single-stage microinverter that combines both the voltage step-up and inversion functions in one power stage can possibly lead to a lower component count and a reduced cost. Thus, the single-stage inverters have been the focus of recent research activities. Numerous single-stage boost-derived topologies have been proposed in the literature due to the inherent voltage step-up capability [1]. The limited voltage gain of the boost-type converter can be improved by means of integrating tapped inductors, as discussed in [2,3].

Additionally, due to the voltage step-up/down capability, the buck-boost derived topologies can also be a viable solution for single-stage inverter applications. Thus, a number of buck-boost type single-stage inverters with low component counts were reported. For instance, single-stage buck-boost inverters with only three switches were proposed in [4,5], as shown in Figure 1a, where a tapped inductor was used as a regular inductor in one half-line cycle and as a fly-back transformer in the subsequent half-line cycle. Unfortunately, this type of inverter cannot attain the required voltage step-up. As shown in Figure 1b, a four-switch, single-stage, buck-boost inverter was then presented in [6], which employed a tapped inductor and the SEPIC converter to increase the voltage gain. However, according to the operational principles, the turns ratio of the tapped inductor has to be equal to unity, and consequently, the voltage gain is still limited. Topologies in [7,8] also have only four switches to realize the single-stage conversion and have the merit of a common terminal between input and output ports. Figure 1c shows the circuit diagram of the converter in [7]. Another single-stage, buck-boost inverter has the advantage of reduced magnetic volume and low leakage currents [9]. The topologies in [10,11,12] were conceived to also eliminate the leakage currents, but the number of active switches is increased, as observed in Figure 1d. Furthermore, a differential buck-boost inverter with active power decoupling capability was proposed in [13,14], where no extra components are required. It has only four switches; on the contrary, a rather complicated control method is needed. An active buck-boost inverter using an “AC/AC unit” to realize the buck-boost conversion was introduced in [15,16], as presented in Figure 1e. Yet, each unit consisted of four switches, and, thus, in total, eight switches are needed for the microinverter. The authors of [17] expanded this idea to cascaded multilevel buck-boost inverters using H-bridges for each PV panel and a central AC/AC unit. To improve the efficiency and system reliability, a solution for the current shoot-through issue was discussed in [18,19] to eliminate the dead-time effect. Moreover, ref. [18] presented a converter with eight switches and four inductors, while [19] has four switches, four diodes, and six inductors, which make the topologies quite complicated. The topology in [20] has merits of a wide input voltage range, low leakage currents, small grid current ripples, and low common-mode voltages. However, as seen in Figure 1f, it has four high-frequency switches and two bidirectional switches, which are realized by connecting back-to-back MOSFETs in series. Doing so significantly increases the total number of switches (i.e., eight). Although the ideas of [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20] are very interesting, their attained voltage gain is comparable to the traditional buck-boost converter.

Additional attempts to increase the gain of the buck-boost derived topologies were reported. For example, in [21] a series connection between a buck-boost converter and the PV array was introduced to have a higher gain, but the gain improvement was limited. The topology in [22], see Figure 2a, employed a switched inductor, which can improve the gain by the factor of $\sqrt{2}$ over that of the traditional buck-boost converter. However, in total, the topology in [22] had four switches, eight diodes, and four inductors. The tapped-inductor buck-boost inverter topologies presented in [23,24], as shown in Figure 2b,c, respectively, can achieve a much higher voltage gain than the traditional ones, but the switch counts were up to eight, whereas [25,26] had five switches, as presented in Figure 2d. The advantage of the topologies in [25,26] is that only one high-frequency switch was used, and thus, the switching losses were lower. For the topologies in Figure 2, the main characteristics are further compared in

Table 1. Comparison of the main topologies of the existing single-stage, buck-boost inverters.

Ref.	Switches Count	Diodes Count	Inductors Count	Input Voltage	Output Voltage	Output Power	Efficiency
[22]	4	8	4	20 V	314 V	100 W	/
[23]	8	0	1 Tapped	100–200 V	110 V	500 W	>96%
Figure 2b [24]	8	0	1 Tapped	40 V	230 V	/	/
[25]	5	2	1 Tapped	60 V	230 V	100 W	86%

. According to Table 1, most of the topologies had a high semiconductor count, from 7 up to 12. The experimental efficiency of more than 96% was reported in [23]. However, the test was with an input of 100–200 V and a 110-V output, which cannot support the performance with a high-voltage step-up. An efficiency of 86% was achieved in [25] with a 60-V input, a 230-V output, and 100-W output power, which is reasonable for a tapped-inductor buck-boost inverter. Yet, the experimental efficiency of the other two proposals was not reported clearly in the literature.

The high switch count of the reviewed converters, the resulting circuit complexity, higher cost, and lower efficiency, counter the main design goal of producing a simple and low-cost single-stage inverter. Therefore, more efforts have been made to develop more single-stage, buck-boost inverter topologies with a high gain and a low switch count. Recently, a family of single-stage, buck-boost rectifiers with high power factor were proposed in [27], analyzed, and verified in [28]. With the same principles, a family of tapped-inductor, buck-boost microinverters can be derived by reversing the power flow. This calls for the application of bidirectional switches. The proposed tapped-inductor, buck-boost type inverter family is illustrated in Figure 3. The basic operation and the preliminary simulation study of the two topologies in the family were reported in [29,30], while the converters have not been experimentally verified, and the design considerations are not fully addressed.

Accordingly, in addition to the topologies in [29,30], this paper further introduces two more practical topologies and all four topologies in the family are presented in detail. More importantly, a comparison of the proposed family was done thoroughly in terms of the component count, the voltage conversion ratio, the voltage stress, the peak current stress, and the RMS current stress, which can be used in the design phase. What is more, more detailed simulation studies for all the topologies in the family were presented. A prototype of the SSBBI of the proposed family was built and experimental results are illustrated in this paper. The rest of the paper is organized as follows. Section 2 introduces the proposed family, and the operation principles of the proposed family are demonstrated on a topology (i.e., the SSBBI) in Section 3. Circuit characteristics are discussed in Section 4, including the analysis of the conversion ratio, turns ratio, and duty cycle constraints together with voltage and current stresses, as design considerations. Simulation results are given in Section 5, where the comparison of the family is provided. Experimental tests are presented in Section 6 to validate the discussion. Finally, concluding remarks are provided in Section 7.

2. Single-Stage, Buck-Boost Inverter Family

As shown in Figure 3, the proposed inverter family makes use of a tapped inductor to attain a high step-up voltage conversion ratio. This helps to generate a grid-compatible voltage from a low DC voltage source. Two, three, and four winding, tapped-inductor structures are needed. The turns ratio, n, of the tapped inductor is defined as follows. For the two-windings inverter topology in Figure 3a, n = N₂/N₁. The three-windings topology in Figure 3b has an equal number of primary turns, N₁ = N₂, and the turns ratio is defined as n = N₃/N₁ = N₃/N₂. The topologies in Figure 3c,d rely on a symmetrical tapped-inductor structure with an equal turns ratio, defined as n = N₃/N₁ = N₄/N₂.

The topology in Figure 3a includes a floating source, a single ground-referenced PWM switch, Q_1, and a ground-referenced line frequency unfolding bridge, Q₂–Q₅. The topology in Figure 3b includes a grounded source, a ground-referenced push-pull pair of PWM switches, Q₁–Q_2, and a floating line frequency unfolding totem pole, Q₃–Q₄. The topology in Figure 3c includes a floating source, a single ground-referenced PWM switch, Q_1, and a floating line frequency unfolding totem pole, Q₂–Q₃. The topology in Figure 3d includes a grounded source and a ground-referenced full bridge. Here, the lower switches, Q₁–Q_3, are PWM devices, whereas the high switch pair can perform either a simple line frequency unfolding function or be operated as synchronous rectifiers. Since the body diodes of the high switches are exploited as rectifiers, the reverse recovery capability should be considered. This can be an issue for silicon-based devices, while the emerging GaN MOSFETs can deliver the required performance.

To summarize, the proposed inverters have the merits of:

(1)

Generating a grid-level AC output voltage from a relatively low DC input voltage without extra high gain DC-DC converters.

(2)

Having a low component count as single-stage topologies consisting of a single magnetic device and three or four switches.

(3)

A push-pull or half/full-bridge arrangement of the switches, where the commercial low-cost driver-integrated circuits can be easily used.

The proposed tapped-inductor, buck-boost inverter family in Figure 3 was then studied through simulations. The exploration indicated that the topology in Figure 3d can also help to avoid much of the practical grounding, driving, and controller interface issues. Additionally, considering the lowest semiconductor count (see

Table 2. Comparison of the component count of the tapped-inductor, buck-boost inverter family.

Topologies	Switches	Diodes	Windings	Filter Cap.
Figure 3a	5	1	2	1
Figure 3b	4	2	3	1
Figure 3c	3	2	4	1
Figure 3d	4	0	4	1

), the topology in Figure 3d appears as the most attractive candidate in the family. Hereafter, this topology (i.e., the SSBBI in Figure 3d) is considered in the following detailed analysis to exemplify the converter operation.

3. Operation Principles of the Proposed SSBBI

As shown in Figure 3d, the power stage of the proposed SSBBI included four switches, Q₁–Q₄, in a full-bridge arrangement. A tapped inductor, L_cp, with four windings was employed. The output filter capacitor here was C_o and the load was an equivalent resistance, R_L, for stand-alone applications. The voltage across them was the AC output, v_o. As mentioned previously, two symmetrical pairs of windings were used for the tapped inductor. The turns of the primary windings must be the same, i.e., N₁ = N₂. Similarly, equal secondary windings were used, i.e., N₃ = N₄. The turns ratio of the tapped inductor was then obtained as n = N₃/N₁ = N₄/N₂. The SSBBI can generate a bipolar output voltage with the help of the symmetrical structure, and thus, it can achieve the DC-AC inversion. The desired output voltage can be obtained using any common control strategy of a constant frequency duty cycle. The operation principle is detailed in the following.

Supposing the converter was operating in the CCM, the SSBBI had two switching states in each half-line cycle, denoted as states A and B in the positive half-line cycle and A’ and B’ in the negative half-line cycle. The switching states of the four switches are listed in

Table 3. Switching states of semiconductor devices.

Switches	Positive Output Voltage		Negative Output Voltage
	State A	State B	State A’	State B’
Q1	On	Off	Off	Off
Q2	Off	On	On	On
Q3	Off	Off	On	Off
Q4	On	On	Off	On

, and further illustrated in Figure 4.

According to the equivalent circuit of state A shown in Figure 4a, the state started at the beginning of each switching cycle in the positive half-line cycle. Here, the switch Q₁ was turned on and the state lasted for the duration of DT_s. In this state, the tapped inductor was charged by the input source, V_in, through the primary winding N₁. The output capacitor, C_o, can sustain the output voltage on the load. As shown in Figure 4b, state B began when the switch Q₁ was turned off and lasted for the duration of (1 − D)T_s. In this state, the energy stored in the tapped inductor was discharged and released to the output side through all the four windings of the tapped inductor. During states A and B, when the output voltage was positive, Q₁ and Q₂ were switched, while the switch Q₃ was maintained off and Q₄ remained on. In comparison, the states A and B were replaced by the states A’ and B’ during the negative output half-line cycle due to the symmetrical operation principle. The equivalent circuits of state A’ and B’ are shown in Figure 4c,d, respectively.

The key waveforms of the SSBBI are described in Figure 5, where S_Q1–S_Q4 are the gating signals for Q₁–Q₄ switches, respectively. Due to the symmetry of the SSBBI, it was sufficient to consider its operation during the positive half cycle. When Q₁ was turned on and Q₂ was turned off, the primary winding of the tapped inductor was energized. This caused the magnetizing current of the tapped inductor to ramp up. When Q₁ was turned off and Q₂ was turned on, the tapped inductor was discharged to support the output through all the windings. Thus, the magnetizing current of the tapped inductor ramped down. Notably, in terms of control of the converter, in grid-tied applications, the task of the control circuit is to shape the average output current, I_o, into a sinusoidal waveform (see i_N4 in Figure 5), while the controller should regulate the output voltage in stand-alone applications.

4. Analysis and Design Considerations of the Proposed SSBBI

4.1. CCM Voltage Gain

In the CCM, the tapped inductor, L_cp, was charged by the input voltage source, V_in, only through the primary winding N₁ or N₂ during the time of DT_s (state A or A’). However, the output voltage, v_o was stressed on all the four windings of the tapped inductor during the time of (1 − D)T_s (state B or B’). Thus, according to the volt-sec balance, it gives

$${\displaystyle {\int }_0^{D{T}_s}{V}_{in}dt+}{\displaystyle {\int }_{D{T}_s}^{T_s}\frac{-v_o}{2n+2}dt=0}$$

(1)

which led to that the quasi-steady-state voltage gain of the SSBBI to be calculated as

$$M=\frac{v_o}{V_{in}}=2\left(n+1\right)\frac{D}{1-D}.$$

(2)

It can be recognized from Equation (2) that the SSBBI was a buck-boost type topology and had the function of voltage step-up/down. A higher gain can be achieved by choosing a proper turns ratio, n.

4.2. Turns Ratio and Duty Cycle Constraints

It should be noticed that when the tapped inductor is discharged to the output side (see states B and B’), the voltage across the primary winding must be always less than the DC input voltage, V_in. Accordingly,

$$\frac{v_o}{2\left(n+1\right)}<V_{in}.$$

(3)

In this way, it prevented the discharging current of the tapped inductor to go back to the DC input source through the body diode of the switch at the lower side. Such a condition should be avoided since the output voltage would be clamped and the circulating current will lower the efficiency as well. With this concern, the turns ratio should be designed sufficiently large to make the SSBBI work properly. Thus,

$$n>\frac{V_{o\max }}{2V_{in}}-1.$$

(4)

Moreover, it can be obtained by combining (2) and (3) that

$$\frac{D}{1-D}<1.$$

(5)

Subsequently, the maximum duty ratio, D_max, should be limited to

$$D_{\max }<0.5.$$

(6)

4.3. Voltage and Current Stress

4.3.1. Voltage Stress of Switches

During state A, the input voltage, V_in, was imposed on the primary winding N₁ of the tapped inductor when the switch Q₁ was on. Therefore, the voltage stress on the switch Q₃ was the sum of the input voltage and the induced voltage across the primary winding N₂, which was twice the input voltage, V_in as

$$V_{Q3\max }=2V_{in}.$$

(7)

Meanwhile, since the switch Q₄ was in on-state, the voltage across the four windings of the tapped inductor as well as the output voltage, v_o, was stressed on the off-state switch Q₂. Thus, the maximum stress of the Q₂ will lead to:

$$V_{Q2\max }=2\left(n+1\right)V_{in}+V_{o\max }.$$

(8)

The same results can be obtained for the switches Q₁ and Q₄ in state A’ because of the symmetrical operation of the SSBBI. The voltage stresses for all the switches are summarized in

Table 4. SSBBI switch voltage and current stresses.

Switches	Voltage Stress	Current Stress
		Peak	RMS
Q1, Q3	2Vin	$2\left(n+1\right)I_m+\frac{I_m{V}_m}{V_{in}}$	$I_{acrms}\sqrt{\frac{3}{8}\frac{V_m^2}{V_{in}^2}+\frac{8}{3\pi }\frac{\left(n+1\right)V_m}{V_{in}}}$
Q2, Q4	2(n+1)Vin+Vomax	$I_m^{}+\frac{I_m{V}_m}{2\left(n+1\right)V_{in}}$	$I_{acrms}^{}\sqrt{1+\frac{4}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$

.

4.3.2. Analysis of Current Stress

It was assumed that the output voltage and current of the SSBBI were ideally in phase without harmonics as

$$\{\begin{array}{l}{v}_o\left(t\right)=V_m\sin \omega t\\ i_o\left(t\right)=I_m\sin \omega t\end{array}$$

(9)

Furthermore, by applying Equations (2) and (9), and replacing the steady-state duty ratio D with the time-varying duty ratio d(t), it can be obtained that

$$\frac{v_o\left(t\right)}{V_{in}}=2\left(n+1\right)\frac{d\left(t\right)}{1-d\left(t\right)}=\frac{V_m\sin \omega t}{V_{in}}$$

(10)

from which the duty ratio, d(t), can be derived as

$$d\left(t\right)=\frac{V_m\sin \omega t}{2\left(n+1\right)V_{in}+V_m\sin \omega t}.$$

(11)

For the proposed SSBBI, the average output current equaled to the average current of the upper switch, 〈i_o(t)〉 = i_Q2(t)[1 − d(t)], as shown in Figure 6. Therefore, assuming that the current ripples are negligible, the current amplitude of the switch Q₂ can be obtained by combining Equations (9) and (11) as

$$i_{Q2}\left(t\right)=\frac{\langle i_o\left(t\right)\rangle }{1-d\left(t\right)}=I_m\sin \omega t+\frac{I_m{V}_m{\sin }^2\omega t}{2\left(n+1\right)V_{in}}.$$

(12)

Thus, the maximum current of the switch Q₂ at the peak output voltage can be obtained as

$$I_{Q2\max }=I_m^{}+\frac{I_m{V}_m}{2\left(n+1\right)V_{in}}.$$

(13)

The squared RMS current of the switch Q₂ within a switching period is:

$$i_{Q2rmsTs}^2=\frac{1}{T_s}{\displaystyle {\int }_t^{t+T_s}{i}_{Q2}^2\left(t\right)}dt=\left[1-d\left(t\right)\right]i_{Q2}^2\left(t\right).$$

(14)

Subsequently, the squared value of the switch RMS current is:

$$I_{Q2rms}^2=\frac{1}{T/2}{\displaystyle {\int }_0^{T/2}{i}_{Q2rmsTs}^2}dt$$

(15)

with T being the generated output voltage period. Substituting Equations (11), (12), and (14) into (15) yields

$$I_{Q2rms}^2=\frac{1}{T/2}{\displaystyle {\int }_0^{T/2}{I}_m^2{\sin }^2\omega t+\frac{I_m^2{V}_m{\sin }^3\omega t}{2\left(n+1\right)V_{in}}}dt=I_{acrms}^2\left(1+\frac{4}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}\right).$$

(16)

Thus, the RMS current of the switch Q₂ is obtained as

$$I_{Q2rms}=I_{acrms}^{}\sqrt{1+\frac{4}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}.$$

(17)

The current amplitude of the lower switch Q₁ is 2(n + 1) times higher than the upper switch current due to the function of the tapped-inductor turns ratio, n. Thus,

$$i_{Q1}\left(t\right)=2\left(n+1\right)i_{Q2}\left(t\right)=2\left(n+1\right)I_m\sin \omega t+\frac{I_m{V}_m{\sin }^2\omega t}{V_{in}}.$$

(18)

Therefore, the peak current through the lower switch, Q₁, is:

$$i_{Q1\max }=2\left(n+1\right)I_m+\frac{I_m{V}_m}{V_{in}}.$$

(19)

The squared value of the lower switch RMS current through the switching period, T_s, is:

$$i_{Q1rmsTs}^2=\frac{1}{T_s}{\displaystyle {\int }_t^{t+T_s}{i}_{Q1}^2\left(t\right)}dt=d\left(t\right)i_{Q1}^2\left(t\right).$$

(20)

Since the low switch conducts for half the line period, the squared value of its RMS current on the line period scale can be calculated as:

$$I_{Q1rms}^2=\frac{1}{T}{\displaystyle {\int }_0^T{i}_{Q1rmsTs}^2}dt.$$

(21)

Substituting Equations (11), (18), and (20) into (21), gives

$$I_{Q1rms}=I_{acrms}\sqrt{\frac{3}{8}\frac{V_m^2}{V_g^2}+\frac{8}{3\pi }\frac{\left(n+1\right)V_m}{V_{in}}}.$$

(22)

With the above analysis, the voltage and current stresses of the SSBBI are summarized in Table 4.

5. Simulation Results and Comparison

5.1. Basic System Operation

Referring to Figure 3d, simulations were carried out to verify the feasibility of the proposed SSBBI in PSIM software. The key simulation parameters were: Output power P_o = 200 W, input voltage V_in = 48 V, output voltage v_o = 110 V/60 Hz, switching frequency f_s = 20 kHz, tapped-inductor magnetizing inductance L_m = 150 μH, turns ratio n = 1.5, and output capacitance C_o = 2 μF. Several control strategies can be applied to control the proposed SSBBI. Initially, to validate the basic operational principle, the simple open-loop SPWM was used. Simulation results are shown in Figure 7, which demonstrates that the SSBBI can generate the desired output voltage. This provides proof of concept of the proposed circuit family for single-stage microinverter applications.

Furthermore, as can be observed in Figure 7a, the circuit simulation results (key waveforms) were in a close agreement with the analytical results in Figure 5. The gate-driving signals are further shown in Figure 7b to demonstrate the controllability of the converter. Moreover, the output voltage of the proposed inverter is given in Figure 7c, as well as the voltage across the switches. It can be observed in Figure 7c that the SSBI can produce high-quality sinusoidal outputs, and the voltage stresses on the switches were also in consistency with the analysis. Additionally, the currents flowing through the power devices under the 200-W output power are presented in Figure 7d, which again agrees with the theoretical analysis presented in Section 4.

The analytical results were further verified by simulations. Key simulated waveforms of the proposed topologies in Figure 3a–c are shown in Figure 8. It is observed in Figure 8 that all the topologies of the proposed family can generate a good-quality sinusoidal output voltage. Simulations also support the theoretically predicted results of the current stress analysis. When comparing the performance of the topologies in Figure 3a–c with the SSBBI, it can be seen that the four topologies had similar high-quality output voltage waveforms and the comparable current stress at the same output power. However, the SSBBI had the lowest semiconductor count and the easier driver implementation, which proved again the competitiveness of the SSBBI in the family.

5.2. Comparison of the Proposed Single-Stage, Buck-Boost Inverter Family

To better appreciate the merits of the proposed single-stage inverter family, a detailed comparison of the proposed topologies is conducted in this section. The voltage conversion ratio of the proposed family and its derivation under the assumption of the CCM operation is summarized in

Table 5. Comparison of the voltage conversion ratio of the proposed topologies.

Topology	Voltage Gain M = vo/Vin
		Figure 3a	$M_a=\left(n+1\right)\frac{D}{1-D}$
Figure 3b	$M_b=\left(n+2\right)\frac{D}{1-D}$
Figure 3c	$M_c=\frac{\left(n+1\right)}{2}\frac{D}{1-D}$
SSBBI	$M=2\left(n+1\right)\frac{D}{1-D}$

. The benchmarking of the proposed topologies’ voltage conversion ratio with the same turns ratio n = 2 is further shown in Figure 9a and with the same duty ratio D = 0.5 in Figure 9b. According to Table 5 and Figure 9, the SSBBI had the largest voltage gain in the family. The peak voltage stress analysis was performed and is summarized in

Table 6. Comparison of the voltage stress.

Topology	Voltage Stress
	Low Side Switches	High Side Switches	Diodes
Figure 3a	$V_{in}+\frac{V_{o\max }}{n+1}$	Vomax	(n+1)Vin+Vomax
Figure 3b	2Vin	(n+2)Vin+Vomax	(n+2)Vin+Vomax
Figure 3c	$V_{in}+\frac{2V_{o\max }}{n+1}$	2Vomax	$\frac{\left(n+1\right)V_{in}}{2}+V_{o\max }$
SSBBI	2Vin	2(n+1)Vin+Vomax	/

. Lastly,

Table 7. Comparison of the peak current stress.

Topology	Peak Current Stress
	Low Side Switches	High Side Switches	Diodes
Figure 3a	$\left(n+1\right)I_m+\frac{I_m{V}_m}{V_{in}}$	$I_m^{}+\frac{I_m{V}_m}{\left(n+1\right)V_{in}}$	$I_m^{}+\frac{I_m{V}_m}{\left(n+1\right)V_{in}}$
Figure 3b	$\left(n+2\right)I_m+\frac{I_m{V}_m}{V_{in}}$	$I_m^{}+\frac{I_m{V}_m}{\left(n+2\right)V_{in}}$	$I_m^{}+\frac{I_m{V}_m}{\left(n+2\right)V_{in}}$
Figure 3c	$\frac{\left(n+1\right)}{2}{I}_m+\frac{I_m{V}_m}{V_{in}}$	$I_m^{}+\frac{2I_m{V}_m}{\left(n+1\right)V_{in}}$	$I_m^{}+\frac{2I_m{V}_m}{\left(n+1\right)V_{in}}$
SSBBI	$2\left(n+1\right)I_m+\frac{I_m{V}_m}{V_{in}}$	$I_m^{}+\frac{I_m{V}_m}{2\left(n+1\right)V_{in}}$	/

and

Table 8. Comparison of the RMS current stress.

Topology	RMS Current Stress
	Low Side Switches	High Side Switches	Diodes
Figure 3a	$I_{acrms}\sqrt{\frac{3}{4}\frac{V_m^2}{V_{in}^2}+\frac{8}{3\pi }\frac{\left(n+1\right)V_m}{V_{in}}}$	$I_{acrms}^{}\sqrt{\frac{1}{2}+\frac{4}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$	$I_{acrms}^{}\sqrt{1+\frac{8}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$
Figure 3b	$I_{acrms}\sqrt{\frac{3}{8}\frac{V_m^2}{V_{in}^2}+\frac{4}{3\pi }\frac{\left(n+2\right)V_m}{V_{in}}}$	$I_{acrms}^{}\sqrt{\frac{1}{2}+\frac{4}{3\pi }\frac{V_m}{\left(n+2\right)V_{in}}}$	$I_{acrms}^{}\sqrt{\frac{1}{2}+\frac{4}{3\pi }\frac{V_m}{\left(n+2\right)V_{in}}}$
Figure 3c	$I_{acrms}\sqrt{\frac{3}{4}\frac{V_m^2}{V_{in}^2}+\frac{4}{3\pi }\frac{\left(n+1\right)V_m}{V_{in}}}$	$I_{acrms}^{}\sqrt{\frac{1}{2}+\frac{8}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$	$I_{acrms}^{}\sqrt{\frac{1}{2}+\frac{8}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$
SSBBI	$I_{acrms}\sqrt{\frac{3}{8}\frac{V_m^2}{V_{in}^2}+\frac{8}{3\pi }\frac{\left(n+1\right)V_m}{V_{in}}}$	$I_{acrms}^{}\sqrt{1+\frac{4}{3\pi }\frac{V_m}{\left(n+1\right)V_{in}}}$	/

present the results of the peak current and the RMS current stress analysis of semiconductor devices. As can be seen from Table 6, Table 7 and Table 8, the voltage and current stresses of the SSBBI were comparable to other topologies in the family. Moreover, as mentioned previously, the SSBBI component count was lower by one or two diodes. Thus, the SSBBI had the optimum circuit composition and characteristics in the family.

6. Experimental Results and Discussion

6.1. Experimental Results of SSBBI

A 100-W laboratory prototype of the proposed SSBBI was built and tested. The key operation parameters were: Input voltage, V_in = 48 V; output voltage, v_o = 110 V/60 Hz; and switching frequency, f_s = 20 kHz. The prototype’s view and the components arrangement are shown in Figure 10. The board was designed larger to reserve additional space needed for experimenting with various snubbers and control schemes. The main components of the prototype are summarized in

Table 9. Main components of the prototype of the proposed SSBBI.

Components	Value/Model
		High side switches	IPW90R340C3
Low side switches	IPW65R125C
Driver ICs	1EDI20N12AF
Primary magnetizing inductance	100 μH
Inductor core	55439A2
Inductor Turns	30/45
Output capacitor	2.2 μF

. The tapped inductor was designed according to the design guide provided by Magnetics-Inc [31], including the magnetic core, the turns, and the wire. A dSPACE system was used to implement the control for the quick experimental study of the SSBBI.

Experimental results are shown in Figure 11 and Figure 12. Figure 11 presents the gate-driving signals for switches at the line period scale and at the switching period scale, respectively. The output voltage and the switch voltage are shown in Figure 12. Observations in Figure 12 clearly indicate that the output voltage was sinusoidal. The THD of the experimental output voltage was around 5% with the open-loop control. This verified that the experimental SSBBI prototype operated according to the theoretical expectations. That is, the proposed SSBBI can achieve the inversion and produce a high-quality sinusoidal output.

In addition, as shown in Figure 12, when zooming into the switch voltage waveform, it was revealed that a voltage spike appeared at the instant of the switch turning off. This is typical for converters with coupled inductors [32]. For the first version of the prototype, a simple RCD snubber was used to verify the basic operation principle of the proposed topologies. The efficiency of 75% was achieved with 100-W output power, where the RCD snubber accounted for a large portion of the total power losses. Moreover, the voltage spike can be suppressed with an appropriate snubber arrangement and design to capture and recycle the leakage energy to achieve much higher efficiency according to the analysis. Snubber details and verification are the subjects of the follow-up research work. What is more, the voltage gain was slightly lower than the theoretical one due to the power losses. With the planned regenerative snubber, the power losses will be less and, thus, the practical voltage gain should be closer to the theoretical one. Overall, the simulation and experimental results were in agreement with the theoretical analysis. Thus, the effectiveness of the proposed inverter family was verified, which had the merits of single-stage conversion, low component count, and easy implementation. These advantages are significant from PV applications, while the efficiency should be further enhanced.

6.2. Comparison of the SSBBI and the State of the Art

After the preliminary experimental test of the SSBBI prototype, the non-optimized performance of the SSBBI could be compared with its counterparts. The comparison results are shown in

Table 10. Comparison of the SSBBI with the state of the art.

Topologies	Switches Count	Diodes Count	Inductors Count	Input Voltage	Output Voltage	Output Power	Efficiency
[22]	4	8	4	20 V	314 V	100 W	/
[23]	8	0	1 Tapped	100–200 V	110 V	500 W	>96%
Figure 2b [24]	8	0	1 Tapped	40 V	230 V	/	/
[25]	5	2	1 Tapped	60 V	230 V	100 W	86%
SSBBI	4	0	1 Tapped	48 V	110 V	100 W	75%

. According to Table 10, it is known that the SSBBI had the lowest semiconductor count, almost half of its counterparts. The lower component count makes the SSBBI a simple structure, requiring simpler driving and auxiliary power supplies. These advantages will lead to lower cost, which is a practical concern for the microinverters.

The efficiency performance of the SSBBI was not outperforming, as mentioned previously. With the theoretical analysis and simulations, the power losses on the RCD snubber were around 15%. Thus, with a proper regenerative snubber, the efficiency will be more than 85% as predicted, where component optimization can further be applied to improve the efficiency. Nevertheless, the efficiency of 85% will be reasonable for a 100-W, single-stage, buck-boost inverter and comparable with the experimental efficiency in [25].

7. Conclusions

This paper introduced a family of single-stage, buck-boost inverter topologies. Compared to the counterparts, the proposed topologies had a lower component count. The key feature of the proposed family was the application of a multi-winding tapped inductor that helped to attain a higher voltage gain required in PV applications, as microinverters. The operational principle was discussed in this paper, which was supported by simulation and experimental results. A stand-alone experimental SSBBI prototype was designed, built, and tested. Experimental results showed that the proposed topology is capable of delivering a well-shaped sinusoidal output. However, the practical voltage gain was slightly lower than theoretical prediction and the efficiency was not at a very satisfactory level due to the RCD snubber losses and the un-optimized components of the converter, which will be the future work. Overall, the proposed family can present a viable solution to single-stage microinverter applications.