Improvement in Voltage Gain of Interleaved High Step-Down Converter

Abstract

An interleaved high step-down converter is presented herein, which utilized a diode-capacitor module so as to make the step-down voltage gain under the same duty cycle as well as the voltage stresses on switches and diodes relatively low as compared with the existing circuits. Also, under the same voltage gain, the proposed circuit had a relatively large duty cycle, making the elapsed time per cycle for the connection between the input and the output enlarged, and hence the controller was not interrupted by noises. This converter can be used in low-output-power high-output-current applications. In this study, the basic operating principles of the proposed converter were firstly described and analyzed, and finally, its effectiveness was demonstrated by experiment.

1. Introduction

With the fast development of technology, the high step-down converter is widely used in the relatively low output voltage of the power supply feeding batteries and light emitting diode (LED) lamps, among others. If an extremely small duty cycle in the traditional buck converter is needed, it is difficult to control this converter and the accompanying power loss would be increased.

For the step-down converter to be considered, the studies [1,2,3,4,5] present two-stage converters. Such converters can effectively improve the step-down converter ratio. However, these converters need a relatively large number of components, gate driving circuits, and other additional factors. In addition, the efficiency of the two-stage converter is the product of individual efficiencies, thereby making the overall efficiency relatively low.

For the multiple phases to be considered, the converter needs interleaved control. In general, this converter has two or more identical circuits that are paralleled and are then connected to the output load. Each phase has an angle difference angle of $\pm {360}^{\circ }/N$ between the two adjacent phases, if N phases are used. By doing so, the current stresses on components are reduced, the overall efficiency is improved, and the output current ripple is reduced, thus rendering the low output capacitance needed, as well as the output capacitor lifespan enlarged. Recently, many multiphase interleaved high step-down converters have been presented [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The papers [6,7,8] present two-phase interleaved step-down converters based on coupling inductors so as to attain high step-down voltage gains. The papers [8,9,10,11,12] and [15,16,17,18,19,20] present the converters with energy-transferring capacitors so as to achieve high step-down voltage gains and current balance as well as to reduce switch/diode voltage stresses. The paper [13] presents a two-phase interleaved high step-down converter, which is based on the energy-transferring capacitor so as to improve a high step-down voltage gain as well as to reduce switch voltage stresses. Nevertheless, the currents in two phases are not identical. The paper [14] presents a four-phase interleaved synchronously rectified (SR) buck converter to improve the step-down voltage gain. As for the papers [18,19,20], the output voltages were floating due to the switches connected in series with the ground. By doing so, the galvanic isolation between the input and the output is required.

On the basis of the aforementioned papers, the proposed converter was derived from the converter shown in [13], so as to improve the step-down conversion ratio in [13]. As compared with the circuit shown in [13], the proposed circuit had a relatively large duty cycle under the same voltage gain, thereby causing the elapsed time per cycle for the connection between the input and the output to be enlarged, and hence the controller to not be interrupted by noises.

2. Basic Operating Principles

Figure 1 displays the proposed high step-down converter, which is constructed by five switches Q₁, Q₂, Q₃, Q₄, and Q₅; three diodes D₁, D₂,and D₃; three energy-transferring capacitors C₁, C₂, and C₃; two inductors L₁ and L₂; and one output capacitor C_o. Regarding the load, it was built up by one output resistor R_o. It is noted that the diode-capacitor module was composed of D₁, D₂, D₃, C₁, C₂ and C₃, making the voltage gain of the proposed converter lower than that of the converter shown in [13].

Some symbols and definitions are to be given prior to dealing with this section, and are listed below:

(1)

The input voltage is signified by V_in and the output is denoted by V_o.

(2)

The values of the capacitors C₁, C₂, and C₃ are large enough such that the voltages across them can be regarded as some constant values.

(3)

The currents in Q₁, Q₂, Q₃, Q₄, and Q₅ are expressed by i_ds1, i_ds2, i_ds3, i_ds4, and i_ds5, respectively; the currents in C₁, C₂, and C₃ are represented by i_C1, i_C2, and i_C3, respectively; the currents in L₁ and L₂ are indicated by i_L1 and i_L2, respectively; the current i_Lo is the sum of i_L1 and i_L2; the currents in D₁, D₂, and D₃ are signified by i_D1, i_D2, and i_D3, respectively; the current R_o is expressed by I_o.

(4)

The voltages on L₁ and L₂ are denoted by v_L1 and v_L2, respectively; the voltages on C₁, C₂, and C₃ are expressed by V_C1, V_C2, and V_C3, respectively; the voltage across C_o is represented by V_o.

(5)

The switching period and frequency are indicated by T_s and f_s, respectively.

(6)

The gate driving signals for Q₁, Q₂, Q₃, Q₄, and Q₅ are denoted by v_gs1, v_gs2, v_gs3, v_gs4, and v_gs5, respectively. Furthermore, v_gs1 is in phase with v_gs3 but is complimentary to v_gs4, whereas v_gs2 is complimentary to v_gs5 and is shifted by 180^o from v_gs1. In addition, the duty cycle of v_gs1 is D_a, the duty cycle of v_gs2 is D_b and D_a = D_b = D.

(7)

Because the proposed circuit operates in the continuous conduction mode (CCM), there are four operating states over one switching period as shown in Figure 2.

2.1. Basic Operating Principles

2.1.1. State 1: $\left[t_o\le t\le t_1\right]$

As displayed in Figure 3, the switches Q₁, Q₃, and Q₅ are turned on but the switches Q₂ and Q₄ are turned off, whereas the diode D₁ is turned off but the diodes D₂ and D₃ are turned on. During this state, the input voltage V_in minus V_o is across the energy-transferring capacitor C₁ and the inductor L₂, thereby making C₁ charged and L₂ magnetized. At the same time, the energy-transferring capacitors C₂ and C₃ are discharged, and the inductor L₁ is demagnetized due to the voltage across L₁ being –V_o, thus rendering the current i_L1 flow through the switch Q₅.

2.1.2. States 2 and 4: $\left[t_1\le t\le t_2,t_3\le t\le t_o\le T_S\right]$

As displayed in Figure 4, the switches Q₄, and Q₅ are turned on but the switches Q₁, Q₂, and Q₃ are turned off. During this state, the diodes D₁, D₂, and D₃ are turned off. At the same time, the inductors L₁ and L₂ are demagnetized due to the voltages across L₁ and L₂ being −V_o, thereby rendering the currents i_L1 and i_L2 flow through the switches Q₄ and Q₅, respectively.

2.1.3. State 3: $\left[t_2\le t\le t_3\right]$

As displayed in Figure 5, the switches Q₂ and Q₄ are turned on but the switches Q₁, Q₃, and Q₅ are turned off, whereas the diode D₁ is turned on but the diodes D₂ and D₃ are tuned off. During this state, the energy stored in the energy-transferring capacitor C₁ releases energy to the energy-transferring-capacitors C₂ and C₃, the inductor L₁ and the load, thereby making C₂ and C₃ charged and L₁ magnetized. At the same time, the inductor L₂ is still demagnetized, thus making the current i_L2 flow through the switch Q₄. It is noted that the diode-capacitor module is composed of D₁, D₂, D₃, C₁, C₂, and C₃.

2.2. Voltage Gain

By applying the voltage-second balance to the inductors L₁ and L₂, the following expressions can be obtained with D_a = D_b = D as

$$(V_{C1}-V_{C2}-V_{C3}-V_o)D=V_o(1-D)$$

(1)

$$(V_{in}-V_{C1}-V_o)D=V_o(1-D)$$

(2)

$$(V_{C2}-V_o)D=V_o(1-D)$$

(3)

$$(V_{C3}-V_o)D=V_o(1-D)$$

(4)

By substituting (3) and (4) into (1), the following expression can be found as

$$V_{C1}D=3V_o$$

(5)

Finally, by substituting (5) into (2), the voltage gain can be obtained as

$$\frac{V_o}{V_{in}}=\frac{D}{4}$$

(6)

2.3. Boundary Conditions of L₁ and L₂

The condition of the boundary conduction mode (BCM) of the inductor L₁ can be described as follows:

$$2I_{L1}=\Delta i_{L1}$$

(7)

where I_L1 and $\Delta i_{L1}$ are the DC and AC values of the current i_L1, respectively.

The condition of the BCM of the inductor L₂ can be described as follows:

$$2I_{L2}=\Delta i_{L2}$$

(8)

where I_L2 and $\Delta i_{L2}$ are the DC and AC values of the current i_L2, respectively.

First of all, let two inductors be the same and three capacitors C₁, C₂, and C₃ be identical. Accordingly, on the basis of the capacitor ampere-second balance of C₁ and from states 1 and 3, the following expression can be obtained:

$$\frac{1}{3}\cdot I_{L2}\cdot D_b\cdot T_s=I_{L1}\cdot D_a\cdot T_s$$

(9)

Since D_a = D_b = D, from (9), the relationship between I_L1 and I_L2 can be obtained as

$$I_{L1}=\frac{1}{3}{I}_{L2}$$

(10)

According to Kirchiff’s current law, the following expression of DC value of i_Lo, called I_Lo, can be obtained as:

$$I_{Lo}=I_{L1}+I_{L2}=I_o$$

(11)

By substituting (10) into (11), the currents I_L1 and I_L2 can be represented as:

$$\{\begin{array}{l}{I}_{L1}=\frac{1}{4}{I}_o\\ I_{L2}=\frac{3}{4}{I}_o\end{array}$$

(12)

Also,

$$I_o=\frac{V_o}{R_o}$$

(13)

Therefore, by substituting (13) into (12), the following equations can be obtained as:

$$\{\begin{array}{l}{I}_{L1}=\frac{V_o}{4R_o}\\ I_{L2}=\frac{3V_o}{4R_o}\end{array}$$

(14)

2.3.1. BCM Curve of L₁

The ripple of the current flowing through the inductor L₁, called $\Delta i_{L1}$, can be expressed by:

$$\Delta i_{L1}=\frac{v_{L1}\Delta t}{L_1}=\frac{V_o(1-D)T_s}{L_1}$$

(15)

Therefore, as $2I_{L1}\ge \Delta i_{L1}$, the inductor L₁ will operate in the CCM, namely,

$$\begin{array}{l}2I_{L1}\ge \Delta i_{L1}\\ \Rightarrow 2\times \frac{V_o}{4R_o}\ge \frac{V_o(1-D)T_s}{L_1}\\ \Rightarrow \frac{L_1}{R_o{T}_s}\ge 2(1-D)\\ \Rightarrow K_1\ge K_{crit1}(D)\end{array}$$

(16)

where $K_1=\frac{L_1}{R_o{T}_s}$ and K_crit1(D) = 2(1 – D).

From (16), if $K_1\ge K_{crit1}(D)$, the inductor L₁ works in the CCM; otherwise, the inductor L₁ works in the DCM. Therefore, the boundary curve between the two modes can be drawn as shown in Figure 6.

2.3.2. BCM Curve of L₂

The ripple of the current flowing through the inductor L₂, called $\Delta i_{L2}$, can be indicated by

$$\Delta i_{L2}=\frac{v_{L2}\Delta t}{L_2}=\frac{V_o(1-D)T_s}{L_2}$$

(17)

Therefore, as $2I_{L2}\ge \Delta i_{L2}$, the current L₂ will operate in the CCM, namely,

$$\begin{array}{l}2I_{L2}\ge \Delta i_{L2}\\ \Rightarrow 2\times \frac{3V_o}{4R_o}\ge \frac{V_o(1-D)T_s}{L_2}\\ \Rightarrow \frac{L_2}{R_o{T}_s}\ge \frac{2}{3}(1-D)\\ \Rightarrow K_2\ge K_{crit2}(D)\end{array}$$

(18)

where $K_2=\frac{L_2}{R_o{T}_s}$ and $K_{crit2}(D)=\frac{2}{3}(1-D)$.

From (18), if $K_2\ge K_{crit2}(D)$, the inductor L₂ works in the CCM; otherwise, the inductor L₂ works in the DCM. Therefore, the boundary curve between the two modes can be plotted as shown in Figure 7.

2.4. Circuit Comparison

In this subsection, the proposed converter is compared with the existing circuits shown in [13,17,19,20] in terms of voltage gain, number of components, voltage stresses on switches and diodes, and floating output. The results are tabulated in

Table 1. Circuit comparison.

Circuit	Voltage Gain	Component Number	Switch Voltage Stress	Diode Voltage Stress	Floating Output
Proposed	$\frac{D}{4}$	14	$V_{ds1}=V_{ds4}=V_{ds5}=\frac{V_{in}}{4}$ $V_{ds2}=V_{ds3}=\frac{3}{4}{V}_{in}$	$V_{D1}=V_{D2}=V_{D3}=\frac{V_{in}}{4}$	No
[20]	$\frac{D}{2}$	9	$V_{ds1}=V_{in}$; $V_{ds4}=\frac{V_{in}}{2}$ $V_{ds2}=V_{ds3}=\frac{V_{in}}{2}$	No	Yes
[13]	$\frac{D}{3}$	10	$V_{ds1}=\frac{V_{in}}{3}$ $V_{ds2}=V_{ds3}=\frac{2}{3}{V}_{in}$ $V_{ds4}=V_{ds5}=\frac{V_{in}}{3}$	No	Yes
[17]	$\frac{D}{4}$	16	$V_{ds1}=\frac{V_{in}}{4}$ $V_{ds2}=V_{ds3}=V_{ds4}=\frac{V_{in}}{2}$	$V_{D1}=V_{D2}=V_{D3}=V_{D4}=\frac{V_{in}}{4}$	No
[19]	$\frac{D}{4}$	17	$V_{ds1}=V_{ds3}=V_{ds4}=\frac{V_{in}}{2}$ $V_{ds2}=\frac{V_{in}}{4}$	$V_{D1}=V_{D2}=V_{D3}=V_{D4}=\frac{V_{in}}{4}$	Yes

.

The proposed circuit has the same voltage gain as the circuits shown in [17,19], it has a lower voltage gain than the circuits shown in [13,20], it has a smaller component count than the circuits in [17,19], and it has a greater component count than the circuits in [13,20]. Furthermore, the proposed circuit and the circuit shown in [17] have no floating output. In addition, the average values of voltage stresses on switches and diodes for the circuits in [13,17,19,20], were 3/8V_in, 5/8V_in, 7/15V_in, and 11/32V_in, respectively. From this, it can be seen that the proposed has a smaller average value than the former two and a larger average value than the last two. In addition, for the proposed converter to be considered, the voltage across L₁ is V_in – V_C1 – V_o during the magnetizing period, whereas the voltage across L₂ is V_C1 – V_C2 – V_C3 during the magnetizing period. For the converter shown in [20] to be considered, the voltages across L₁ and L₂ are both 0.5V_in–V_o during the magnetizing period. Because the values of V_in – V_C1 – V_o and V_C1 – V_C2 – V_C3 are both smaller than 0.5V_in – V_o, the former has a lower voltage gain than the latter.

3. Design Considerations

Table 2. System specifications.

System Parameters	Specifications
Operating mode	CCM
Rated input voltage (Vin)	60 V
Rated output voltage (Vo)	1.8 V
Rated output current (Io,rated)/power (Po,rated)	20 A/36 W
Minimum output current (Io,min)/power (Po,min)	2 A/3.6 W
Switching frequency (fs)/period (Ts)	100 kHz/10 μs

shows the system specifications. On the basis of this table, the associated components are designed.

3.1. Design of Inductors L₁ and L₂

According to Table 1 and (6), the corresponding duty cycle D can be obtained:

$$D=\frac{4V_o}{V_{in}}=\frac{4\times 1.8}{60}=0.12$$

(19)

From (16), if the inductor L₁ works in the CCM, then the value of the inductor L₁ should be satisfied with the following inequality:

$$\begin{array}{l}{L}_1\ge (1-D)\times 2\times R_{o,max}\times T_s\\ \Rightarrow L_1\ge (1-D)\times \frac{2V_o}{I_{o,min}}\times T_s\end{array}$$

(20)

where R_o,max is the load resistance at the minimum load. By substituting the system specifications shown in Table 1 and (19) into (20), the value range of the inductor L₁ can be expressed as

$$\begin{array}{l}{L}_1\ge (1-0.12)\times \frac{2\times 1.8}{2}\times 10 \mathsf{\mu }\\ \Rightarrow L_1\ge 15.84 \mathsf{\mu }\mathrm{H}\end{array}$$

(21)

From (18), if the inductor L₂ works in the CCM, then the value of the inductor L₂ should be satisfied with the following inequality:

$$\begin{array}{l}{L}_2\ge \frac{(1-D)\times 2\times R_{o,max}\times T_s}{3}\\ \Rightarrow L_2\ge \frac{(1-D)\times 2\times V_o\times T_s}{3\times I_{o,min}}\end{array}$$

(22)

By substituting the system specifications shown in Table 1 and (19) into (22), the value range of the inductor L₂ can be expressed as

$$\begin{array}{l}{L}_2\ge \frac{(1-0.12)\times 2\times 1.8\times 10\mathsf{\mu }}{3\times 2}\\ \Rightarrow L_2\ge 5.28 \mathsf{\mu }\mathrm{H}\end{array}$$

(23)

Finally, the values of L₁ and L₂ are identical and equal to 20 µH in order to meet the requirement of I_L2 = 3I_L1.

3.2. Design of Energy-Transferring Capacitors C₁ to C₃

As shown in state 1, the current waveform of the energy-transferring capacitor C₁ is the same as that of the inductor L₁, and hence the corresponding constant values can be expressed by

$$I_{C1,DaTs}=I_{L1,DaTs}=I_{L1}$$

(24)

From (1) to (4) and Table 1, the voltage across C₁, V_C1, can be signified by

$$V_{C1}=\frac{3\times V_o}{D}=\frac{3\times 1.8}{0.12}=45 \mathrm{V}$$

(25)

In addition, by assuming that the voltage ripple of C₁ is 0.1% of V_C1 and by substituting the results from (12), (19), and (25) into (26), the value of C₁ can be obtained as

$$\begin{array}{l}{C}_1\ge \frac{I_{C1,DaTs}\times D_a{T}_s}{0.1\%\times V_{C1}}\\ =\frac{I_{L1}\times D{T}_s}{0.001\times V_{C1}}\\ =\frac{5\times 0.12\times 10\mathsf{\mu }}{0.001\times 45}=133.3\mathsf{\mu }\mathrm{F}\end{array}$$

(26)

As shown in state 3, the current waveforms of the energy-transferring capacitors C₂ and C₃ are the same as that of the inductor L₁, and hence the corresponding constant value can be represented by:

$$I_{C2,DbTs}=I_{C3,DbTs}=I_{L1,DbTs}=I_{L1}$$

(27)

From (1) to (4) and Table 1, the voltages across C₂ and C₃, V_C2 and V_C3, can be obtained as

$$V_{C2}=V_{C3}=\frac{V_o}{D}=\frac{1.8}{0.12}=15\mathrm{V}$$

(28)

In addition, by assuming that the voltage ripples of C₂ and C₃ are both 0.1% of V_C2, and by substituting the results from (12), (19), and (28) into (29), the values of C₂ and C₃ can be obtained as

$$\begin{array}{l}{C}_3=C_2\ge \frac{I_{C2,DbTs}}{0.1\%\times V_{C2}}\times D_a{T}_s=\frac{I_{L1}\times D{T}_s}{0.001\times V_{C2}}\\ =\frac{5\times 0.12\times 10\mathsf{\mu }}{0.001\times 15}=400\mathsf{\mu }\mathrm{F}\end{array}$$

(29)

Finally, in order to meet the assumption for (11), the values of C₁, C₂, and C₃ are all set at 470 µF.

3.3. Design of Output Capacitor C_o

The current flowing through the output capacitor C_o is the sum of the currents i_L1 and i_L2, namely,

$$\begin{array}{l}\Delta i_{Co}(t)=\Delta i_{L1}(t)+\Delta i_{L2}(t)\\ \Rightarrow \Delta i_{Co}(D_a{T}_s)=\Delta i_{L1}(D_a{T}_s)+\Delta i_{L2}(D_a{T}_s)\\ \Rightarrow \Delta i_{Co}(D_a{T}_s)=(\frac{V_{in}-V_{C1}-V_o}{L_1})\times \frac{D}{f_s}+(\frac{-V_o}{L_2})\times \frac{D}{f_s}\end{array}$$

(30)

Because L₁ = L₂ = L, (30) can be rearranged as

$$\Delta i_{Co}=\frac{(1-2D_a)\times V_o}{L\times f_s}$$

(31)

After this, by assuming that the output voltage ripple of C_o is 0.1% of V_o, and by substituting the results from Table 1, (19), and (31) into (32), the value of C_o can be obtained to be

$$\begin{array}{l}{C}_o\ge \frac{\Delta i_{Co,DaTs}}{0.1\%\times V_o}\times D_a{T}_s=\frac{(1-2D)\times V_o\times D{T}_s}{8\times 0.001\times V_o\times L\times f_s}\\ =\frac{(1-2\times 0.12)\times 0.12\times 10\mathsf{\mu }}{8\times 0.001\times 20\mathsf{\mu }\times 100\mathrm{k}}=57\mathsf{\mu }\mathrm{F}\end{array}$$

(32)

Eventually, the value of C_o was chosen as 68 μF. In addition,

Table 3. Component specifications.

Components		Specifications
MOSFET	Q1, Q4, Q5	FDP047AN
	Q2, Q3	FDP047AN
Diode	D1, D2, D3	STPS30L45CT
Energy-transferring Capacitor	C1	47 470 μF/100 V Rubycon Electrolytic Capacitor
	C2, C3	470 μF/35 V Rubycon Electrolytic Capacitor
Capacitor	Co	68 μF/6.3 V Rubycon Electrolytic Capacitor
Inductor		Core CH330125, L1 = L2 = 20 μH
Gate driver		TLP250

lists the component specifications of the proposed converter.

4. System Control Strategy

Figure 8 shows the system configuration of the proposed interleaved high step-down converter, which is composed of the main power circuit and the feedback control circuit. As for the feedback control circuit, the output signal is extracted from the voltage divider. Afterwards, such an analog signal is sent to the analog-to-digital converter (ADC) and then is transferred to the digital signal. This digital signal is sent to the field programmable gate array (FPGA) so as to obtain the corresponding gate control signals. Finally, these control signals are used to drive the corresponding switches after individual gate drivers so as to keep the output voltage constant at some value.

5. Experimental Results

5.1. Measured Waveforms

Figure 9 shows the gate driving signals for the switches Q₁, Q₂, Q₃, Q₄, and Q₅, called v_gs1, v_gs2, v_gs3, v_gs4, and v_gs5, respectively. Figure 10 displays the voltages across Q₁, Q₂, Q₄, and Q₅, called v_ds1, v_ds2, v_ds4, and v_ds5. Figure 11 shows the voltages across Q₁ and Q₃, called v_ds1 and v_ds3. Figure 12 displays the voltages across the energy-transferring capacitors C₁, C₂, and C₃, called V_C1, V_C2, and V_C3, respectively. Figure 13 shows the voltages on the diodes D₁, D₂, and D₃, called V_D1, V_D2, and V_D3, respectively. Figure 14 displays the currents i_L1, i_L2, and i_Lo.

From Figure 9, it can be seen that the gate driving signal sequence met the requirements. From Figure 10 and Figure 11, it can be seen that the voltage stresses on Q₁, Q₄, and Q₅, without voltage spikes considered, were all about 15 V, corresponding to V_in–V_C1, whereas the voltage stresses on Q₂ and Q₃, without voltage spike considered, were about 45 V, corresponding to V_C1. As for voltage spikes on switches during the turn-off period, they came from the resonance between line parasitic inductances and switch body capacitances. From Figure 12, it can be seen that the voltages across C₁, C₂, and C₃ were kept at the values of 45.5 V, 15.5 V, and 15 V, respectively, which were slightly larger than the calculated values shown in Equations (25) and (28) at 45 V, 15 V, and 15 V, respectively. From Figure 13, it can be seen that the voltages across D₁, D₂, and D₃ were three-level and the voltage stresses on these diodes were all about 15 V, corresponding to V_C2. From Figure 14, it can be seen that the current i_Lo was the sum of the currents i_L1 and i_L2, whereas the DC values of i_L1 and i_L2 were about 5 A and 15 A, respectively, satisfying Equation (12).

5.2. Efficiency Measurement

The means of measuring the efficiency is given herein, and the accompanying result follows. As displayed in Figure 15, the input current was attained by measuring the voltage across the current sensing resistor according to the digital meter named Fluke 8050 A. Afterwards, the input voltage was also obtained by the digital meter. Hence, the input power can be obtained. Concerning the output power, the output current was read from the digital load and the output voltage was also attained by the digital meter. Hence, the output power can be obtained. Eventually, the resulting efficiency can be known. Accordingly, Figure 16 displays the curve of efficiency versus load current. From Figure 16, it can be known that the efficiency all over the load range was above 81.4% and the maximum efficiency was 85.1%.

5.3. Power Loss Breakdown Analysis

In the following section, the power loss breakdown analysis, not based on circuit modeling [21,22,23,24,25,26,27,28,29,30] but based on component datasheets, is shown under the condition that the converter operated at a rated load of 36 W.

5.3.1. Power Losses in Switches

The power loss in each switch, called P_Q,loss, can be calculated on the basis of Equation (33).

$$\begin{array}{l}{P}_{Q,loss}=P_{on,cond}+P_{turn-on}+P_{turn-off}\\ ={i^2}_{ds,rms}\cdot R_{on}+(\frac{v_{ds}\cdot i_{ds,max}\cdot t_r\cdot f_s}{6})+(\frac{v_{ds}\cdot i_{ds,max}\cdot t_f\cdot f_s}{6})\end{array}$$

(33)

where P_on,cond indicates the turn-on conduction loss, P_turn-on signifies the switching loss during the turn-on period, P_turn-off represents the switching loss during the turn-off period, R_on indicates the turn-on resistance, t_r signifies the turn-on rising time, and t_f represents the turn-off falling time. According to the FDP047AN datasheet, it can be known that the values of R_on, t_r, and t_f are 4 mΩ, 88 ns, and 45 ns, respectively.

Therefore,

$$P_{Q1,loss}={2.5}^2\cdot 4\cdot {10}^{-3}+(\frac{15\cdot 5.132\cdot 133\cdot {10}^{-9}\cdot 100\mathrm{k}}{6})=0.195 \mathrm{W}$$

(34)

$$P_{Q2,loss}={1.95}^2\cdot 4\cdot {10}^{-3}+(\frac{45\cdot 5.396\cdot 133\cdot {10}^{-9}\cdot 100\mathrm{k}}{6})=0.55 \mathrm{W}$$

(35)

$$P_{Q3,loss}={3.548}^2\cdot 4\cdot {10}^{-3}+(\frac{45\cdot 10.264\cdot 133\cdot {10}^{-9}\cdot 100\mathrm{k}}{6})=1.07 \mathrm{W}$$

(36)

$$P_{Q4,loss}={14.43}^2\cdot 4\cdot {10}^{-3}+(\frac{15\cdot 20.792\cdot 133\cdot {10}^{-9}\cdot 100\mathrm{k}}{6})=1.52 \mathrm{W}$$

(37)

$$P_{Q5,loss}={7.139}^2\cdot 4\cdot {10}^{-3}+(\frac{15\cdot 15.66\cdot 133\cdot {10}^{-9}\cdot 100\mathrm{k}}{6})=0.724 \mathrm{W}$$

(38)

Additionally, the total switch power loss, called P_Q,loss,total, can be obtained from (34) to (38) as

$$\begin{array}{ll}{P}_{Q,loss,total}& =P_{Q1,loss}+P_{Q2,loss}+P_{Q3,loss}+P_{Q4,loss}+P_{Q5,loss}\\ & =0.195+0.55+1.07+1.52+0.724=4.059 \mathrm{W}\end{array}$$

(39)

5.3.2. Power Losses in Diodes

The power loss in each diode, called P_D,loss, can be calculated on the basis of (40).

$$P_{D,loss}=V_F\cdot I_{D,avg}$$

(40)

where V_F signifies the forward bias voltage, and I_D,avg represents the forward current.

$$P_{D1.loss}=0.095\cdot 0.68=0.0646 \mathrm{W}$$

(41)

$$P_{D2.loss}=0.096\cdot 0.505=0.0485 \mathrm{W}$$

(42)

$$P_{D3.loss}=0.097\cdot 0.505=0.0489 \mathrm{W}$$

(43)

In addition, the total diode power loss, called P_D,loss,total, can be obtained from (41) to (43) as

$$\begin{array}{l}{P}_{D,loss,total}=P_{D1,loss}+P_{D2,loss}+P_{D3,loss}\\ =0.0646+0.0485+0.0489=0.162 \mathrm{W}\end{array}$$

(44)

5.3.3. Power Losses in Inductors

The power loss in each inductor, called P_L,loss, can be calculated on the basis of (45).

$$P_{L.loss}=i_{L,rms}^2\cdot R_{DC}$$

(45)

where R_DC signifies the copper resistance.

$$P_{L1,loss}=5^2\cdot 14.7\cdot {10}^{-3}=0.3675\mathrm{W}$$

(46)

$$P_{L2,loss}={15}^2\cdot 10.5\cdot {10}^{-3}=2.3625\mathrm{W}$$

(47)

Additionally, the total inductor power loss, called P_L,loss,total, can be obtained from (46) and (47) as

$$\begin{array}{l}{P}_{L,loss,total}=P_{L1,loss}+P_{L2,loss}\\ =0.3675+2.3625=2.73\mathrm{W}\end{array}$$

(48)

5.3.4. Estimated Efficiency

From Equations (39), (44), and (48), the power losses of components are drawn in Figure 17. In addition, the estimated efficiency was 83.8%, which is higher than the measured efficiency of 81.4%.

6. Conclusions

An interleaved high step-down converter is presented herein. Compared with the related existing circuits [13,20] shown in Table 1, the proposed circuit had a relatively low step-down voltage gain under the same duty cycle, and had relatively low voltage stresses on the switches and diodes, thereby causing the switches with low turn-on resistances and the diodes with low forward bias voltages to be chosen. The main reason was that a diode-capacitor module utilized in the proposed converter can make inductors magnetized with relatively low voltages. Moreover, under the same voltage gain, the proposed circuit had a larger duty cycle than the circuits shown in [13,20], thereby rendering the elapsed time per cycle for the connection between the input and the output enlarged, and hence the controller not interrupted by noises.