Improvement in Voltage Gain of Interleaved High Step-Down Converter

: An interleaved high step-down converter is presented herein, which utilized a diode-capacitor module so as to make the step-down voltage gain under the same duty cycle as well as the voltage stresses on switches and diodes relatively low as compared with the existing circuits. Also, under the same voltage gain, the proposed circuit had a relatively large duty cycle, making the elapsed time per cycle for the connection between the input and the output enlarged, and hence the controller was not interrupted by noises. This converter can be used in low-output-power high-output-current applications. In this study, the basic operating principles of the proposed converter were firstly described and analyzed, and finally, its effectiveness was demonstrated by experiment.


Introduction
With the fast development of technology, the high step-down converter is widely used in the relatively low output voltage of the power supply feeding batteries and light emitting diode (LED) lamps, among others. If an extremely small duty cycle in the traditional buck converter is needed, it is difficult to control this converter and the accompanying power loss would be increased.
For the step-down converter to be considered, the studies [1][2][3][4][5] present two-stage converters. Such converters can effectively improve the step-down converter ratio. However, these converters need a relatively large number of components, gate driving circuits, and other additional factors. In addition, the efficiency of the two-stage converter is the product of individual efficiencies, thereby making the overall efficiency relatively low.
For the multiple phases to be considered, the converter needs interleaved control. In general, this converter has two or more identical circuits that are paralleled and are then connected to the output load. Each phase has an angle difference angle of 360 / N   between the two adjacent phases, if N phases are used. By doing so, the current stresses on components are reduced, the overall efficiency is improved, and the output current ripple is reduced, thus rendering the low output capacitance needed, as well as the output capacitor lifespan enlarged. Recently, many multiphase interleaved high step-down converters have been presented [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The papers [6][7][8] present twophase interleaved step-down converters based on coupling inductors so as to attain high step-down voltage gains. The papers [8][9][10][11][12] and [15][16][17][18][19][20] present the converters with energy-transferring capacitors so as to achieve high step-down voltage gains and current balance as well as to reduce switch/diode voltage stresses. The paper [13] presents a two-phase interleaved high step-down converter, which is based on the energy-transferring capacitor so as to improve a high step-down voltage gain as well as to reduce switch voltage stresses. Nevertheless, the currents in two phases are not identical. The paper [14] presents a four-phase interleaved synchronously rectified (SR) buck converter to improve the step-down voltage gain. As for the papers [18][19][20], the output voltages were floating due to the switches connected in series with the ground. By doing so, the galvanic isolation between the input and the output is required.
On the basis of the aforementioned papers, the proposed converter was derived from the converter shown in [13], so as to improve the step-down conversion ratio in [13]. As compared with the circuit shown in [13], the proposed circuit had a relatively large duty cycle under the same voltage gain, thereby causing the elapsed time per cycle for the connection between the input and the output to be enlarged, and hence the controller to not be interrupted by noises. Figure 1 displays the proposed high step-down converter, which is constructed by five switches Q1, Q2, Q3, Q4, and Q5; three diodes D1, D2,and D3; three energy-transferring capacitors C1, C2, and C3; two inductors L1 and L2; and one output capacitor Co. Regarding the load, it was built up by one output resistor Ro. It is noted that the diode-capacitor module was composed of D1, D2, D3, C1, C2 and C3, making the voltage gain of the proposed converter lower than that of the converter shown in [13]. Some symbols and definitions are to be given prior to dealing with this section, and are listed below:

Basic Operating Principles
(1) The input voltage is signified by Vin and the output is denoted by Vo. As displayed in Figure 3, the switches Q1, Q3, and Q5 are turned on but the switches Q2 and Q4 are turned off, whereas the diode D1 is turned off but the diodes D2 and D3 are turned on. During this state, the input voltage Vin minus Vo is across the energy-transferring capacitor C1 and the inductor L2, thereby making C1 charged and L2 magnetized. At the same time, the energy-transferring capacitors C2 and C3 are discharged, and the inductor L1 is demagnetized due to the voltage across L1 being -Vo, thus rendering the current iL1 flow through the switch Q5.
As displayed in Figure 4, the switches Q4, and Q5 are turned on but the switches Q1, Q2, and Q3 are turned off. During this state, the diodes D1, D2, and D3 are turned off. At the same time, the inductors L1 and L2 are demagnetized due to the voltages across L1 and L2 being −Vo, thereby rendering the currents iL1 and iL2 flow through the switches Q4 and Q5, respectively. As displayed in Figure 5, the switches Q2 and Q4 are turned on but the switches Q1, Q3, and Q5 are turned off, whereas the diode D1 is turned on but the diodes D2 and D3 are tuned off. During this state, the energy stored in the energy-transferring capacitor C1 releases energy to the energytransferring-capacitors C2 and C3, the inductor L1 and the load, thereby making C2 and C3 charged and L1 magnetized. At the same time, the inductor L2 is still demagnetized, thus making the current iL2 flow through the switch Q4. It is noted that the diode-capacitor module is composed of D1, D2, D3, C1, C2, and C3. Figure 5. Current flow of state 3.

Voltage Gain
By applying the voltage-second balance to the inductors L1 and L2, the following expressions can be obtained with Da = Db = D as By substituting (3) and (4) into (1), the following expression can be found as Finally, by substituting (5) into (2), the voltage gain can be obtained as

Boundary Conditions of L1 and L2
The condition of the boundary conduction mode (BCM) of the inductor L1 can be described as follows: are the DC and AC values of the current iL1, respectively.
The condition of the BCM of the inductor L2 can be described as follows: First of all, let two inductors be the same and three capacitors C1, C2, and C3 be identical. Accordingly, on the basis of the capacitor ampere-second balance of C1 and from states 1 and 3, the following expression can be obtained: Since Da = Db = D, from (9), the relationship between IL1 and IL2 can be obtained as According to Kirchiff's current law, the following expression of DC value of iLo, called ILo, can be obtained as: By substituting (10) into (11), the currents IL1 and IL2 can be represented as: Therefore, by substituting (13) into (12), the following equations can be obtained as:

BCM Curve of L1
The ripple of the current flowing through the inductor L1, called 1 L i  , can be expressed by: Therefore, as the inductor L1 will operate in the CCM, namely, , the inductor L1 works in the CCM; otherwise, the inductor L1 works in the DCM. Therefore, the boundary curve between the two modes can be drawn as shown in Figure 6.

BCM Curve of L2
The ripple of the current flowing through the inductor L2, called 2 L i  , can be indicated by Therefore, as , the inductor L2 works in the CCM; otherwise, the inductor L2 works in the DCM. Therefore, the boundary curve between the two modes can be plotted as shown in Figure 7.

Circuit Comparison
In this subsection, the proposed converter is compared with the existing circuits shown in [13,17,19,20] in terms of voltage gain, number of components, voltage stresses on switches and diodes, and floating output. The results are tabulated in Table 1.
The proposed circuit has the same voltage gain as the circuits shown in [17,19], it has a lower voltage gain than the circuits shown in [13,20], it has a smaller component count than the circuits in [17,19], and it has a greater component count than the circuits in [13,20]. Furthermore, the proposed circuit and the circuit shown in [17] have no floating output. In addition, the average values of voltage stresses on switches and diodes for the circuits in [20], [13], [17], and [19], were 3/8Vin, 5/8Vin, 7/15Vin, and 11/32Vin, respectively. From this, it can be seen that the proposed has a smaller average value than the former two and a larger average value than the last two. In addition, for the proposed converter to be considered, the voltage across L1 is Vin -VC1 -Vo during the magnetizing period, whereas the voltage across L2 is VC1 -VC2 -VC3 during the magnetizing period. For the converter shown in [20] to be considered, the voltages across L1 and L2 are both 0.5Vin-Vo during the magnetizing period. Because the values of Vin -VC1 -Vo and VC1 -VC2 -VC3 are both smaller than 0.5Vin -Vo, the former has a lower voltage gain than the latter.  Table 2 shows the system specifications. On the basis of this table, the associated components are designed.

Design of Inductors L1 and L2
According to Table 1 and (6), the corresponding duty cycle D can be obtained: From (16), if the inductor L1 works in the CCM, then the value of the inductor L1 should be satisfied with the following inequality: where Ro,max is the load resistance at the minimum load. By substituting the system specifications shown in Table 1 and (19) into (20), the value range of the inductor L1 can be expressed as From (18), if the inductor L2 works in the CCM, then the value of the inductor L2 should be satisfied with the following inequality: By substituting the system specifications shown in Table 1 and (19) into (22), the value range of the inductor L2 can be expressed as Finally, the values of L1 and L2 are identical and equal to 20 µH in order to meet the requirement of IL2 = 3IL1.

Design of Energy-Transferring Capacitors C1 to C3
As shown in state 1, the current waveform of the energy-transferring capacitor C1 is the same as that of the inductor L1, and hence the corresponding constant values can be expressed by From (1) to (4) and Table 1, the voltage across C1, VC1, can be signified by In addition, by assuming that the voltage ripple of C1 is 0.1% of VC1 and by substituting the results from (12), (19), and (25) into (26), the value of C1 can be obtained as In addition, by assuming that the voltage ripples of C2 and C3 are both 0.1% of VC2, and by substituting the results from (12), (19), and (28) into (29), the values of C2 and C3 can be obtained as Finally, in order to meet the assumption for (11), the values of C1, C2, and C3 are all set at 470 µF.

Design of Output Capacitor Co
The current flowing through the output capacitor Co is the sum of the currents iL1 and iL2, namely, Because L1 = L2 = L, (30) can be rearranged as After this, by assuming that the output voltage ripple of Co is 0.1% of Vo, and by substituting the results from Table 1 Eventually, the value of Co was chosen as 68 µF. In addition, Table 3 lists the component specifications of the proposed converter.  Figure 8 shows the system configuration of the proposed interleaved high step-down converter, which is composed of the main power circuit and the feedback control circuit. As for the feedback control circuit, the output signal is extracted from the voltage divider. Afterwards, such an analog signal is sent to the analog-to-digital converter (ADC) and then is transferred to the digital signal. This digital signal is sent to the field programmable gate array (FPGA) so as to obtain the corresponding gate control signals. Finally, these control signals are used to drive the corresponding switches after individual gate drivers so as to keep the output voltage constant at some value.  Figure 9 shows the gate driving signals for the switches Q1, Q2, Q3, Q4, and Q5, called vgs1, vgs2, vgs3, vgs4, and vgs5, respectively. Figure 10 displays the voltages across Q1, Q2, Q4, and Q5, called vds1, vds2, vds4, and vds5. Figure 11 shows the voltages across Q1 and Q3, called vds1 and vds3. Figure 12 displays the voltages across the energy-transferring capacitors C1, C2, and C3, called VC1, VC2, and VC3, respectively. Figure 13 shows the voltages on the diodes D1, D2, and D3, called VD1, VD2, and VD3, respectively. Figure  14 displays the currents iL1, iL2, and iLo.

Measured Waveforms
From Figure 9, it can be seen that the gate driving signal sequence met the requirements. From Figures 10 and 11, it can be seen that the voltage stresses on Q1, Q4, and Q5, without voltage spikes considered, were all about 15 V, corresponding to Vin-VC1, whereas the voltage stresses on Q2 and Q3, without voltage spike considered, were about 45 V, corresponding to VC1. As for voltage spikes on switches during the turn-off period, they came from the resonance between line parasitic inductances and switch body capacitances. From Figure 12, it can be seen that the voltages across C1, C2, and C3 were kept at the values of 45.5 V, 15.5 V, and 15 V, respectively, which were slightly larger than the calculated values shown in Equations (25) and (28) at 45 V, 15 V, and 15 V, respectively. From Figure  13, it can be seen that the voltages across D1, D2, and D3 were three-level and the voltage stresses on these diodes were all about 15 V, corresponding to VC2. From Figure 14, it can be seen that the current iLo was the sum of the currents iL1 and iL2, whereas the DC values of iL1 and iL2 were about 5 A and 15 A, respectively, satisfying Equation (12).

Efficiency Measurement
The means of measuring the efficiency is given herein, and the accompanying result follows. As displayed in Figure 15, the input current was attained by measuring the voltage across the current sensing resistor according to the digital meter named Fluke 8050 A. Afterwards, the input voltage was also obtained by the digital meter. Hence, the input power can be obtained. Concerning the output power, the output current was read from the digital load and the output voltage was also attained by the digital meter. Hence, the output power can be obtained. Eventually, the resulting efficiency can be known. Accordingly, Figure 16 displays the curve of efficiency versus load current. From Figure 16, it can be known that the efficiency all over the load range was above 81.4% and the maximum efficiency was 85.1%.

Power Losses in Switches
The power loss in each switch, called PQ,loss, can be calculated on the basis of Equation (33).
where Pon,cond indicates the turn-on conduction loss, Pturn-on signifies the switching loss during the turnon period, Pturn-off represents the switching loss during the turn-off period, Ron indicates the turn-on resistance, tr signifies the turn-on rising time, and tf represents the turn-off falling time.

Estimated Efficiency
From Equations (39), (44), and (48), the power losses of components are drawn in Figure 17. In addition, the estimated efficiency was 83.8%, which is higher than the measured efficiency of 81.4%.

Switches
Inductors Diodes Components

Conclusions
An interleaved high step-down converter is presented herein. Compared with the related existing circuits [13,20] shown in Table 1, the proposed circuit had a relatively low step-down voltage gain under the same duty cycle, and had relatively low voltage stresses on the switches and diodes, thereby causing the switches with low turn-on resistances and the diodes with low forward bias voltages to be chosen. The main reason was that a diode-capacitor module utilized in the proposed converter can make inductors magnetized with relatively low voltages. Moreover, under the same voltage gain, the proposed circuit had a larger duty cycle than the circuits shown in [13,20], thereby rendering the elapsed time per cycle for the connection between the input and the output enlarged, and hence the controller not interrupted by noises.