Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

Abstract

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (V_{GS, OFF}). We have investigated drain channel current (I_{DS, Max}) collapse/degradation and turn-on and rise-time (t_R) delay, on-state resistance (R_DS-ON) and maximum transconductance (G_{m, max}) degradation and threshold voltage (V_TH) shift for pulsed and prolonged off-state gate bias stress V_{GS, OFF}. We have found that as stress voltage magnitude and stress duration increases, similarly I_{DS, Max} and R_DS-ON degradation, V_TH shift and turn-on/rise time (t_R) delay, and G_{m, max} degradation increases. In a pulsed off-state V_{GS, OFF} stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, V_TH shift, I_DS collapse, R_DS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent V_TH shift and high I_{DS, Max} and R_DS-ON degradation in pulsed V_{GS, Stress} and increased rise-time and turn-on delay. In addition to this, a positive V_TH shift and G_{m, max} degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

1. Introduction

Gallium Nitride (GaN) power devices play a vital role in power conversion applications [1,2,3], achieving extraordinary capabilities in photonics and semiconductor technology. In recent decades, GaN high-electron-mobility-transistors (HEMTs) have shown high performance under high temperature (up to 200 °C) [4,5], high breakdown voltage (>650 V) [2,3] and high frequency (>1 MHz) [6,7] operating conditions. Based on these qualities, GaN-HEMT becomes an alternative and competitive candidate to silicon for future semiconductor technology [8]. In the case of switching applications, the gate channel of GaN HEMT with a metal-insulator-semiconductor (MIS-HEMT) structure, which shown in Figure 1a, provides an enlarged gate swing. Due to the addition of a gate insulator, it becomes very effective towards suppressing the gate leakage current (I_{GS, Off}), thus improving long-term reliability compared to its conventional equivalent [9,10]. From these advantages, GaN HEMTs with MIS structure are used in a wide range of applications like electric vehicles, hybrid electric vehicles, and photovoltaic devices [11,12,13].

Normally in switching applications, enhancement mode (E-mode) switches need highly accurate control to get narrow gate swing regarding spikes [14,15] while commonly available gate drivers are very difficult to provide the required negative drive voltage on depletion mode (D-mode) devices [16,17]. To avoid the deficiencies of the above approaches in GaN power switches, cascode power switch configurations were developed, which combines high voltage (HV) D-mode GaN MIS-HEMT connected in series with a low voltage (LV) Si-MOSFET device [18,19], as shown in Figure 1b. GaN cascode configuration achieved a high quality in terms of high breakdown voltage (1200 V), high thermal performance and extended gate drive safety margin (10 V). On the other hand, it also achieved higher reliability qualities, such as maximum transient protection (800 V) and extended JEDEC, AEC-Q101 qualifications, than the commercialized E-mode GaN. In this hybrid cascode configuration, D-mode devices can act like E-mode devices, thus achieving maximum acceptability and applicability. The on-state and off-state of the HV D-mode GaN MIS-HEMT device are controlled using LV Si-MOSFET, which makes the cascode power switch compatible with Si gate-drivers and provides a sufficient safety driving margin for the HV D-mode GaN switch. The body diode in the cascode configuration plays a role in reduced power consumption and support for peripheral components. This cascode configuration offers an extended operating voltage for HV GaN HEMT power systems. However, the GaN power switches dynamic switching problems and static reliability problems still present limitations to the market penetration for advanced GaN in semiconductor technology.

Gate lag (Pulsed Off-State Gate Bias Stress) is the phenomenon in which the drain current shows slow transients for abrupt change in gate voltage and causes a serious problem for analog and digital III-V field effect transistors as results [20,21]. The device’s main parameters, such as I_DS, R_DS-ON, V_TH, and RF power variation and degradation, are observed with respect to the short duty cycle of off-state V_GS bias stress. Several gate-lag effects have been reported in GaN based FET and correlated to current-collapse problems reducing RF power performance of the devices [22,23,24]. These gate-lag effects are caused by surface state generation at the ungated region of the device and held responsible for observed phenomena. During the off-state pulsed V_GS bias stress, the leaking electrons from the gate metal are trapped or detrapped by the surface states and are concerned as far as the mechanism behind surface states charging or discharging. These traps act like “virtual gates”, which are responsible for carrier capture and capture emission phenomena from traps with time leading towards delay of rise-time (t_R) and degradation of drain current during switching conditions [25,26]. Off-state gate pulse-induced surface states trap the region modulated in the density of negatively charged traps with an increase in the magnitude of gate bias stress and evolution of stress time.

Negative bias instability has been found as a critical reliability issue in power transistors, such as MOSFETs, which are made of many material systems, such as Si, SiC, and particularly with GaN. Under reverse gate bias stress, positive charge can be trapped at interface-states in near-interface defects, which are border traps [27]. These trapped charges play a role on the negative threshold voltage (V_TH) shift and also degrade channel carrier mobility [28,29]. A similar observation was reported in SiC MOSFETs, where a partially recoverable decrease in lifetime and increase in interface state density took place after reverse gate bias stress [30]. Based on previous studies on GaN power devices, under negative gate bias stress, the GaN HEMT and MIS-HEMT showed a significant negative V_TH shift, which is a typical behavior with other material systems, and for enhancement-mode GaN MOSFETs, a positive V_TH shift was observed [31]. These observations suggests that the electron trapping in the GaN region results in a positive V_TH shift. Moreover, compared to other GaN power devices, the recent understanding of prolonged off-state gate bias stress effects on the GaN based cascode power switch is very limited. This is mainly due to the configuration structure and multi-layered gate stack with multiple interfaces, which presents more chances for its electron tapping effects. A wider study is needed to provide a solid understanding of the mechanism behind negative gate bias stress in GaN cascode technology.

This paper contributes an understanding of the surface and oxide related trapping processes in GaN cascode power switches during off-state V_GS bias stress. The results of trapping processes described below indicate that: (i) in pulsed off-state bias the surface trapping may constitute a relevant parasitic mechanism that continuously limits dynamic performance of the switch; (ii) in prolonged off-state gate stress bias, the oxide-related trapping and interface state generation may constitute a relevant threshold voltage (V_TH) shift, transconductance (G_{m, max}) degradation, and rise-time (t_R) delay increase, with increasing stress voltage magnitude and stress time evolution at room temperature. The major issue in the presence of electronic traps in the GaN power switch structure limits performance continuously.

2. Experimental Details

This paper contains the study of dynamic instability and static reliability that has been carried out on a commercialized 650 V breakdown voltage and 130 mΩ maximum on-state resistance GaN MIS-HEMT-based cascode power switch from a manufacturer. Initially have investigated the electrical characteristics, such as I_DS-V_DS and I_DS-V_GS of a virgin GaN cascode power switch before pulsed and prolonged off-state gate bias stress measurements, which are shown in Figure 2. From virgin I_DS-V_GS characteristics, main device parameters of threshold voltage V_TH = 2.6 V (defined at I_DS = 1 A/mm), on-state resistance (R_DS-ON) (defined at maximum drain saturation current I_{DS, Max} at V_DS = 5 V), and maximum transconductance (G_{m, max}) were confirmed with the data sheet before off-state gate bias experiments. Further GaN cascode switches were subjected to an extensive trapping-effect analysis based on pulsed and prolonged off-state V_{GS, OFF} bias at room temperature. All these experiments were carried out in a Keithley 2651A and 2601A Source meter system at room temperature.

In the pulsed off-state gate bias stress (Gate-Lag), we characterized the impact of negative gate bias (V_{GS, OFF}) pulsed stress on device behavior through the device parameter stability. A double pulse technique was used in the pulsed off-state stress experiment [32,33,34,35]. The device’s main parameters, threshold voltage (V_TH) instability, maximum drain channel current (I_{DS, Max}) collapse, and on-state resistance (R_DS-ON) degradation were studied during pulsed V_{GS, OFF} stress through two regimes. The impact of low/mid V_{GS, OFF} pulse stress on the performance of the GaN cascode were observed in the first regime, where the device pulsed with V_GS,OFF = −5 to −20 V and V_DS = 0 to 5 V at room temperature. Similarly, in the second regime, the device with high-stress voltages of V_{GS, OFF} pulse = −25 to −40 V. During V_{GS, OFF} pulsed stress, the dynamic instabilities with an electron trapping effect on the device were monitored through I_{DS, Max} collapse and R_DS-ON degradation, V_TH shift and turn-on or rise-time (t_R) delay. At each pulse of V_{GS, OFF} stress, the GaN cascode device was stressed for 300 μs and the on-state pulse was 300 ms. Figure 3 shows the flow chart and stress waveform schematic of the pulsed off-state gate (V_{GS, OFF}) stress bias experiment.

In the prolonged gate stress bias experiment, we characterized the negative bias instability on the GaN cascode device at room temperature through the device parameters instability at the linear operating region (V_DS = 5 V). More specifically, we studied the stability of the threshold voltage (V_TH), which is defined at I_DS = 1 A and maximum transconductance (G_{m, max}). The prolonged V_{GS, OFF} stress phases include a series of stress segments of increasing V_{GS, OFF} and time evolution of stress t_stress. When the device is subjected into V_{GS, OFF} stress, both source and drain channels are grounded with V_DS = 0 V. Based on the pulsed off-state gate stress bias results, the GaN cascode device is subjected to prolonged off-state gate bias stress experiments with selected high-stress voltages of V_{GS, OFF} = −30 to −40 V. For each V_{GS, OFF} bias stress experiment, different GaN cascode devices are used in this study. In this experiment also, the device is initially subjected to virgin I_DS-V_GS characterization with V_DS = 5 V before V_{GS, OFF} stress. Further, the device has been subjected to high-stress voltages for 5000 s, and during the stress experiment, I_DS-V_GS characteristics are observed every 1000 s interval. The device threshold voltage (V_TH) shift and transconductance (G_{m, max}) degradation were observed during the stress phase and after the stress experiment. The prolonged off-state gate bias experimental flow chart is shown in Figure 4.

3. Results and Discussion

3.1. Pulsed Negative Gate Bias Stress (Gate Lag)

Our study shows behaviors on two regimes of I_{DS, Max} degradation, turn-on delay (t_R), negative V_TH shift, and R_DS-ON degradation for the GaN cascode under pulsed off-state gate stress bias experiment. We have applied a pulsed negative V_{GS, OFF} starting from two different quiescent bias points: V_{GS, OFF} bias = 0 V and V_DS = 5 V, which are virgin characteristics and V_{GS, OFF} bias = −5, −10, −15, up to, −40 V with V_DS = 5 V, which can induce measurable trapping processes on the GaN cascode switch. In the first regime, under low/mid V_{GS, OFF} pulsed bias stress, the device has minimal I_{DS, Max} collapse, a negligible turn-on delay to reach the max drain output, recoverable ΔV_TH shift, and ΔR_DS-ON, which is shown in Figure 5. The ΔV_TH and ΔR_DS-ON are normalized V_TH and R_DS-ON, which are defined with fresh and stressed values (R_DS-ON stress/R_DS-ON fresh). In the second regime, the device exposing results of increased I_{DS, Max} degradation, permanent negative ΔV_TH shift, high ΔR_DS-ON degradation, and increased turn-on delay of device under high V_{GS, OFF} stress is shown in Figure 6.

In this pulsed V_{GS, OFF} bias stress experiment, as the evolution stress pulse width and magnitude of stress voltage increases, the V_TH instability and R_DS-ON degradation of the device also continuously increases for relevant trapping effects on the device. Figure 5a shows the device I_DS-V_GS characteristics over low/mid V_{GS, OFF} pulsed stress voltages at low temperature (room temperature). From Figure 5a during low/mid V_{GS, OFF} pulsed stress, the ΔV_TH shift and ΔR_DS-ON degradation of the device were extracted, which is shown in Figure 5b. The negative ΔV_TH shift for low/mid V_{GS, OFF} stress is very minimal and negligible. Under low-stress, a recoverable I_{DS, Max} collapse and ΔR_DS-ON degradation is observed, which is shown in Figure 5a,b. As the V_{GS, OFF} pulsed stress increases to −20 V, I_{DS, max} degradation increases along with turn-on delay to reach the drain saturation current, which indicates the generation of surface traps at the ungated access region [36]. As V_{GS, OFF} stress has a higher increase at room temperature, the I_{DS, Max} degradation further increases, which is shown in Figure 6a. The strong reduction in the drain saturation current I_{DS, Max} is observed due to the generation of surface state traps. The I_{DS, Max} defined at V_DS = 5 V and V_GS = 10 V changes from 44.5 to 30.5 A, and this is attributed to the reduction of the conduction channel, which is caused by the generation surface straps under V_{GS, OFF} pulsed stress. Eventually, ΔR_DS-ON degradation also increases along with I_{DS, Max} degradation for high V_{GS, OFF} pulsed stress. On the other hand, as we increase the V_{GS, OFF} pulsed stress voltages, the negative ΔV_TH shift also increases. Figure 6b is an example of this transition with V_{GS, OFF} pulses (−25, −30, −35, and −40 V). This high increase in a negative ΔV_TH shift is consistent with electron detrapping from preexisting oxide traps [36,37].

Figure 7a shows the I_DS versus time (t) measured from the GaN cascode device in response to the V_{GS, OFF} pulses featuring various V_{GS, OFF} values. Gate lag is asymmetrical, it delays the turn-on transient, leaving the turn-off one almost unaffected. Moreover, the gate lag effects of turn-on delay to reach the maximum drain saturation current are significant in the GaN cascode device. The delay in reaching the I_{DS, Max} of the device has no changes for low/mid stress voltages. As the V_{GS, OFF} pulse value increases, the turn-on delay also increases, which is shown in Figure 7a. The maximum gate lag effect is observed at V_{GS, OFF} = −40 V and is shown in Figure 7a. These gate-lag effects, shown in Figure 7a, by the GaN cascode device originated by the generation of surface traps at the ungated access region. From this observation, the gate-lag transient composed by a fast change in drain current I_DS takes place immediately after the application of the V_GS turn-on step, followed by a delayed increase of I_DS. Both fast and slow components depend on V_{GS, OFF} and V_DS values. Figure 7b shows a negative V_TH shift and also the rise-time t_R delay for the GaN cascode device after the V_{GS, OFF} experiment with V_{GS, OFF} pulse stress = −40 V and V_DS = 5 V. By increasing V_DS for V_{GS, OFF} pulse, gate lag effects are strongly attenuated with increasing magnitude of turn-on delay and rise-time delay.

These observations suggest that the generation of field-induced surface traps at the ungated access region between gate and drain sides and electron detrapping effects from preexisting oxide traps induces the I_{DS, Max} and ΔR_DS-ON degradation [38,39,40], turn-on and rise-time delay, and negative ΔV_TH shift [29,30], which is shown in Figure 5, Figure 6 and Figure 7. The generation of ungated surface-state traps between the gate and source/drain contacts act as “virtual gates”, modulating the underlying depletion region through changes in the density of negatively charged traps. When the off-state gate bias is changed abruptly, these virtual gates respond with the time characteristics of carrier capture/emission phenomena, thus leading to I_DS and ΔR_DS-ON degradation and delayed switching performance. The charging/discharging from surface-state traps with off-state gate pulsed bias stress is concerned as the mechanism behind the device performance degradation. Under off-state gate V_{GS, OFF} pulsed bias stress, the electron detrapping effects from the preexisting oxide traps play a role on the negative V_TH shift. Figure 9 shows that the schematic diagram of the device illustrates possible surface state electron trapping between the drain and gate channel at the ungated region and electron detrapping effects from oxide traps/trapping under the gate channel.

3.2. Prolonged Off-State Gate Bias Stress

Our study focused on selected high V_{GS, OFF} stress voltages based on pulsed (V_{GS, OFF}) stress results. In prolonged off-state gate V_{GS, OFF} bias stress, we show instability and degradation behaviors of threshold voltage V_TH, maximum transconductance (G_{m, max}), and rise-time (t_R) delay for the GaN cascode power switch. As the device was subjected into off-state gate stress, V_{GS, OFF} = −30, −35, and −40 V for 5000 s at low temperature (room temperature). The progression of device instability and degradation of V_TH and G_{m, max} behaviors with time evolution under V_{GS, OFF} is shown in Figure 8a. In the course of the same experiment, the rise-time t_R delay effect increases over the time evolution of stress under V_{GS, OFF} stress = −40 V, which is shown in Figure 8b. At the end of the experiment, after adding V_{GS, OFF} stress, a residual degradation of G_{m, max}, t_R delay and V_TH is left.

From Figure 8a, the device under V_{GS, OFF} stress (−30 V) with short t_stress, the V_TH shift becomes a negative V_TH shift and the G_{m, max} value increases initially. As we increase t_stress and the stress voltage V_{GS, OFF} magnitude increases, the initial negative V_TH shift becomes positive and G_{m, max} starts to degrade, which is also shown in Figure 8a. These V_TH positive shifts and G_{m, max} degradation are enhanced by higher V_{GS, OFF} and increased t_stress. Figure 8b shows the device progression under high V_{GS, OFF} stress (−40 V), a continuous increase in positive V_TH shift and rise-time t_R delay. As we increase t_stress, both positive V_TH shifts and t_R delay increases. This positive V_TH shift is consistent with NBTI studies on GaN MOSFETs. This suggests the appearance of a temporary charge buildup around the threshold voltage after stress.

These observations suggest that a field-induced electron trapping in the GaN channel under both edges of the gate on the source and drain sides [41,42] induces the increase in G_{m, max} and positive V_TH shift. Under high reverse electric field, electrons tunnel from the valence band to GaN channel trap states where electron trapping takes place. In this study, a high electron trapping in the GaN channel might effectively increase the local hole concentration under both edges, which causes a positive V_TH shift as well as a degradation of the maximum transconductance and an increase in the rise-time delay of the GaN cascode power switch. Figure 9 shows the schematic diagram of the device, illustrating possible high electron trapping in the GaN channel under both edges of drain and source sides and interface traps.

4. Conclusions

We identified two different mechanisms that are responsible for different off-state V_{GS, OFF} stress bias experiments in GaN MIS-HEMT based cascode power switches. Theses studies indicate that: (i) in pulsed off-state V_{GS, OFF} bias stress, under low-stress, recoverable electron trapping from an ungated surface region takes place, which degrades the I_{DS, Max} and ΔR_DS-ON, and turn-delay in reaching the maximum drain channel saturation current, are very minimal. As V_{GS, OFF} pulsed stress increases, the electron detrapping from preexisting oxide traps close to the GaN interface also takes place with surface trapping effects, which shifts ΔV_TH negative and increases the ΔR_DS-ON degradation and turn-on delay of the device. At the end of the pulsed off-state experiment, a permanent negative V_TH shift and increased rise-time were observed. (ii) In prolonged off-state V_{GS, OFF} stress bias, an additional transient positive V_TH shift is observed that is accompanied by a degradation in G_{m, max} and an increase in rise-time. This appears to be caused by electron trapping under both gate edges of the GaN channel. In the presence of electron traps in the GaN cascode power switch, such as surface traps, oxide traps, and interface traps, the device continuously limits the performance and stability. These studies give an understanding of the more complex dynamic instability and static reliability issues of GaN MIS-HEMTs-based Cascode devices.