Parametric Compact Thermal Models of Power LEDs

Abstract

Light-emitting diodes are nowadays the most dynamically developing type of light sources. Considering that temperature is the main factor affecting the electrical and lighting parameters of these devices, thermal models are essential subcomponents of the multidomain models commonly used for simulation of their operation. The authors investigated white power light-emitting diodes soldered to Metal Core Printed Circuit Boards (MCPCBs). The tested devices were placed in a light-tight box on a cold plate and their cooling curves were registered for different diode heating current values and various preset cold plate temperatures. These data allowed the computation of optical and real heating power values and consequently the generation of compact thermal models in the form of Foster and Cauer RC ladders. This also rendered possible the analysis of the influence of the considered factors on the compact model element values and their parametrization. The resulting models yield accurate values of diode junction temperature in most realistic operating conditions and they can be easily included in multidomain compact models of power light emitting diodes.

1. Introduction

Power light emitting diodes are nowadays rapidly replacing traditional incandescent bulbs and they are ever more and more frequently being used in numerous lighting applications [1]. From the consumer point of view, the most important parameter describing the performance of LEDs is the emitted optical power. However, its value is a function of many different factors, such as the device operating point or the cooling conditions [2,3,4]. Thus, the analysis of LED operation involves various coupled phenomena of different nature: electrical, optical and thermal. Especially important for the operation of these devices is temperature, which affects all other physical domains. Consequently, the thermal management of LED applications is currently the objective of extensive research [5].

For these reasons, thermal simulations of either individual devices or their luminaries together with cooling assemblies are always carried out during the design phase. These simulations could be performed using software based on some numerical method, such as the finite element one [6,7,8]. Unfortunately, numerical methods require the knowledge of exact structure geometry and material thermal properties, which might not be readily available. Additional problems poses the complexity of structure discretization mesh which could render the simulation time unacceptably long [9].

Thus, when the knowledge of detailed temperature field distribution in space is not required and the main goal of simulations is the determination of device junction temperature, an attractive alternative to detailed 3D thermal models are Compact Thermal Models (CTMs), which typically consist of a very limited number of thermal resistors and capacitors, yet they provide satisfactory simulation accuracy. An additional advantage of CTMs is that, using the electro-thermal analogy, they render possible the execution of multidomain simulations in some ordinary SPICE-like circuit simulators [10,11,12]. Obviously, a standardized form of CTMs are the DELPHI style ones, which are boundary condition independent and do not disclose any proprietary information, but again the data necessary to generate them can be provided only by device manufacturers [13,14].

Another form of CTMs are the RC ladder models which can be obtained directly from system dynamic thermal responses using different model order reduction methods [15,16]. Unfortunately, compared to the DELPHI style models, the ladder ones are not boundary condition independent and they can be employed only in a specific LED operating point and cooling conditions. Hence, the main goal of the research presented in this paper was to develop a methodology for the generation of parametrized ladder models, which could be applied in a wide range of LED operating and cooling conditions. Such thermal networks might be included then in more complex compact multidomain models taking into account also mutual dependencies between multiple LEDs contained in a single luminaire or those capable of determining the heating and optical power for a given operating point and cooling conditions [5,17,18,19]. However, the research on the development of such models for LEDs is still ongoing, e.g. in the frames of the Delphi4LED European project [20].

The following section presents the experimental setup as well as the results of device thermal and optical measurements which allowed the determination of the optical and real heating power. Then, the computed spectra of thermal time constants for the recorded cooling curves are analyzed in order to generate device CTMs in the form of Cauer ladders. Next, parametric expressions for the computation of model element values are proposed. Finally, the cooling curves simulated with these models are compared with the measured ones.

2. Measurement Results

2.1. Measurement Equipment and Experimental Setup

The devices investigated in this paper were commercially available white power LEDs from the XLamp^® XP-L family manufactured by the Cree Company (Durham, North Carolina, USA). The diodes were soldered to the MCPCBs made of an aluminum alloy having the dimensions of 2.5 cm × 2.5 cm × 0.2 cm and pictured in Figure 1a. During all measurements the substrates were attached with the application of thermal grease to the 10.0 cm × 8.0 cm × 1.8 cm copper cold plate through which continuous water flow was forced as shown in Figure 1b. The temperature values of the cold plate and the MCPCB were measured by thermocouples whose locations are indicated in the figure. Based on the temperature values provided by the thermocouples the water temperature was automatically adjusted to maintain the preset cold plate temperature. The LED, which is lit-on in the figure, was positioned on the cold plate at the bottom of the box exactly in its middle.

Initially, the investigated LEDs were calibrated on a cold plate for the forward current of 10 mA. The measured voltage drop across the diode junction decreased linearly with temperature at the rate of –1.34 mV/K. During the actual measurements, first the diode was heated with a preset current value until the thermal steady state was reached. Then, the power was switched off and the device cooling curves were measured by forcing the constant current value for which the diodes were previously calibrated. Each time the heating and cooling phases lasted 30 s. All measurements were taken with the thermal transient tester T3Ster^®, manufactured by Mentor Graphics (Wilsonville, OR USA), which renders possible the recording of thermal responses with a microsecond resolution. Besides, this equipment provides also an entire range of software thermal analysis tools used extensively later on in this paper.

The electrical power supplied to LED terminals is the sum of the emitted optical radiant power and the real heating power. The ratio of the optical power to the electrical one, expressed in percent, is known as the radiant efficiency. Consequently, the measurement of the optical power is required in order to carry out any thermal analysis because it allows also the determination of the real heating power, which should be used as an input quantity for an LED thermal model [21].

The JEDEC standard recommends that the value of this power should be found by performing the measurements of the total emitted radiant flux in an integrating sphere [22]. However, in this paper the optical power was computed based on the irradiance value measured with the Delta OHM HD2302 photoradiometer (Caselle di Selvazzano, Italy), which was placed in the lid of the light-tight box directly over the diode at the distance of 17 cm. This distance, which is 50 times greater than the size of the LED, is large enough so as to consider the diode as a point light source for geometrical analyses. Then, the optical power emitted by the diode was evaluated, as outlined in [23], using the radiation spatial distribution chart provided in the datasheet by the LED manufacturer.

2.2. Results of Electrical Measurements

The diode thermal responses were recorded for 8 different forward current values ranging from 0.1 A to 2.0 A and 9 preset cold plate temperature varying between 10ºC and 90ºC with the step of 10ºC. Each time the measurements were repeated with the LED thermal pad not soldered and then again with the pad properly soldered. This procedure is similar to the dual interface measurement method suggested for the identification of the junction-to-case thermal resistance in the JEDEC standard [24]. Altogether, 144 diode cooling curves were measured. Selected measurement results, shown in Figure 2, are represented as the diode heating curves, which were obtained by subtracting the measured values from the respective steady state values.

This approach is correct if material thermal properties can be considered temperature independent, what was justified here taking into account that the junction temperature rise values were relatively small because of the forced water cooling. Figure 2 presents the curves recorded for the LED heating current of 1.5 A and the cold plate temperature maintained at 10 °C and 90 °C, whereas Figure 2b shows the curves registered for the current values of 0.7 A and 1.5 A when the cold plate temperature was maintained at 50 °C. The black lines represent the measurement results obtained with the thermal pad soldered (WTP) and the lighter ones when the thermal pad was not soldered (NTP). The double lines refer either to lower current or temperature values. The curves, as can be seen in the charts, are only moderately affected by the cold plate temperature and the junction steady state temperature rise value increases with temperature by less than 10%. On the other hand, the soldering of the thermal pad reduces effectively the temperature rise value by approximately 40%, but any effect is visible only after some 0.5 s.

2.3. Optical Measurements

The optical (P_o) and real heating (P_h) power values as well as the radiant efficiency computed for the two limit temperature values using the earlier described methodology are shown in Figure 3. The optical power is plotted in Figure 3a using the solid lines, whereas the dashed ones represent the heating power. Similarly as previously, the cases when the thermal pad is not soldered are denoted by the double lines. The heating power, as can be seen, is fairly independent from temperature, but its value increases rapidly for high current values, reaching even 2 W. On the other hand, the increase of the optical power is less important for high diode currents and its value is visibly affected both by the cold plate temperature and the device soldering manner. For the heating current of 2.0 A, the optical power is reduced by 15% because of the higher cold temperature and another 10% when the thermal pad is not soldered. Therefore, the radiant efficiency curves plotted in Figure 3b have their distinct maxima, which correspond to the LED forward current values ranging from 40 mA to 120 mA. Both the proper soldering of the thermal pad and the increase of cold plate temperature shift the maxima towards higher current values and reduce the efficiency.

3. Thermal Modeling and Simulations

3.1. Time Constant Spectra

The measurements of the optical power emitted by the investigated device, as stated previously, allowed the computation of the heating power and the application of the Network Identification by Deconvolution (NID) thermal analysis method. According to this method, the device responses to power step excitations, sampled at time instants equidistant on the logarithmic time scale, are numerically differentiated and then the frequency spectra of thermal time constants contained in the responses can be computed by performing the numerical deconvolution [25]. The spectra obtained for the previously presented heating curves using the software implementing the NID method and provided together with the thermal tester are shown in Figure 4.

According to the theory, the minima in the spectra indicate the locations where heat diffuses into another material. Here, there are two distinct minima located around 30 ms and 3 s, which are marked in the charts by arrows. These minima, as discussed in [26], correspond to the time instants when heat diffuses from the LED package to the MCPCB and then to the cold plate. Consequently, the thermal resistance of the leftmost section characterizes the heat flow from the junction through the package. The middle part of the spectra corresponds to the interface with the MCPCB. Therefore, leaving the thermal pad unsoldered visibly increases the magnitude of these peaks and shifts them to the right, hence delaying thermal responses. Finally, the rightmost tiny peaks reflect the heat exchange with the cold plate.

3.2. Compact Thermal Models

The division of the time constant spectra into individual sections in the locations of the minima indicated in Figure 4 leads directly to the three-stage compact models in the form of the Foster RC ladder, pictured in Figure 5a. In this circuit the real heating power dissipated in the junction (the current source) flows through three consecutive RC stages towards the ambient (the thermal ground). The time constants of these three stages are equal to the products of the respective thermal resistances and capacitances. The currents represent the heat flow and the voltages correspond to the temperature rise over the ambient.

The division of the spectra directly determined the resistor values of the Foster RC ladder. Then, the thermal time constant values were found employing the built-in Matlab^® Levenberg-Marquardt constrained optimization routine [27]. The optimal time constant values within each of the allowable ranges, delimited by the earlier discussed minima located at some 30 ms and 3 s, were computed by minimizing the error between simulations and measurements. Finally, the thermal capacitor values were found by dividing the respective time constant and resistor values.

Unfortunately, the element values of CTMs in the form of Foster RC ladders cannot have any physical interpretation since capacitors form a direct path from the junction to the ambient. Hence, heat dissipated in the source can be instantaneously sensed as a non-zero heat flux (capacitor current) virtually at any location in this thermal network, thus implying the infinite speed of heat diffusion. A physically correct CTM can be obtained by converting the Foster RC ladder into the mathematically equivalent Cauer RC network shown in Figure 5b. The element values of this model could already have physical interpretation since all the capacitors are connected to the thermal ground. Consequently, heat does not reach remote locations of the network until the thermal capacitors are charged, so the speed of heat diffusion is limited. This conversion can be carried out by executing the continued fraction algorithm, which for a low number of RC components is numerically stable [28].

3.3. Parametric Model

The Cauer RC ladder CTMs generated for different heating current and cold plate temperature values were analyzed so as to identify the influence of these factors on the CTM element values. The results showed that only the resistances R1, R2 and the capacitance C2 vary noticeably, but unlike in the case discussed in [29], they depend only on one of the considered factors at a time. Thus, it was possible to use the following simple parametric formulas to compute model element values:

Y (X) = a × X^b + c,

(1)

where Y is either a resistor or capacitor value and X is a heating current or cold plate temperature value. The values of coefficients a, b, c were determined again using the built-in Matlab^® optimization routines (The MathWorks, Natick, Massachusetts USA).

The final expressions obtained for the computation of the parametrized RC Cauer ladder CTM element values are provided in

Table 1. Element values of the parametrized Cauer CTM for LED with the thermal pad soldered.

Thermal Resistances R (K/W)	Thermal Capacitances C (J/K)
$R1=1.757\times {10}^{-15}·T^{7.321}+3.018$	C1 = 0.00144
$R2=23.3277·I^{-0.0976}-12.9997$	$C2=0.005074·I^{0.6914}+0.01149$
R3 = 0.48	C3 = 14.71

and

Table 2. Element values of the parametrized Cauer CTM for LED with the thermal not connected.

Thermal Resistances R (K/W)	Thermal Capacitances C (J/K)
$R1=1.252\times {10}^{-13}·T^{6.361}+3.239$	C1 = 0.002
$R2=15.12·I^{-0.2534}+3.786$	$C2=0.2071·I^{-0.01749}+0.223$
R3 = 0.95	C3 = 7.07

, separately for each manner of diode soldering considered here. The current should be expressed here in amperes and the temperature in degrees Celsius. Moreover, the variable resistor values computed with the models are plotted in Figure 6 and the variable capacitance in Figure 7a. As can be seen in the tables, it was assumed that the value of resistor R1 depends on temperature and the values of the elements in the middle RC stage depend on the current. In all the considered cases very high values of the determination coefficient R² were attained what proves a reasonable goodness of fit.

Analyzing the thermal resistances, the resistor R1, which corresponds to the standard junction-to-case resistance, has a fairly constant value up to the cold plate temperature of 50 °C. Then this value gradually increases, by approximately 10% at 90 °C. Referring to the value of 2.2 K/W given in the datasheet as the typical junction to the solder point resistance, the value of slightly more than 3.0 K/W seems very realistic, since the manufacturer did not specify any measurement conditions or the type of thermal model applied. The resistance values in the case when the thermal pad is not soldered are always by some 0.2 K/W higher, what is justified by the fact that in this case the heat diffusion to the MCPB is impeded and the resistance increases.

The value of the resistor R2, which represents the resistance of the interface between the package and the MCPCB, decreases significantly with the current and falls in the range from 8.8 to 14.2 K/W in the case when the thermal pad is soldered. In the other case this value is much higher, and ranges from 16.5 to 26.5 K/W, what demonstrates the importance of the proper use of the thermal pad. Owing to the forced water cooling, the value of the resistor R3 is the smallest one and it is equal to 0.48 K/W in the first case or 0.95 K/W in the latter one. This discrepancy will be discussed later on during the analysis of capacitance values.

Looking now at the capacitances, the capacitor C1 values, though constant, differ significantly for the two considered soldering cases and amount to 1.4 mJ/K and 2.0 mJ/K. This time again it can be explained by the fact that generated heat, when it is not properly sunk into the substrate spreads throughout a relatively larger volume of the package, hence the capacitance value of the heated volume is higher. The modeled value of capacitance C2, plotted in Figure 7a, slightly increases with current and at the value of 2.0 A is equal to some 20 mJ/K and 40 mJ/K. This time again the higher capacitance value for the case when the thermal pad is not soldered can be explained by the existence of a poor thermal contact, which is characterized also by a higher capacitance. Finally, the values of the capacitance C3 differ significantly, similarly as the ones for the resistor R3, however it should be pointed that they both correspond to virtually the same thermal time constant value of around 7 s. Looking at Figure 4, one can notice that the black peaks, which correspond to the thermal pad soldered, are indeed visibly lower, so probably this difference results from the identification errors introduced by the NID method which has a limited resolution.

3.4. Thermal Simulations

Considering that the detailed thermal model of the LED was not available, the parametric CTMs were validated by simulating the diode heating curves and comparing them with the measured ones. The resulting curves are plotted in Figure 7b for the two extreme cold plate temperature values and the heating currents of 0.5 A and 2.0 A. This time the measured curves are represented with black lines the simulated ones with lighter lines. Unlike in Figure 2, the double logarithmic scale was used in order to assess better the simulation errors for short heating times. As can be seen, the simulated curves follow accurately the measured ones at all the time instants over 1 ms. This relatively simple CTM provided in all cases an excellent accuracy with simulation errors remaining under 3% of the steady state temperature rise.

Undoubtedly, the simulation accuracy for short time instants could be improved by the addition of the fourth RC stage inserted next to the LED junction and corresponding to the peaks located to the left of the tiny minima at around 0.1±0.2 ms visible in Figure 4, which probably could be attributed to the die attach. However, taking into account that the details of the internal package structure are unknown, this stage was not included in the present model because it would increase greatly the computational effort of parametrization.

4. Conclusions

This paper demonstrated, based on a practical example, that with the proper determination of the real heating power and the division of thermal time constant spectra in the locations of their minima it is possible to obtain compact thermal models in the form of Cauer ladders with physically meaningful element values. Furthermore, it was shown that in the case of LEDs repeating the thermal measurements with the thermal pad soldered and left unsoldered might constitute an interesting alternative to the dual interface measurement method suggested in the JEDEC standard [24], where the thermal contact resistance with the heat sink is changed by applying thermal grease or loosening the attaching screw.

Moreover, extending the research presented by the authors in [26], the parametric relations describing the dependence of thermal resistances and capacitances on device operating current and temperature were proposed for the computation of CTM element values. The diode heating curves simulated with these parametric models showed very good agreement with the experimental results. Such models could become then thermal components of larger multidomain LED compact models coupling electrical, thermal and optical phenomena.

The parametrization of ladder CTMs rendered such models more versatile because now they could be used in different ambient conditions, similarly as the Delphi-style boundary condition independent models. Furthermore, the generation of such models does not require any proprietary information from a manufacturer because it is carried out based only on the knowledge of measured dynamic thermal responses. Finally, considering that the ladder thermal model components have physical meaning, i.e., they correspond to the semiconductor die, the package or the heat sink, the change of a certain component requires the replacement of only one RC stage in the model without the necessity to regenerate the entire model.