A New Modular Multilevel Inverter Based on Step-Up Switched-Capacitor Modules

Abstract

A new structure of switched capacitor multilevel inverter (SCMLI) capable of voltage boosting and with self-balancing ability is introduced in this article. This advantage is the result of a step by step rise of capacitor voltages in each module, supplied by just one DC voltage source. The proposed topology generates a sinusoidal output waveform with a magnitude several times greater than the input one. Higher output staircase AC voltage is obtained by applying a nearest level control (NLC) modulation technique. The most significant features of this configuration can be mentioned as: fewer semiconductor devices, remarkably low total harmonic distortion (THD), desirable operating under high/low frequency, high efficiency, inherent bipolar voltage production, easy circuit expansion, ease of control and size reduction of the circuit thanks to utilizing neither bulky transformer nor inductor. Moreover, the proposed SCMLI is comprehensively surveyed through theoretical investigation and a comparison of its effectiveness to recent topologies. Eventually, the operating principle of a 25-level prototype of the suggested SCMLI is validated by simulation in the MATLAB SIMULINK environment and experimental results.

1. Introduction

The growth of energy consumption and reduction in fossil fuel reserves has led to renewable energy penetration in power system. In order to transmit the electricity generated by these sources to grids, power electronic devices are widely required. Hence, the noticeable role of power electronic converters in these applications have attracted the attention of many researchers aiming for augmentation of quality, efficiency and costs of such systems [1]. Among all kinds of power electronic converters, inverters are vitally required in such equipment. According to [2], the necessity of high voltage and high power inverters are significantly observed in bulk power controls.

Initial inverters, built in three-level topologies, suffered from high voltage stresses and total harmonic distortion (THD) [3]. Consideration of these limitations, resulted in the introduction of the multilevel inverter (MLI). These inverters are considered favorably for their special characteristics in less THD, lower dv/dt stress, better electromagnetic compatibility and of course lower switching losses [3,4,5]. Quality improvement of output voltage wave form depends on the number of voltage levels in multilevel inverters (the greater the output voltage level, the greater the sinusoidal wave form). Based on the quality and type of source and high/medium power demand of circuit, different topologies for multilevel inverters are presented. These inverters are widely implemented in devices used daily such as ac motor equipment (like ac fans, mills, conveyers and pumps) which are commonly utilized in metal, power, oil and gas, water, mining, marine and chemistry industries [6].

The most applicable MLI topologies can be named as neutral point clamp (NPC) [7], flying capacitor (FC) [8], cascade H-bridge (CHB) [9] and switched capacitor (SC) [10] arrangement inverters. Each topology has its own weaknesses that made it necessary to introduce newer structures. For example, NPC and FC suffer from voltage balancing in their DC link capacitors due to their limited switching states. In CHB topology, the requirement of several DC sources causes considerable increase in the cost and size of the inverter.

Among these, the SC is more utilized in power electronic devices, thanks to its less source requirement (single DC source) and boosting capability with no need of any transformers or inductors and ease of controllability. The performance of SC inverter is summarized in charging several capacitors and then discharging them over the load in a predetermined pattern to make a staircase near the sinusoidal voltage. The output voltage amplitude is several times bigger than the input source depending on the structure and number of capacitors included. Recently, these topologies are used in applications such as: lasers, radars, X-rays [11], fuel-cell systems [12], UPS (uninterruptible power supplies) [13], White Light Emitting Diode (WLED), LCD drivers, fluorescent lamp [14], electrical vehicles [15], mobile equipment [16], Induction heating [17], grid integration of renewable energy systems [18], high-frequency AC micro grids [19], high-frequency AC power distribution systems [20], high-frequency-link DC transformers for a Medium Voltage Direct Current (MVDC) power distribution [21] and MRI (Magnetic Resonance Imaging) [22].

A new single-source multi-level inverter (MLI) based on the SC concept with the minimum number of switches is proposed by [23]. Reference [24] proposed another SC-based MLI. In this structure, not only is there no inductors but also larger voltage than the input one is produced. This increase is reached by connecting the capacitors in a series or parallel fashion. On the other hand, introducing two new MLIs consisting of SC units and H-bridges is presented by [25]. A single source SC-based MLI which makes it possible to reach several output levels is introduced by [26]. A different number of output levels is accessible by changing the number of SC cells. References [27,28] introduce new single-source switched capacitor multilevel inverter (SCMLI) structures producing high output voltage levels, aiming for reduction of both active and passive components. Considering power loss analysis is another noticeable aspect of these studies that further discussion over circuit loss is fundamentally investigated in [29,30].

Producing a 5-level output with 7 switches based on the SCMLI technique is presented in [31]. This structure is single source and requires 2 capacitors. Similarly, references [32,33] SC-based topologies are fed by one source aiming to boost the input voltage.

The presented article reveals a new single-source SCMLI topology, which is expected to operate in both high power and high voltage applications. In Section 2 the topology of proposed new SCMLI module and its cascaded structure is described. In Section 3 the operating principles of this topology is discussed. A comprehensive discussion on the proposed topology and others with similar criteria is performed in Section 4. Then, in Section 5, first, simulation results are presented and then experimental tests of the proposed topology are undertaken in the laboratory environment to verify the proposed inverter performance. Finally, Section 6 is devoted to the conclusion of this paper.

2. Proposed Topology

The structure of proposed SCMLI consists of two different parts which are connected one after another to achieve the desired performance (Figure 1). Each part consists of several switches and capacitors in order to generate predetermined voltage levels. The first part includes four capacitors and 14 switches (including 6 unidirectional and 4 bidirectional ones) controlled by 10 driver circuits.

Notice that the connection of two switches one after another form a unit to control the current flow bi-directionally. The topology is capable of generating 9 voltage levels containing 4 positive levels, 4 negative levels and a zero level. While the first part is made of one main module, the second part can be made by combining one or more sub-modules together. Each sub-module is made up of 2 capacitors and 8 switches (including 6 unidirectional and 1 bidirectional). By implementing 7 driver circuits, 5 different voltage levels (consist of 2 positive, 2 negative and a zero one) are achievable in each sub-module. Eventually, the predefined output voltage is achieved by combination of the two parts, which the number of sub-modules in the second part fundamentally depends on the desired output level.

3. Operating Principles

Figure 2 shows a 25-level prototype based on the proposed structure which consist of the main module and one sub-module in the second part. The output staircase waveform includes 12 positive, 12 negative and the zero level where each level is reached by synthesizing the different capacitors voltages. It is noticeable that, generating the required staircase waveform can be achieved considering the fact that all capacitors should be charged to the predetermined voltage. Besides, the limitation of rated voltage of the semiconductor devices must be taken into account during charge and discharge.

To reach the aforementioned essentials, specific switching patterns for capacitors charging and discharging should be considered.

3.1. Capacitors Charging Pattern

Achieving the favorable voltage waveform requires predetermined charging paths for the capacitors. To reach this goal, the initial step is to charge the capacitors placed in the first part (main module). Regarding Figure 3a capacitor C₁₂ is charged directly by the input source via S₀, S₁₂, S₁₃ and S₁₄ switches up to V_in. Similarly, C₁₃ is supplied by the source up to V_in via S₀, S₁₁, S₁₄ and S₁₅ switches (Figure 3b). Then, capacitors C₁₁, C₁₄ are charged to the 2V_in voltage by the serial connection of C₁₂ and C₁₃ (Figure 3c,d).

The next step is to charge the capacitors of the second part (the sub-module) by the serial combination of the capacitors voltages from the previous part. As shown in Figure 3e,f, by using 5 switches and 3 anti-parallel diodes, C₂₁ and C₂₂ are charged to 4V_in. Then, for rest of the modules, two different approaches could be considered. This is either to charge all the other modules with the same voltage, or keep on multiplying (doubling) the capacitor voltages in each step. As a result, for an n-module structure the charging mode for the first and second method could be indicated by $\left(1,2,4,4,4,\dots \right)\times V_{in}$ and $\left(1,2,4,8,\dots ,2^n\right)\times V_{in}$ respectively. Choosing each method depends on the amplitude of the input source, required output voltage level and the rated values of the semiconductors.

3.2. Output Multilevel Generation

The selected switching states for charge and discharge of the capacitors for the proposed SCMLI introduced in Figure 2 are brought in

Table 1. Selected switching states for charge and discharge of the capacitors (state of charge).

Levels	Switching States (C11, C12, C13, C14, C21, C22)
+12 Vin	15871(-↓↓↓↓↓)
+11 Vin	33871(--↑↓↓↓)
+10 Vin	1C8F1(-↓↓↑↓↓)/140F1(-↓↓-↓↓)
+9 Vin	330F1(--↑-↓↓)/14151(-↓--↓↓)
+8 Vin	15829(-↓↓↓-↓)/090F1(----↓↓) 1CA91(-↓↓↑↓↓)/2E151(-↑--↓↓)
+7 Vin	09151(--↓-↓↓)/33829(--↑↓-↓)/03A39(-↓↓↓↑↓)
+6 Vin	19611(↑↓↓-↓↓)/09A39(-↓↓↓↑↓)/140A9(-↓↓--↓)
+5 Vin	064B9(↓↓↓-↑↓)/330A9(--↑--↓)/14109(-↓---↓)
+4 Vin	0D411(↓↓↓-↓↓)/33109(--↑--↓)/15A4D(-↓↓↓-↑)
+3 Vin	33805(--↑↓--)/09109(--↓--↓)/2E249(-↑---↓)
+2 Vin	19E05(↑↓↓↓--)/1C885(-↓↓↑--) 09249(-↓↓--↓)/140F2(-↓↓---)
+1 Vin	14125(-↓----)/064CD(↓↓↓--↑) 2E0F2(-↑↓---)/1C9D2(-↓↓↑--)
0	19685(↑↓↓---)/2E125(-↑----) 33152(--↑---)/15A3A(--↓↑--)
−1 Vin	03A3A(-↓↓↓↑-)/19725(↑↓↓---) 2E265(-↑----)/09152(--↓---)
−2 Vin	11C3A(↓↓↓↓↑-)/09212(-↓↓---) 1C8AA(-↓↓↑↓-)/140AA(-↓↓-↓-)
−3 Vin	2E412(↓↑----)/064BA(↓↓↓-↑-)/1410A(-↓--↓-)
−4 Vin	3310A(--↑-↓-)/0D412(↓↓↓---)/15A4E(-↓↓↓↓↑)
−5 Vin	03A4E(-↓↓↓↓↑)/197A(↑↓↓-↓-)/03806(--↓↓↓↓)
−6 Vin	11E4E(↓↓↓↓↓↑)/0924A(-↓↓-↓-)/19E06(↑↓↓↓↓↓)
−7 Vin	064CE(↓↓↓-↓↑)/14126(-↓--↓↓)/33086(--↑-↓↓)
−8 Vin	1944A(↑↓↓-↓↓)/0D44A(↓↓↓-↓-) 33126(--↑-↓↓)/14266(----↓↓)
−9 Vin	2E266(-↑--↓↓)/19726(↑↓↓-↓↓)
−10 Vin	19666(↑↓↓-↓↓)/09266(-↓↓-↓↓)
−11 Vin	2E466(↓↑--↓↓)
−12 Vin	0D466(↓↓↓-↓↓)

. Besides, the state of charge for each capacitor is shown by either ↑, ↓ or – representing charging, discharging and no change, respectively. As the main module requires 10 gate signals for its 14 switches, then its switching state consists of a 10-digit binary number (including 0 and 1), which 1 means that the corresponding switch in the defined row is in ON state and 0 means that it is in OFF state. Moreover, the switching state of the submodule consists of a 7-digit number. To simplify the demonstration, we separated this 17-digit number into 4-digit parts and turned them from binary to hexadecimal numbers. Then, each switching state is revealed by a 5-digit hexadecimal vector as S = (S₀, S₁₁, m₁₁, m₁₂, m₂₁, m₂₂). Where each term means m₁₁ = (S₁₂, S₁₃, S₁₄, S₁₅), m₁₂ = (S₁₆, S₁₇, S₁₈, S₁₉), m₂₁ = (S₁₁₀, S₂₁, S₂₂, S₂₃), m ₂₂ = (S₂₄, S₂₅, S₂₆, S₂₇).

Figure 4 illustrates a few selected discharging paths related to the switching states of Table 1 resulting in a specific mixture of multiple capacitors shaping the staircase output voltage.

3.3. Modulation Strategy

The NLC (nearest level control) technique is utilized for operation of the proposed SCMLI in order to generate the desired staircase voltage. This method generates voltage level by converting the nearest voltage level (V_nl) to the predetermined voltage reference (V_ref) [29]. Implementation of this technique not only leads to augmentation of process speed but also eases the calculations by its conceptual and implementation simplicity.

Furthermore, small voltage steps beside low switching frequency allowance makes this technique one of the most suitable methods for high level MLIs. Considering mentioned options, proper switching states could be adapted for each voltage level by the help of switching table (see Table 1). As it is shown in Figure 5, initially the waveform is formed by comparing the V_ref and desired output voltage waveform. Then the V_nl can be determined with:

$${\mathrm{V}}_{\mathrm{n}\mathrm{l}}=\frac{1}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}\mathrm{round}({\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}})$$

(1)

3.4. Calculations of the Capacitances

To prevent capacitors undercharging and maintaining their voltage ripple in an acceptable range, the capacitances should be determined carefully in the SCMLI topologies. Two main factors should be considered while calculating the circuit capacitances: (1) amplitude of the output current and the phase difference between output voltage and current (2) capacitors discharging time in the worst case. Therefore, maximum discharging of each capacitor can be calculated as [24]:

$$\Delta {\mathrm{Q}}_{\mathrm{C}\mathrm{i}}={\displaystyle {\int }_{{\mathrm{t}}_{1\mathrm{i}}}^{{\mathrm{t}}_2{}_{\mathrm{i}}}{\mathrm{I}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\sin (2\mathsf{\pi }{\mathrm{f}}_{\mathrm{o}}\mathrm{t}-\mathsf{\varphi })}\mathrm{d}\mathrm{t}$$

(2)

where f_o is fundamental output frequency and I_out is the amplitude of the output current. [t_1i, t_2i] is the longest discharging period for each capacitor to demonstrate the worst case. Notice that each pair of (C₁₂, C₁₃), (C₁₁, C₁₄) and (C₂₁, C₂₂) have the same capacitance values.

Considering k as the maximum acceptable voltage ripple, the equivalent capacitance of the circuit while supplying the load is obtained as:

$${\mathrm{C}}_{\mathrm{e}\mathrm{q}}\ge \frac{\Delta {\mathrm{Q}}_{\mathrm{C}}}{\mathrm{k}{\mathrm{V}}_{\mathrm{e}\mathrm{q}}}$$

(3)

As the capacitors C₁₂ and C₁₃, are charged directly by the input source (see Figure 3a,b), thus their voltage is equal to:

$${\mathrm{V}}_{12}={\mathrm{V}}_{13}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(4)

Considering p percent tolerance for voltage drop while charging each capacitor, C₁₁ and C₁₄ are charged by series combination of C₁₂ and C₁₃ (see Figure 3c,d). Thus their voltage would be calculated as:

$${\mathrm{V}}_{11}={\mathrm{V}}_{14}=(1-\mathrm{p})\times ({\mathrm{V}}_{12}+{\mathrm{V}}_{13})=\frac{\frac{{\mathrm{C}}_{12}}{2}}{\frac{{\mathrm{C}}_{12}}{2}+{\mathrm{C}}_{11}}\times \left({\mathrm{V}}_{12}+{\mathrm{V}}_{13}\right)$$

(5)

Meaning that ${\mathrm{V}}_{11}={\mathrm{V}}_{14}=2(1-\mathrm{p})\times {\mathrm{V}}_{\mathrm{in}}$. Also the voltages across C₁₂ and C₁₃ would decrease to ${\mathrm{V}}_{12}={\mathrm{V}}_{13}=(1-\mathrm{p})\times {\mathrm{V}}_{\mathrm{in}}$, unless they are charged again by the DC source. Consequently C₁₁ is obtained by ${\mathrm{C}}_{11}={\mathrm{C}}_{14}=\frac{{\mathrm{C}}_{12}}{2}\times \frac{\mathrm{p}}{(1-\mathrm{p})}$. Finally, C₂₁ and C₂₂ are charged by series combination of either C₁₁, C₁₂ and C₁₃ or C₁₄, C₁₂ and C₁₃ (see Figure 3e,f) up to:

$${\mathrm{V}}_{21}={\mathrm{V}}_{22}=4{(1-\mathrm{p})}^2\times {\mathrm{V}}_{\mathrm{in}}$$

(6)

Which means that ${\mathrm{C}}_{21}={\mathrm{C}}_{22}=\frac{{\mathrm{C}}_{12}}{2}\times \frac{{\mathrm{p}}^2}{(1-\mathrm{p})}$. Afterwards, in order to transfer the voltage of each sub-module to the next one properly with minimum possible voltage drop, the capacitance values in each sub-module should be $\frac{1}{2}\times \frac{\mathrm{p}}{(1-\mathrm{p})}$ times of the previous one. By knowing the value of C_eq and the aforementioned equations, the exact value of every capacitor can be obtained.

4. Discussion

This section presents a discussion on the proposed topology, including two parts: comparison of the proposed structure with a few existing ones, and determination of losses and efficiency.

4.1. Comparison

Table 2. Comparison of the Suggested SCMLI with six other topologies for a (2N + 1) level output.

Items	Proposed	[10]	[23]	[24]	[25]	[26]	[28]
Switches	$-18+8{\log }_2(2\mathrm{N}+8)$	2N + 4	2N + 2	3N + 4	2N + 2	N + 4	3N + 1
Diodes	0	2N − 2	N − 1	0	N − 1	2N − 2	0
Capacitors	$-4+2{\log }_2(2\mathrm{N}+8)$	N − 1	N − 1	N - 1	N − 1	N − 1	N − 1
Drivers	$-18+7{\log }_2(2\mathrm{N}+8)$	2N + 4	2N + 2	3N + 4	2N + 2	N + 4	3N + 1
Bipolar output	inherent	With H-Bridge	With H-Bridge	With H-Bridge	With H-Bridge	With H-Bridge	inherent
PIV(*Vin)	$\frac{2\mathrm{N}+8}{4}$	N	N	N	N − 1	N	N
TSV(*Vin)	$-20+\frac{11(2\mathrm{N}+8)}{4}$	${\mathrm{N}}^2+5\mathrm{N}+1$	$\frac{{\mathrm{N}}^2+11\mathrm{N}-4}{2}$	7N	7N − 7	${\mathrm{N}}^2+4\mathrm{N}-1$	$\frac{{\mathrm{N}}^2+5\mathrm{N}}{2}$
Output levels	2N + 1	2N + 1	2N + 1	2N + 1	2N + 1	2N + 1	2N + 1

reveals a comprehensive study on the proposed SCMLI structure and six others, for a (2N + 1) level output voltage. The study is categorized into seven parts considering: number of active switches, series diodes, capacitors, driver circuits, the ability to produce bipolar output, peak inverse voltage (PIV) and total standing voltage (TSV).

The comparison results are illustrated in Figure 6. As shown in Figure 6a, in terms of the semiconductor devices the presented SCMLI utilizes much less active switches and diodes to produce the same output voltage. One may note that [26] needs less active switches, but it is important that [26] uses two series diodes to generate each voltage level. Figure 6b in which the aforementioned topologies are compared in terms of number of capacitors involved in their circuit, implies that the presented topology requires less than 10 capacitors to produce high level output voltages thanks to its multiplying characteristic.

It is noteworthy that unlike most other SCMLIs, the proposed concept requires no auxiliary circuit like H-bridge to generate a bipolar voltage. A closer look at Figure 6c reveals that the suggested topology can operate by using semiconductor devices with lower ratings, consequently reducing the total cost of the circuit. In addition, having the lowest amount of the TSV (see Figure 6d) makes the proposed structure suitable for high-voltage applications.

4.2. Determination of Losses and Efficiency

Total circuit loss fundamentally depends on two important sources namely switching and conduction losses [30]. Switching loss enrolls the most important part of circuit loss caused by switching delays which are semiconductor devices inherent characteristics. This source of loss occurs in the course of turning ON and OFF of the active switches determined by the following Equations [27]:

$$P_{sw-i(ON)}=f_{sw}{\displaystyle {\int }_0^{t_{on}}{V}_{offstate-i}(t)\cdot i(t)dt}=\frac{1}{6}{f}_{sw}{V}_{offstate-i}{I}_{onstate1-i}{t}_{on}$$

(7)

$$P_{sw-i(OFF)}=f_{sw}{\displaystyle {\int }_0^{t_{off}}{V}_{offstate-i}(t)\cdot i(t)dt}=\frac{1}{6}{f}_{sw}{V}_{offstate-i}{I}_{onstate2-i}{t}_{off}$$

(8)

Note that in these equations, f_sw represents the switching frequency of each switch of the circuit, $V_{offstate-i}$ stands for the off-state voltage of ith switch, $I_{onstate1-i}$ is the current of ith switch when the switch is entirely turned on, and $I_{onstate2-i}$ shows the current of ith switch before turning off. Therefore, overall switching loss of the whole circuit can be obtained from the following equation:

$$P_{sw}={\displaystyle \sum _{i=1}^{N-switch}\left({\displaystyle \sum _{j=1}^{N_{on(i)}}{P}_{sw-on(ij)}}+{\displaystyle \sum _{j=1}^{N_{off(i)}}{P}_{sw-off(ij)}}\right)}$$

(9)

Consider that N_on(i) and N_off(i) are the number of times which ith switch turns on and off, throughout one cycle. On the other hand, conduction loss is basically generated due to current of semiconductors and hence the load. This loss is calculated by [29]:

$$P_{con-L}=P_{{}_{con-L}}^{sw}+P_{{}_{con-L}}^D=(k_1\cdot V_{on}^{sw}+k_2\cdot V_{on}^D)\cdot i_{av-L}+(k_1\cdot R_{on}^{sw}+k_2\cdot R_{on}^D)\cdot i_{rms-L}^2$$

(10)

where i_av-L and i_rms-L are average and RMS current of voltage level L, respectively. Coefficients k₁ and k₂ are the number of switches and diodes involved in each level, respectively. Finally, total conduction losses can be calculated as:

$$P_{con}={\displaystyle \sum _{L=-12}^{12}{P}_{con-L}}$$

(11)

Efficiency (η) is obtained from:

$$\eta =\left(\frac{P_{out}}{P_{out}+P_{loss}}\right)\times 100$$

(12)

where P_loss includes switching losses (P_sw) and conduction losses (P_con). For the proposed SCMLI with ${\mathrm{V}}_{\mathrm{in}}=30\mathrm{V}$, ${\mathrm{V}}_{\mathrm{out}-\max }=360\mathrm{V}$, ${\mathrm{f}}_{\mathrm{out}}=50\mathrm{Hz}$ and using IRF740MOSFET switches, exact calculations were made and the efficiency reached to 92.63%. It is worth highlighting that in the proposed topology of this article the f_sw is considerably lower than conventional structures (in the range of 50 Hz up to 1 KHz). Consequently, achieving both lower switching loss and total circuit loss is accessible.

Moreover, in

Table 3. Comparison of the proposed topology with other recently introduced ones in terms of efficiency.

Topologies	I Load (A)	P Out (W)	Efficiency (%)
			Theoretical	Experimental
Proposed	1	180	92.13	90.22
	2	360	92.63	90.85
	4	720	91.65	88.69
	8	1440	91.17	87.61
[24]	0.5	5.8	85.9	84.9
[26]	3.1	247.5	Not mentioned	89.2
[28]	2	1000	90	87.5

the proposed inverter has been compared with other recently introduced topologies in terms of the efficiency. The results depict that the proposed converter not only has the least possible number of components (including active switches with lower TSV, drivers and capacitors), but also enjoys higher efficiency under different load conditions.

The overall efficiency of the proposed 25-level converter is investigated experimentally and theoretically with different loadings as depicted in Figure 7. As can be seen, the lower efficiencies have been recorded by increasing the output power. These high-efficiency values occurred as a result for the few involved components in the current flow paths. The measured efficiencies are in good agreement with theoretical ones.

5. Results

Evaluation of the proposed theory is comprehensively accomplished in both simulation and experimental sections which are exclusively explained in the following parts.

5.1. Simulation Results

In order to prove the concept of the presented structure, MATLAB simulations were done on a 25-level (30 volts each level) inverter of the proposed topology, using NLC modulation. Figure 8a shows the output voltage and current waveforms for an input of 30 volts (DC) and a resistive load of R = 180 Ω.

It is worth noting that the amplitude of the output voltage is 12 times the input. The FFT (fast Fourier transform) of the load voltage is illustrated in Figure 8b. This reveals that the amount of Voltage THD is 3.27% and the amplitude of all voltage harmonics are below 0.6% of the fundamental one.

On the other hand, Figure 8c illustrates the output waveforms of a resistive-inductive load with a power factor of 0.75 (R = 180 Ω and L = 500 mH). In this case, the harmonic content of the load current is 0.18%, which is considerably lower (Figure 8d).

5.2. Experimental Results

In order to validate the simulation results, a laboratory prototype of a 25-level inverter of the presented SCMLI is made. Figure 9 shows the test setup which is fabricated using the parameters of

Table 4. Laboratory setup specifications.

Component	Specification
Input voltage (Vin)	30 V
Output voltage levels	25
Output frequency	50 Hz
Switches	IRF740 MOSFET
Capacitors	C11 = C14 = 1300 μF C12 = C13 = 23,000 μF C21 = C22 = 130 μF
Switches gate driver	HCPL3120
Voltage probe	PINTEK DP-50
Current probe	FLUKE 80i-110s AC/DC
R load	180 Ω
R-L load	180 Ω, 500 mH

.

Figure 10a,b illustrate the experimental results of the test setup, for a pure resistive load of R = 180 Ω. The voltage and current waveforms comprise 25 steps from peak to peak (each of 30 volts). Note that the voltage probe is set on 100:1 ratio. In addition, test results of a resistive-inductive load (R = 180 Ω, L = 50 mH) with a power factor of 0.75 is brought in Figure 10c,d.

6. Conclusions

The introduced novel switched-capacitor multilevel inverter (SCMLI) with self-balancing capability presents a modular structure with high gain modules in which each capacitor is charged by two capacitors through a predetermined path. The NLC modulation technique is applied for operation of the configuration resulting in a better sinusoidal output voltage waveform. Theoretical analysis, along with simulation in MATLAB software, represent the efficiency peak at 92.63% and also the THD reaching 3.27%. Moreover, comparative study implies that the suggested construction performs better in terms of PIV and TSV compared with recent topologies. The proposed topology not only needs fewer capacitors and semi-conductor devices, but also, thanks to inherent specifications of the module, it utilizes fewer driver circuits. Furthermore, the operation of the proposed structure is validated by test results of a 25-level prototype.