# An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches

^{1}

^{2}

^{3}

^{4}

^{5}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Analysis of the Proposed Nine-Level Inverter

#### 2.1. Circuit Description

_{IN}, ±3V

_{IN}/2, ±V

_{IN}, ±V

_{IN}/2 and 0). As demonstrated in Figure 1, it comprises twelve power switches, two capacitors (C

_{1}, C

_{2}), and only one input DC source with the advantage of regenerative capability. The output voltage can be boosted up to 2V

_{IN}by connecting the input source with pre-charged capacitors in series. It should be underscored that the blocking voltage of all switches employed in the proposed inverter is equal to the input DC source (i.e., V

_{IN}), with the exception of S

_{7}, S

_{8,}and S

_{12}which block only half the V

_{IN}. In other words, it generates a bipolar output voltage without using end-side H-bridge. This ability is considered a beneficial feature of the proposed circuit since the lower switch voltage rating, the cheaper switch.

_{1}and C

_{2}are charged up to V

_{IN}/2 by turning S

_{3}and S

_{4}on during 0 and ±1V

_{IN}levels. Then, the capacitors are connected in parallel at ±V

_{IN}/2 and ±3V

_{IN}/2 levels. Thereby, the voltage across them is balanced. Finally, they are discharged across the load during ±V

_{IN}/2 and ±2V

_{IN}levels. Relying on this simple switching plan, the proposed inverter does not require any external balancer circuit.

#### 2.2. Comparative Assessment

_{IN}and V

_{IN}/2 respectively, while [13] requires nineteen IGBTs with the voltage ratings of V

_{IN}. Thereby, the proposed inverter can be an acceptable alternative to the topologies listed in Table 1.

## 3. Multicarrier PWM Strategy

_{t1}to V

_{t8}) arranged with shifts in amplitudes are required (see Figure 3a). It should be noted that they are the same in amplitude (A

_{t}), frequency (f

_{t}) and phase [16,17]. The carriers are compared to a reference waveform (V

_{ref}) which results in generating appropriate fire pulses for all switches. For instance, S

_{11}is turned on when V

_{ref}> V

_{t1}or V

_{t2}< V

_{ref}< V

_{t1}or V

_{t8}< V

_{ref}< V

_{t7}or V

_{ref}<V

_{t8}. In other words, S

_{11}must be turned on when S

_{1}: ON, S

_{4}: ON, S

_{3}: OFF (or S

_{2}: ON, S

_{3}: ON, S

_{4}: OFF), which can be observed in Figure 2. Similarly, S

_{12}is turned on when V

_{ref}> V

_{t1}or V

_{t3}< V

_{ref}< V

_{t2}or V

_{t5}< V

_{ref}< V

_{t4}or V

_{t7}< V

_{ref}< V

_{t6}or V

_{ref}< V

_{t8}. In other words, S

_{12}must be turned on when S

_{7}and S

_{8}are OFF (see Figure 2). Further clarification concerning switching strategy is brought up in Figure 3b and Table 3.

## 4. Loss Distribution and Thermal Modeling

#### 4.1. Power Loss Analysis

_{C}, P

_{S}and P

_{R}which are elaborated as follows:

#### 4.1.1. Conduction Loss (P_{C})

_{C}is caused by parasitic resistance (i.e., ON-state resistance of the switch (R

_{S}) and its parallel diode (R

_{D}), capacitor internal resistance (R

_{C})) involved in the current paths [18]. Table 4 shows the equivalent value of the parasitic resistance (R

_{eq}) existing in each voltage level. It should be noted that in the present work R

_{S}, R

_{D}

_{,}and R

_{C}are considered equal to 0.27 Ω, 0.05 Ω, and 0.03 Ω, respectively.

_{ref}| < A

_{t}, the output voltage switches between 0 and +V

_{IN}/2 (see Figure 3a). Consequently, the output current passes through two switches and two diodes (three switches, two diodes, and one capacitor) during 0 (+V

_{IN}/2) level, as depicted in Table 4. In this case, the energy dissipated within 0 < t < t

_{1}(t

_{6}< t < t

_{7}or t

_{12}< t < 2π) is attained by Equation (1) in which A

_{t}, A

_{ref}

_{,}and f

_{ref}are considered equal to 0.25, 0.9, and 50 Hz, respectively [18]. Moreover, t

_{1}is calculated as follows:

#### 4.1.2. Switching Loss (P_{S})

_{on}and t

_{off}) leads to P

_{S}, which is highly proportional to the f

_{S}. The turn-on and turn-off power loss of the switch S are attained by [19]:

_{S}

^{on}(I

_{S}

^{off}) is the switch current after (before) turning on (off). Considering t

_{on}= t

_{off}= 58 ns and f

_{t}= 4 kHz, P

_{S}for all the switches is obtained as follows:

#### 4.1.3. Power Loss Generated by Capacitor Voltage Ripple (P_{R})

_{R}is due to the voltage difference between the capacitor and input DC source during the charging periods. Generally, the maximum discharging value of each capacitor in a switched-capacitor circuit is attained by [13,18]:

_{c}, t

_{d}] is the discharging interval of each capacitor. According to Figure 2a and Figure 3a, the maximum discharging period of C

_{1}(or C

_{2}) is equal to [t

_{3}, t

_{4}]. Thus, considering maximum acceptable voltage drop across C

_{1}(or C

_{2}) equal to ΔV

_{ripple}, the capacitance of each capacitor is calculated by [13,18]:

_{out}= 1.4 kW (I

_{Load}= 7 A, V

_{IN}=200 V) and ΔV

_{ripple}= 10%, the capacitances for the proposed inverter are obtained as follows:

_{IN}/2 (see Figure 2). Consequently, P

_{R}for the proposed topology is attained as follows:

#### 4.2. Thermal Model

_{j}[20]. This temperature, for safety reasons, should be monitored and kept within a specified range during the inverter operation. Figure 5a illustrates the thermal model implemented for a single semiconductor, in which the thermal impedance between junction and case (Z

_{th}) is considered a four-layer foster network (see Figure 5b) [21,22]. It should be noted that Z

_{c}and Z

_{s}are the thermal impedances from the case to the heat sink and from the heat sink to the ambient, respectively. These are found on the manufacturer datasheet.

_{a}is considered equal to 40 °C and the PM75CLA060 switch produced by Mitsubishi Electric is chosen in the thermal estimation.

_{j}of some power switches employed in the proposed inverter at 20 kW output power is illustrated in Figure 6. It can be observed that S

_{12}has the lowest T

_{j}(approximately 43.9 °C), while this temperature approaches 46.7 °C for S

_{11}.

## 5. Simulation and Experimental Results

_{t}= 4 kHz, C

_{1}= C

_{2}= 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V, respectively. The proposed topology has also been simulated under step change in the load, and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify the inherent capacitor voltage balancing ability during inverter operation.

_{3}, S

_{5,}and S

_{11}(also S

_{1}, S

_{2}, S

_{4}, S

_{6}, S

_{9}and S

_{10}) must withstand voltages equal to the input DC source (i.e., 200 V). Other switches (S

_{7}, S

_{8}and S

_{12}), however, block voltages equal to half the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Nomenclature

MLIs | Multilevel inverters |

CHB | Cascaded H-bridge |

NPC | Neutral point clamped |

FC | Flying capacitor |

TSV | Total standing voltage (V) |

PIV | Peak inverse voltage (V) |

PWM | Pulse width modulation |

DSP | Digital signal processor |

V_{IN} and I_{IN} | Input voltage (V) and current (A) of the inverter |

V_{Load} and I_{Load} | Maximum load voltage (V) and current (A) |

V_{t} | Triangular carrier of the PWM modulation |

V_{ref} | Reference waveform of the PWM modulation |

V_{S} and I_{S} | Voltage (V) and current (A) of the switch S |

ΔV_{ripple} | Voltage ripple across each capacitor (V) |

ΔQ_{C} | Maximum discharging value of the capacitor C |

N | Number of power switches with the same PIV |

M | Number of cascaded modules |

A_{t} and f_{t} | Amplitude and frequency of the triangular carriers (V_{t}) |

A_{ref} and f_{ref} | Amplitude and frequency of the reference waveform (V_{ref}) |

P_{C} | Conduction loss (W) |

P_{S} | Switching loss (W) |

P_{R} | Power loss caused by capacitor voltage ripple (W) |

P_{S, on} and P_{S, off} | Turn-on and turn-off power loss of the switch S (W) |

P_{out} | Inverter output power (W) |

R_{S} and R_{D} | ON-state resistance of the switch S and its parallel diode (Ω) |

R_{C} | Capacitor internal resistance (Ω) |

R_{eq} | Equivalent value of the parasitic resistance in each voltage level (Ω) |

R and L | Resistance (Ω) and inductance (H) of the load |

t_{on} and t_{off} | Rise and fall times of the switch S (s) |

f_{S} | Switching frequency (Hz) |

T_{j} | Semiconductor junction temperature (°C) |

T_{c} | Semiconductor case temperature (°C) |

T_{s} | Heat sink temperature (°C) |

T_{a} | Ambient temperature (°C) |

Z_{th} | Thermal impedance between junction and case of the semiconductor |

Z_{c} | Thermal impedance between semiconductor case and its heat sink |

Z_{s} | Thermal impedance between heat sink and ambient |

## References

- Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Wu, B.; Rodriguez, J.; Perez, M.A.; Leon, J.I. Recent Advances and Industrial Applications of Multilevel Converters. IEEE Trans. Ind. Electron.
**2010**, 57, 2553–2580. [Google Scholar] [CrossRef] - Yuan, X. Derivation of Voltage Source Multilevel Converter Topologies. IEEE Trans. Ind. Electron.
**2017**, 64, 966–976. [Google Scholar] [CrossRef] [Green Version] - Rodriguez, J.; Franquelo, L.G.; Kouro, S.; Leon, J.I.; Portillo, R.C.; Prats, M.A.M.; Perez, M.A. Multilevel Converters: An Enabling Technology for High-Power Applications. Proc. IEEE
**2009**, 97, 1786–1817. [Google Scholar] [CrossRef] - Gupta, K.K.; Ranjan, A.; Bhatnagar, P.; Kumar Sahu, L.; Jain, S. Multilevel Inverter Topologies with Reduced Device Count: A Review. IEEE Trans. Power Electron.
**2016**, 31, 135–151. [Google Scholar] [CrossRef] - Leon, J.I.; Vazquez, S.; Franquelo, L.G. Multilevel Converters: Control and Modulation Techniques for Their Operation and Industrial Applications. Proc. IEEE
**2017**, 105, 2066–2081. [Google Scholar] [CrossRef] - Akagi, H. Multilevel Converters: Fundamental Circuits and Systems. Proc. IEEE
**2017**, 105, 2048–2065. [Google Scholar] [CrossRef] - Wu, B.; Narimani, M. Diode-Clamped Multilevel Inverters. In High-Power Converters and AC Drives; Wiley-IEEE Press: New York, NY, USA, 2017. [Google Scholar]
- Khounjahan, H.; Abapour, M.; Zare, K. Switched-Capacitor Based Single Source Cascaded H-bridge Multilevel Inverter Featuring Boosting Ability. IEEE Trans. Power Electron.
**2018**, 34, 1113–1124. [Google Scholar] [CrossRef] - Lee, S. Single-Stage Switched-Capacitor Module (S3CM) Topology for Cascaded Multilevel Inverter. IEEE Trans. Power Electron.
**2018**, 33, 8204–8207. [Google Scholar] [CrossRef] - Choi, J.S.; Kang, F.S. Seven-Level PWM Inverter Employing Series-Connected Capacitors Paralleled to a Single DC Voltage Source. IEEE Trans. Ind. Electron.
**2015**, 62, 3448–3459. [Google Scholar] - Hinago, Y.; Koizumi, H. A Switched-Capacitor Inverter Using Series/Parallel Conversion. IEEE Int. Symp. Circuits Syst.
**2010**, 62, 3188–3191. [Google Scholar] - Wang, K.; Zheng, Z.; Wei, D.; Fan, B.; Li, Y. Topology and Capacitor Voltage Balancing Control of a Symmetrical Hybrid Nine-Level Inverter for High-Speed Motor Drives. IEEE Trans. Ind. Appl.
**2017**, 53, 5563–5572. [Google Scholar] [CrossRef] - Taghvaie, A.; Adabi, J.; Rezanejad, M. A Self-Balanced Step-Up Multilevel Inverter Based on Switched-Capacitor Structure. IEEE Trans. Power Electron.
**2018**, 33, 199–209. [Google Scholar] [CrossRef] - Lee, S.S.; Sidorov, M.; Lim, C.S.; Idris, N.R.N.; Heng, Y.E. Hybrid Cascaded Multilevel Inverter (HCMLI) With Improved Symmetrical 4-level Submodule. IEEE Trans. Power Electron.
**2018**, 33, 932–935. [Google Scholar] [CrossRef] - Lee, S.S. A Single-Phase Single-Source 7-Level Inverter with Triple Voltage Boosting Gain. IEEE Access
**2018**, 6, 30005–30011. [Google Scholar] [CrossRef] - McGrath, B.P.; Holmes, D.G. Multicarrier PWM Strategies for Multilevel Inverters. IEEE Trans. Ind. Electron.
**2002**, 49, 858–867. [Google Scholar] [CrossRef] - Mei, J.; Xiao, B.; Shen, K.; Tolbert, L.M.; Zheng, J.Y. Modular Multilevel Inverter with new Modulation Method and its Application to Photovoltaic Grid-Connected Generator. IEEE Trans. Power Electron.
**2013**, 28, 5063–5073. [Google Scholar] [CrossRef] - Tsunoda, A.; Hinago, Y.; Koizumi, H. Level-and Phase-Shifted PWM for Seven-Level Switched-Capacitor Inverter Using Series/Parallel Conversion. IEEE Trans. Ind. Electron.
**2014**, 61, 4011–4021. [Google Scholar] [CrossRef] - Barzegarkhoo, R.; Moradzadeh, M.; Zamiri, E.; Kojabadi, H.M.; Blaabjerg, F. A new Boost Switched-Capacitor Multilevel Converter with Reduced Circuit Devices. IEEE Trans. Power Electron.
**2018**, 33, 6738–6754. [Google Scholar] [CrossRef] - Albarbar, A.; Batunlu, C. Thermal Analysis of Power Electronic Devices Used in Renewable Energy Systems; Springer-Cham: Cham, Switzerland, 2018. [Google Scholar]
- Ma, K.; Muñoz-Aguilar, R.S.; Rodriguez, P.; Blaabjerg, F. Thermal and Efficiency Analysis of Five-Level Multilevel-Clamped Multilevel Converter Considering Grid Codes. IEEE Trans. Ind. Appl.
**2014**, 50, 415–423. [Google Scholar] [Green Version] - Lixiang, W.; McGuire, J.; Lukaszewski, R.A. Analysis of PWM Frequency Control to Improve the Lifetime of PWM Inverter. IEEE Trans. Ind. Electron.
**2011**, 47, 922–929. [Google Scholar] [CrossRef] - Ma, K.; Bahman, A.S.; Beczkowski, S.; Blaabjerg, F. Complete Loss and Thermal Model of Power Semiconductors Including Device Rating Information. IEEE Trans. Power Electron.
**2015**, 30, 2556–2569. [Google Scholar] [CrossRef] - Rajapakse, A.; Gole, A.; Jayasinghe, R. An Improved Representation of FACTS Controller Semiconductor Losses in EMTP-Type Programs Using Accurate Loss-Power Injection Into Network Solution. IEEE Trans. Power Del.
**2009**, 24, 381–389. [Google Scholar] [CrossRef] - Tu, Q.; Xu, Z. Power Losses Evaluation for Modular Multilevel Converter with Junction Temperature Feedback. In Proceedings of the IEEE Power and Energy Society General Meeting, Detroit, MI, USA, 24–29 July 2011; pp. 1–7. [Google Scholar]

**Figure 2.**Switching states of the proposed inverter, (

**a**) +2V

_{IN}, (

**b**) +3V

_{IN}/2, (

**c**) +V

_{IN}, (

**d**) +V

_{IN}/2, (

**e**) 0; (

**f**) −V

_{IN}/2, (

**g**) −V

_{IN}, (

**h**) −3V

_{IN}/2, (

**i**) −2V

_{IN}.

**Figure 10.**The effect of (

**a**) modulation index on the V

_{Load}, (

**b**) switching frequency on the V

_{Load}.

Comparison Item | CHB (Con.) | [11] (2010) | [12] (2017) | [13] (2018) | [14] (2018) | [15] (2018) | Proposed | |
---|---|---|---|---|---|---|---|---|

Level | 9 | 9 | 9 | 9 | 9 | 7 | 9 | 8M * + 1 |

Switch | 16 | 13 | 12 | 19 | 10 | 16 | 12 | 12M |

Capacitor | - | 3 | 4 | 3 | - | 2 | 2 | 2M |

DC source | 4 | 1 | 1 | 1 | 4 | 1 | 1 | M |

N * × PIV | 16 × 1V_{IN} | 4 × 4V_{IN}9 × 1V _{IN} | 4 × 4V_{IN}8 × 1V _{IN} | 19 × 1V_{IN} | 4 × 4V_{IN}2 × 3V _{IN}4 × 1V _{IN} | 16 × 1V_{IN} | 9 × V_{IN}3 × V _{IN}/2 | 9M × V_{IN}3M × V _{IN}/2 |

TSV | 16V_{IN} | 25V_{IN} | 24V_{IN} | 19V_{IN} | 26V_{IN} | 16V_{IN} | 21V_{IN}/2 | M × (21V_{IN}/2) |

Part | Part Number | Voltage Rating (V) | Unit Price * (€) | [11] | [12] | [13] | [15] | Proposed |
---|---|---|---|---|---|---|---|---|

MOSFETs | STW40NF20 | 200 | 3.53 | 9 | 8 | 19 | - | 3 |

SUP40N25-60-E3 | 250 | 4.43 | - | - | - | 16 | 9 | |

FQL40N50 | 450 | 7.73 | - | - | - | - | - | |

SIHG47N60AEFGE3 | 600 | 7.82 | 4 | 4 | - | - | - | |

Capacitors | E32D151HPN472TEE3M | 150 | 23.00 | 3 | 2 | 4 | - | 2 |

B43713F2478M000 | 250 | 39.39 | - | - | - | 2 | - | |

ALS31A472NF350 | 350 | 48.83 | - | 2 | - | - | - | |

Gate driver | IRS21271SPBF | - | 1.34 | 13 | 12 | 19 | 14 | 12 |

Total cost (€) | 149.47 | 219.26 | 184.53 | 168.42 | 112.54 |

Relationship between the Carriers and V_{ref} | ON-State IGBTs | Levels |
---|---|---|

V_{ref} > V_{t1} | S_{1}-S_{4}-S_{5}-S_{10}-S_{11}-S_{12} | +4V_{IN} |

V_{t2} < V_{ref} < V_{t1} | S_{1}-S_{4}-S_{5}-S_{7}-S_{8}-S_{10}-S_{11} | +3V_{IN} |

V_{t3} < V_{ref} < V_{t2} | S_{1}-S_{3}-S_{4}-S_{5}-S_{6}-S_{10}-S_{12} | +2V_{IN} |

V_{t4} < V_{ref} < V_{t3} | S_{1}-S_{3}-S_{5}-S_{7}-S_{8}-S_{10} | +1V_{IN} |

V_{t5} < V_{ref} < V_{t4} | S_{2}-S_{3}-S_{4}-S_{5}-S_{6}-S_{10}-S_{12} | 0 |

V_{t6} < V_{ref} < V_{t5} | S_{2}-S_{4}-S_{6}-S_{7}-S_{8}-S_{9} | −1V_{IN} |

V_{t7} < V_{ref} < V_{t6} | S_{2}-S_{3}-S_{4}-S_{5}-S_{6}-S_{9}-S_{12} | −2V_{IN} |

V_{t8} < V_{ref} < V_{t7} | S_{2}-S_{3}-S_{6}-S_{7}-S_{8}-S_{9}-S_{11} | −3V_{IN} |

V_{ref} < V_{t8} | S_{2}-S_{3}-S_{6}-S_{9}-S_{11}-S_{12} | −4V_{IN} |

Output Level | R_{eq} (Ω) |
---|---|

0 | 2R_{S} + 2R_{D} = 0.64 |

±V_{IN}/2 | 3R_{S} + 2R_{D} + R_{C} = 0.94 |

±V_{IN} | 3R_{S} + R_{D} = 0.86 |

±3V_{IN}/2 | 5R_{S} + R_{D} + R_{C} = 1.43 |

±2V_{IN} | 6R_{S} + 2R_{C} = 1.68 |

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Saeedian, M.; Pouresmaeil, E.; Samadaei, E.; Manuel Godinho Rodrigues, E.; Godina, R.; Marzband, M.
An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches. *Energies* **2019**, *12*, 207.
https://doi.org/10.3390/en12020207

**AMA Style**

Saeedian M, Pouresmaeil E, Samadaei E, Manuel Godinho Rodrigues E, Godina R, Marzband M.
An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches. *Energies*. 2019; 12(2):207.
https://doi.org/10.3390/en12020207

**Chicago/Turabian Style**

Saeedian, Meysam, Edris Pouresmaeil, Emad Samadaei, Eduardo Manuel Godinho Rodrigues, Radu Godina, and Mousa Marzband.
2019. "An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches" *Energies* 12, no. 2: 207.
https://doi.org/10.3390/en12020207