An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches

Abstract

This article presents an innovative switched-capacitor based nine-level inverter employing single DC input for renewable and sustainable energy applications. The proposed configuration generates a step-up bipolar output voltage without end-side H-bridge, and the employed capacitors are charged in a self-balancing form. Applying low-voltage rated switches is another merit of the proposed inverter, which leads to extensive reduction in total standing voltage. Thereby, switching losses as well as inverter cost are reduced proportionally. Furthermore, the comparative analysis against other state-of-the-art inverters depicts that the number of required power electronic devices and implementation cost is reduced in the proposed structure. The working principle of the proposed circuit along with its efficiency calculations and thermal modeling are elaborated in detail. In the end, simulations and experimental tests are conducted to validate the flawless performance of the proposed nine-level topology in power systems.

1. Introduction

In recent years, extensive research has been carried out on multilevel inverters (MLIs) due to their potential in various industrial applications, particularly grid-connected renewable energy sources, machine drives, and high-voltage direct current transmission systems. Improved output waveforms quality, reduced device stress (dv/dt), and increased efficiency are some merits of the MLIs in comparison with the standard two-level inverter [1,2,3,4]. The most popular traditional/basic multilevel topologies are CHB, NPC, and FC, which have widely been put into commercial use in high/medium voltage systems (above 3 kV). Nonetheless, high control/modulation technique complexity and large power electronic device count (dc power supplies, semiconductors, and capacitors) are cited as demerits of the aforementioned topologies [5,6,7].

To overcome these drawbacks, researchers and industrialists all around the world are contributing to present innovative topologies with the ability to produce more voltage levels with reduced device count and to further improve energy efficiency. Apart from that, it has tried to develop MLIs with lower voltage-rating switches and to cope with the voltage unbalancing problem in NPC and FC. These attempts lead not only to reducing filter requirement and simplicity, but also cost/volume reduction of the conversion system [8,9,10].

Despite a plethora of multilevel topologies that have been presented, intensive effort has been devoted to introduce promising topologies. For example, ref. [11,12] presented novel MLIs employing the technique of switched-capacitor. Although a substantial reduction in the device count is achieved in these topologies as compared to the conventional ones, they however require H-bridge circuits to generate bipolar voltages. This weakness leads to a sharp increase in total standing voltage (TSV) and thereupon switches cost. A single source nine-level (9 L) inverter has been proposed in [13], which applies semiconductors with the same Peak inverse voltage (PIV) equal to input voltage level. Nevertheless, this topology utilizes numerous insulated-gate bipolar transistors (IGBTs) and gate drivers, which enlarge the system. A hybrid cascaded MLI with improved symmetrical sub-module was introduced in [14]. It employs four dc sources and ten switches with high PIVs to produce a 9 L voltage waveform. Furthermore, [15] introduced a single source inverter which is comprised of an H-bridge inverter and two switched-capacitor modules. It employs sixteen IGBTs with low voltage ratings for generating a 7 L output voltage. Yet, these presented MLIs in the literature suffer from either a large number of circuit elements or relatively high PIVs.

In summary, the main contribution of this paper is the development of a modified 9 L inverter for single phase systems, which is superior to all the earlier topologies. The switches employed in the proposed configuration enjoy low PIVs. At the same time, a further reduction in device count and implementation cost is attained in the proposed circuit compared to the traditional/cutting-edge ones. Moreover, there is no difficulty in the capacitors’ charging process since the inverter is inherently self-balanced. Due to the voltage boosting capability, this inverter is proposed for grid-connected renewable energy sources (such as solar and wind farms), uninterruptible power supplies, and electric vehicles in which low input DC voltages are required to be boosted to an acceptable range for these systems.

The rest of this article is structured into five sections. Following the introduction, Section 2 presents the operating principle and a detailed comparative study of the proposed topology in order to demonstrate the superiority of the proposed inverter against newest 9 L topologies. Section 3 describes PWM strategy applied to the proposed inverter. Efficiency calculations and thermal analysis are carried out in Section 4. The simulation and experimental results are brought in Section 5 in order to prove the feasibility and effectiveness of the presented topology. Eventually, conclusions are presented in Section 6.

2. Analysis of the Proposed Nine-Level Inverter

2.1. Circuit Description

Figure 1 depicts the proposed switched-capacitor based inverter with the potential of generating a 9 L staircase waveform (±2V_IN, ±3V_IN/2, ±V_IN, ±V_IN/2 and 0). As demonstrated in Figure 1, it comprises twelve power switches, two capacitors (C₁, C₂), and only one input DC source with the advantage of regenerative capability. The output voltage can be boosted up to 2V_IN by connecting the input source with pre-charged capacitors in series. It should be underscored that the blocking voltage of all switches employed in the proposed inverter is equal to the input DC source (i.e., V_IN), with the exception of S₇, S_8, and S₁₂ which block only half the V_IN. In other words, it generates a bipolar output voltage without using end-side H-bridge. This ability is considered a beneficial feature of the proposed circuit since the lower switch voltage rating, the cheaper switch.

The working principle of the proposed inverter is illustrated in Figure 2. As can be observed, C₁ and C₂ are charged up to V_IN/2 by turning S₃ and S₄ on during 0 and ±1V_IN levels. Then, the capacitors are connected in parallel at ±V_IN/2 and ±3V_IN/2 levels. Thereby, the voltage across them is balanced. Finally, they are discharged across the load during ±V_IN/2 and ±2V_IN levels. Relying on this simple switching plan, the proposed inverter does not require any external balancer circuit.

2.2. Comparative Assessment

Table 1. Comparison of the proposed topology with other recently presented inverters.

Comparison Item	CHB (Con.)	[11] (2010)	[12] (2017)	[13] (2018)	[14] (2018)	[15] (2018)	Proposed
Level	9	9	9	9	9	7	9	8M * + 1
Switch	16	13	12	19	10	16	12	12M
Capacitor	-	3	4	3	-	2	2	2M
DC source	4	1	1	1	4	1	1	M
N * × PIV	16 × 1VIN	4 × 4VIN 9 × 1VIN	4 × 4VIN 8 × 1VIN	19 × 1VIN	4 × 4VIN 2 × 3VIN 4 × 1VIN	16 × 1VIN	9 × VIN 3 × VIN/2	9M × VIN 3M × VIN/2
TSV	16VIN	25VIN	24VIN	19VIN	26VIN	16VIN	21VIN/2	M × (21VIN/2)

M *: Number of cascaded modules.

compares the presented circuit with other recently-introduced topologies in terms of the number of required semiconductors/DC sources and switches voltage rating. As observed from the table, ref. [14] the proposed circuit employs the least number of switches and capacitors compared to the other ones. These minimizations result in simpler control and a higher degree of compactness. Apart from this, the table depicts a fourfold increase in the number of required DC power supplies for [14] and conventional CHB, while the others and proposed inverter utilize only one DC source.

Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same voltage rating for each structure is presented in the following table. For instance, the proposed 9 L inverter needs nine and three switches with the PIV of 1V_IN and V_IN/2 respectively, while [13] requires nineteen IGBTs with the voltage ratings of V_IN. Thereby, the proposed inverter can be an acceptable alternative to the topologies listed in Table 1.

Furthermore, the single-source topologies are also compared in terms of total implementation cost (see

Table 2. Price Comparison of the Single-Source MLIs.

Part	Part Number	Voltage Rating (V)	Unit Price * (€)	[11]	[12]	[13]	[15]	Proposed
MOSFETs	STW40NF20	200	3.53	9	8	19	-	3
	SUP40N25-60-E3	250	4.43	-	-	-	16	9
	FQL40N50	450	7.73	-	-	-	-	-
	SIHG47N60AEFGE3	600	7.82	4	4	-	-	-
Capacitors	E32D151HPN472TEE3M	150	23.00	3	2	4	-	2
	B43713F2478M000	250	39.39	-	-	-	2	-
	ALS31A472NF350	350	48.83	-	2	-	-	-
Gate driver	IRS21271SPBF	-	1.34	13	12	19	14	12
Total cost (€)				149.47	219.26	184.53	168.42	112.54

* Source: www.mouser.com.

). It should be noted that CHB and [14] are not considered in the cost-comparative analysis since they require four DC power supplies. For a fair comparison, power rating (i.e., volt/ampere rating) of all the MLIs are assumed to be equal to 5 kW/30.7 A. Moreover, a 50% voltage rating margin is considered for the selection of switches and capacitors. It is observed from Table 2 that the proposed inverter requires the least implementation cost compared to the other ones.

3. Multicarrier PWM Strategy

Therein, phase disposition PWM technique is applied to control each IGBT of the proposed topology. To do this, eight triangular carriers (V_t1 to V_t8) arranged with shifts in amplitudes are required (see Figure 3a). It should be noted that they are the same in amplitude (A_t), frequency (f_t) and phase [16,17]. The carriers are compared to a reference waveform (V_ref) which results in generating appropriate fire pulses for all switches. For instance, S₁₁ is turned on when V_ref > V_t1 or V_t2 < V_ref < V_t1 or V_t8 < V_ref < V_t7 or V_ref <V_t8. In other words, S₁₁ must be turned on when S₁: ON, S₄: ON, S₃: OFF (or S₂: ON, S₃: ON, S₄: OFF), which can be observed in Figure 2. Similarly, S₁₂ is turned on when V_ref > V_t1 or V_t3 < V_ref < V_t2 or V_t5 < V_ref < V_t4 or V_t7 < V_ref < V_t6 or V_ref < V_t8. In other words, S₁₂ must be turned on when S₇ and S₈ are OFF (see Figure 2). Further clarification concerning switching strategy is brought up in Figure 3b and

Table 3. On-State IGBTs for Each Level.

Relationship between the Carriers and Vref	ON-State IGBTs	Levels
Vref > Vt1	S1-S4-S5-S10-S11-S12	+4VIN
Vt2 < Vref < Vt1	S1-S4-S5-S7-S8-S10-S11	+3VIN
Vt3 < Vref < Vt2	S1-S3-S4-S5-S6-S10-S12	+2VIN
Vt4 < Vref < Vt3	S1-S3-S5-S7-S8-S10	+1VIN
Vt5 < Vref < Vt4	S2-S3-S4-S5-S6-S10-S12	0
Vt6 < Vref < Vt5	S2-S4-S6-S7-S8-S9	−1VIN
Vt7 < Vref < Vt6	S2-S3-S4-S5-S6-S9-S12	−2VIN
Vt8 < Vref < Vt7	S2-S3-S6-S7-S8-S9-S11	−3VIN
Vref < Vt8	S2-S3-S6-S9-S11-S12	−4VIN

.

4. Loss Distribution and Thermal Modeling

4.1. Power Loss Analysis

The power loss for a multilevel inverter is composed of three parts including P_C, P_S and P_R which are elaborated as follows:

4.1.1. Conduction Loss (P_C)

P_C is caused by parasitic resistance (i.e., ON-state resistance of the switch (R_S) and its parallel diode (R_D), capacitor internal resistance (R_C)) involved in the current paths [18].

Table 4. R_eq in Each Step.

Output Level	Req (Ω)
0	2RS + 2RD = 0.64
±VIN/2	3RS + 2RD + RC = 0.94
±VIN	3RS + RD = 0.86
±3VIN/2	5RS + RD + RC = 1.43
±2VIN	6RS + 2RC = 1.68

shows the equivalent value of the parasitic resistance (R_eq) existing in each voltage level. It should be noted that in the present work R_S, R_D, and R_C are considered equal to 0.27 Ω, 0.05 Ω, and 0.03 Ω, respectively.

If |V_ref| < A_t, the output voltage switches between 0 and +V_IN/2 (see Figure 3a). Consequently, the output current passes through two switches and two diodes (three switches, two diodes, and one capacitor) during 0 (+V_IN/2) level, as depicted in Table 4. In this case, the energy dissipated within 0 < t < t₁ (t₆ < t < t₇ or t₁₂ < t < 2π) is attained by Equation (1) in which A_t, A_ref, and f_ref are considered equal to 0.25, 0.9, and 50 Hz, respectively [18]. Moreover, t₁ is calculated as follows:

$$\begin{array}{c}{E}_{0\&V_{IN}/2}={{\displaystyle \underset{0}{\overset{t_1}{\int }}\left[I_{Load}sin\left(2\pi f_{ref}t\right)\right]}}^2\times [\left(3R_S+2R_D+R_C\right)\frac{A_{ref}sin\left(2\pi f_{ref}t\right)}{A_t}+\left(2R_S+2R_D\right)\left(1-\frac{A_{ref}sin\left(2\pi f_{ref}t\right)}{A_t}\right)]dt=2.04\times {10}^{-5}\times {\left(\raisebox{1ex}{$P_{out}$}\!\left/ \!\raisebox{-1ex}{$V_{IN}$}\right.\right)}^2\end{array}$$

(1)

$$t_1=\frac{{sin}^{-1}\left(\raisebox{1ex}{$A_t$}\!\left/ \!\raisebox{-1ex}{$A_{ref}$}\right.\right)}{2\pi f_{ref}}=\frac{{sin}^{-1}\left(\raisebox{1ex}{$0.25$}\!\left/ \!\raisebox{-1ex}{$0.9$}\right.\right)}{100\pi }=9\times {10}^{-4}sec.$$

(2)

Similarly, the energy losses that occurred in other time intervals are calculated by Equations (3)–(8).

$$\begin{array}{c}{E}_{V_{IN}/2\hspace{0.17em}\&V_{IN}}={{\displaystyle \underset{t_1}{\overset{t_2}{\int }}\left[I_{Load}sin\left(2\pi f_{ref}t\right)\right]}}^2\times [\left(3R_S+R_D\right)\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-A_t}{A_t}+\left(3R_S+2R_D+R_C\right)\left(1-\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-A_t}{A_t}\right)]dt=2.03\times {10}^{-4}\times {\left(\raisebox{1ex}{$P_{out}$}\!\left/ \!\raisebox{-1ex}{$V_{IN}$}\right.\right)}^2\end{array}$$

(3)

$$t_2=\frac{{sin}^{-1}\left(\raisebox{1ex}{$2A_t$}\!\left/ \!\raisebox{-1ex}{$A_{ref}$}\right.\right)}{2\pi f_{ref}}=\frac{{sin}^{-1}\left(\raisebox{1ex}{$0.5$}\!\left/ \!\raisebox{-1ex}{$0.9$}\right.\right)}{100\pi }=1.87\times {10}^{-3}sec.$$

(4)

$$\begin{array}{c}{E}_{V_{IN}\hspace{0.17em}\&3V_{IN}/2}={{\displaystyle \underset{t_2}{\overset{t_3}{\int }}\left[I_{Load}sin\left(2\pi f_{ref}t\right)\right]}}^2\times [\left(5R_S+R_D+R_C\right)\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-2A_t}{A_t}+\left(3R_S+R_D\right)\left(1-\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-2A_t}{A_t}\right)]dt=7.2\times {10}^{-4}\times {\left(\raisebox{1ex}{$P_{out}$}\!\left/ \!\raisebox{-1ex}{$V_{IN}$}\right.\right)}^2\end{array}$$

(5)

$$t_3=\frac{{sin}^{-1}\left(\raisebox{1ex}{$3A_t$}\!\left/ \!\raisebox{-1ex}{$A_{ref}$}\right.\right)}{2\pi f_{ref}}=\frac{{sin}^{-1}\left(\raisebox{1ex}{$0.75$}\!\left/ \!\raisebox{-1ex}{$0.9$}\right.\right)}{100\pi }=3.1\times {10}^{-3}sec.$$

(6)

$$\begin{array}{c}{E}_{3V_{IN}/2\hspace{0.17em}\&2V_{IN}}={{\displaystyle \underset{t_3}{\overset{t_4}{\int }}\left[I_{Load}sin\left(2\pi f_{ref}t\right)\right]}}^2\times [\left(6R_S+2R_C\right)\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-3A_t}{A_t}+\left(5R_S+R_D+R_C\right)\left(1-\frac{A_{ref}sin\left(2\pi f_{ref}t\right)-3A_t}{A_t}\right)]dt\\ =0.0051\times {\left(\raisebox{1ex}{$P_{out}$}\!\left/ \!\raisebox{-1ex}{$V_{IN}$}\right.\right)}^2\end{array}$$

(7)

$$t_4=\frac{\pi -{sin}^{-1}\left(\raisebox{1ex}{$3A_t$}\!\left/ \!\raisebox{-1ex}{$A_{ref}$}\right.\right)}{2\pi f_{ref}}=\frac{\pi -{sin}^{-1}\left(\raisebox{1ex}{$0.75$}\!\left/ \!\raisebox{-1ex}{$0.9$}\right.\right)}{100\pi }=6.86\times {10}^{-3}sec.$$

(8)

Due to quarter-wave symmetry of the output voltage, the total conduction loss for the proposed 9 L topology is:

$$P_C=(4E_{0\hspace{0.17em}\&V_{IN}/2}+4E_{V_{IN}/2\hspace{0.17em}\&V_{IN}}+4E_{V_{IN}\hspace{0.17em}\&3V_{IN}/2}+2E_{3V_{IN}/2\hspace{0.17em}\&2V_{IN}})\times f_{ref}=0.69\times {\left(\raisebox{1ex}{$P_{out}$}\!\left/ \!\raisebox{-1ex}{$V_{IN}$}\right.\right)}^2$$

(9)

4.1.2. Switching Loss (P_S)

The overlap of switch voltage and current during rise and fall times (i.e., t_on and t_off) leads to P_S, which is highly proportional to the f_S. The turn-on and turn-off power loss of the switch S are attained by [19]:

$$P_{S,\hspace{0.17em}on}=f_S{\displaystyle \underset{0}{\overset{t_{on}}{\int }}{v}_S(t)}\hspace{0.17em}{i}_S(s)\hspace{0.17em}dt=f_S{\displaystyle \underset{0}{\overset{t_{on}}{\int }}\left(\frac{V_S}{t_{on}}t\right)\left(-\frac{I_S^{on}}{t_{on}}\left(t-t_{on}\right)\right)\hspace{0.17em}dt=\frac{1}{6}{f}_S{V}_S{I}_S^{on}{t}_{on}}$$

(10)

$$P_{S,off}=f_S{\displaystyle \underset{0}{\overset{t_{off}}{\int }}{v}_S(t)}\hspace{0.17em}{i}_S(t)\hspace{0.17em}dt=f_S{\displaystyle \underset{0}{\overset{t_{off}}{\int }}\left(\frac{V_S}{t_{off}}t\right)\left(-\frac{I_S^{off}}{t_{off}}\left(t-t_{off}\right)\right)\hspace{0.17em}dt=\frac{1}{6}{f}_S{V}_S{I}_S^{off}{t}_{off}}$$

(11)

In which I_S^on (I_S^off) is the switch current after (before) turning on (off). Considering t_on = t_off = 58 ns and f_t = 4 kHz, P_S for all the switches is obtained as follows:

$$P_{Sj,on}=P_{Sj,off}=\frac{1}{6}\times \frac{1}{2}\times 4\times {10}^3\times V_{IN}\times \frac{I_{Load}}{\pi }\times 58\times {10}^{-9}=6.15\times {10}^{-6}\times P_{out},j=1,\hspace{0.17em}2,\hspace{0.17em}9,\hspace{0.17em}10,\hspace{0.17em}11$$

(12)

$$P_{Sj,on}=P_{Sj,off}=\frac{1}{6}\times 4\times {10}^3\times V_{IN}\times \frac{I_{Load}}{\pi }\times 58\times {10}^{-9}=12.3\times {10}^{-6}\times P_{out},j=3,\hspace{0.17em}4,\hspace{0.17em}5,\hspace{0.17em}6$$

(13)

$$P_{Sj,on}=P_{Sj,off}=\frac{1}{6}\times \frac{1}{2}\times 4\times {10}^3\times \frac{V_{IN}}{2}\times \frac{I_{Load}}{\pi }\times 58\times {10}^{-9}=3.07\times {10}^{-6}\times P_{out},j=7,\hspace{0.17em}8$$

(14)

$$P_{S12,on}=P_{S12,off}=\frac{1}{6}\times \frac{1}{2}\times 4\times {10}^3\times \frac{V_{IN}}{2}\times \frac{I_{Load}}{\pi }\times 58\times {10}^{-9}=3.07\times {10}^{-6}\times P_{out}$$

(15)

Consequently, the total switching loss for the presented 9 L inverter is calculated by:

$$P_S={\displaystyle \sum _{j=1}^{N_{switch}}\left(P_{Sj,\hspace{0.17em}ON}+P_{Sj\hspace{0.17em},OFF}\right)}=178\times {10}^{-6}\times P_{out}$$

(16)

4.1.3. Power Loss Generated by Capacitor Voltage Ripple (P_R)

PP_R is due to the voltage difference between the capacitor and input DC source during the charging periods. Generally, the maximum discharging value of each capacitor in a switched-capacitor circuit is attained by [13,18]:

$$\Delta Q_C={\displaystyle \underset{t_c}{\overset{t_d}{\int }}{I}_{Load}Sin(2\pi f_{ref}t)dt}$$

(17)

where [t_c, t_d] is the discharging interval of each capacitor. According to Figure 2a and Figure 3a, the maximum discharging period of C₁ (or C₂) is equal to [t₃, t₄]. Thus, considering maximum acceptable voltage drop across C₁ (or C₂) equal to ΔV_ripple, the capacitance of each capacitor is calculated by [13,18]:

$$C\ge \frac{\Delta Q_C}{\Delta V_{ripple}\times 0.5V_{IN}}$$

(18)

For example, considering P_out = 1.4 kW (I_Load = 7 A, V_IN=200 V) and ΔV_ripple = 10%, the capacitances for the proposed inverter are obtained as follows:

$$C_1=C_2=\frac{{\displaystyle \underset{0.0031}{\overset{0.00686}{\int }}7\times Sin(100\pi t)dt}}{0.1\times 100}=\frac{0.024}{10}=2400\hspace{0.17em}\mu F$$

(19)

It also should be noted that nominal voltage of the capacitors is equal to V_IN/2 (see Figure 2). Consequently, P_R for the proposed topology is attained as follows:

$$P_R=\raisebox{1ex}{$f_{ref}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.\left({\displaystyle \sum _{i=1}^2{C}_i{\left(\Delta V_{ripple}\times 0.5V_{IN}\right)}^2}\right)=50\times \left({\displaystyle \underset{0.0031}{\overset{0.00686}{\int }}{I}_{Load}sin(100\pi t)}\hspace{0.17em}dt\times \Delta V_{ripple}\times 0.5V_{IN}\right)=0.088\times \Delta V_{ripple}\times P_{out}$$

(20)

Therefore, considering Equations (9), (16), and (20), the efficiency is calculated by Equation (21).

$$\eta =\frac{P_{out}}{P_{in}}=\frac{P_{out}}{P_{out}+P_C+P_S+P_R}$$

(21)

Theoretical efficiency of the proposed inverter has been calculated at different output power and presented in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the output power.

4.2. Thermal Model

Heat distribution through semiconductor components is caused by power loss, which leads to an increasing of T_j [20]. This temperature, for safety reasons, should be monitored and kept within a specified range during the inverter operation. Figure 5a illustrates the thermal model implemented for a single semiconductor, in which the thermal impedance between junction and case (Z_th) is considered a four-layer foster network (see Figure 5b) [21,22]. It should be noted that Z_c and Z_s are the thermal impedances from the case to the heat sink and from the heat sink to the ambient, respectively. These are found on the manufacturer datasheet.

Modelling loss dissipation of the proposed 9 L inverter in MATLAB/Simulink yields the junction temperature of the power electronic devices [23,24,25]. Herein, T_a is considered equal to 40 °C and the PM75CLA060 switch produced by Mitsubishi Electric is chosen in the thermal estimation.

The estimated T_j of some power switches employed in the proposed inverter at 20 kW output power is illustrated in Figure 6. It can be observed that S₁₂ has the lowest T_j (approximately 43.9 °C), while this temperature approaches 46.7 °C for S₁₁.

5. Simulation and Experimental Results

Simulations have been conducted in MATLAB for steady-state and transient modes, as presented below. Figure 7 shows the inverter output voltage/current and capacitors voltage at resistive-inductive load (f_t = 4 kHz, C₁ = C₂ = 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V, respectively. The proposed topology has also been simulated under step change in the load, and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify the inherent capacitor voltage balancing ability during inverter operation.

Figure 9 shows the voltage waveforms across some power switches employed in the proposed topology. It is clear that S₃, S_5, and S₁₁ (also S₁, S₂, S₄, S₆, S₉ and S₁₀) must withstand voltages equal to the input DC source (i.e., 200 V). Other switches (S₇, S₈ and S₁₂), however, block voltages equal to half the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).

Furthermore, the effect of different modulation indexes and switching frequencies on the operation of the proposed inverter is shown in Figure 10. It is observed that the inverter output voltage has lower THD at higher modulation index (and higher switching frequency). Moreover, the fundamental component of output voltage is decreased at lower modulation index.

To validate the high performance of the proposed model, a low-power prototype of the proposed inverter has been implemented and tested. Accordingly, a Texas Instruments (TMS320F28335) fixed-point DSP control board generated gate pulses for employed switches (IRFP460 500 V/20 A). Moreover, the value of capacitances and input DC source are selected at 2300 µF and 140 V, respectively. Figure 11 illustrates the results obtained from the hardware implementation of the proposed inverter model under steady-state and transient operating conditions. These figures fully confirm the flawless performance of the proposed inverter.

6. Conclusions

Herein, the operating principle of a new 9 L inverter has been discussed and confirmed experimentally. The comparative analysis depicted that the presented topology not only reduces the number of semiconductors/DC links required for generating a 9 L voltage waveform, but also employs IGBTs with lower PIV. These merits lead to a high compactness and cost reduction of the conversion system. Due to the intrinsic self-voltage balancing ability, there is no need for complex modulation methods. Thereupon, it enjoys simple control and implementation. Furthermore, the theoretical efficiency demonstrated that the presented configuration has higher efficiency by increasing output power (up to 2000 W). Eventually, the feasibility and effectiveness of the proposed model was verified by the simulation and experimental results.