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Energies 2018, 11(10), 2618; doi:10.3390/en11102618

Article
A Bilateral Zero-Voltage Switching Bidirectional DC-DC Converter with Low Switching Noise
1
Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei 10607, Taiwan
2
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan
*
Author to whom correspondence should be addressed.
Received: 22 August 2018 / Accepted: 26 September 2018 / Published: 1 October 2018

Abstract

:
This paper proposes a novel bilateral zero-voltage switching (ZVS) bidirectional converter with synchronous rectification. By controlling the direction and timing of excessive current injection, the main power switches can achieve bilateral ZVS under various loads and output voltages. Compared with the common soft-switching power converter with only zero-voltage turn-on, the proposed bilateral ZVS bidirectional converter can achieve both zero-voltage switching on and off in every switching cycle. This feature can alleviate the output switching noise due to the controlled rising and falling slope of the switch voltage. Furthermore, the voltage slopes almost remain unchanged over a wide range of output voltages and load levels. The most important feature of bilateral ZVS is to reduce the output switching noise. Experimental results based on a 1 kW prototype are presented to demonstrate the performance of the proposed converter. From experimental results on the proposed scheme, the switching noise reduction is about 75%.
Keywords:
switching noise; zero-voltage switching; bidirectional converter

1. Introduction

With the increasingly stringent requirements on the output quality of instrument power supplies, the switching noise imposed on the output voltage should be minimized. Conventional linear regulators have excellent performance in terms of the noise concern, but cannot handle high power due to efficiency problems and the inability to process bidirectional power flow. Switching power converters, on the contrary, are capable of improving efficiency at high power outputs; the switching actions induce switching noise on the output and degrade the power quality of the load. The high-frequency switching noise usually ranges over a few hundred kHz to several MHz. The voltage perturbation is illustrated as in Figure 1.
There are two factors influencing the switching noise in a switching power supply: one is the non-ideal characteristic of the output filter, and the other is the high-frequency component spectra of the voltage waveform injecting into the filter. Firstly, dealing with the non-ideal characteristics of the filter, take a buck converter as an example. The output inductor and capacitor are not only used to store energy, but also behave as a filter to reduce the output ripple. An ideal LC low-pass filter, as shown in Figure 2a, can completely filter out the high-frequency component well above the designed cut-off frequency. However, practical inductors and capacitors contain parasitic elements. The parasitic elements in an inductor contains the capacitance between the windings as well as between the winding conductor and the core, denoted as lumped capacitance, Cp. In addition, there is winding equivalent resistance, Rs, as shown in Figure 2b. As for the capacitor counterpart, it contains the equivalent series inductance, Lc, and equivalent series resistance, Rc. These parasitic elements alter the transfer function of the filter and deteriorate the capability to filter out high frequency signals. Figure 3 shows the bode plots of ideal, semi-ideal and non-ideal filters. The component parameters used in the figure are as follows: Lo = 42 μH, Rs = 0 Ω, Cp = 10 pF, Co = 1.36 mF, Rc = 1 mΩ, Lc = 6 μH, Ro = 10 Ω. Where Co is the filter capacitor, Lo is the filter inductor, Ro is the load resistor, vIN is the input voltage, and vo is the output voltage. The semi-ideal filter only considers the capacitor’s equivalent series resistance (ESR), the extra zero brings about +20 dB/dec; on the other hand, the non-ideal filter considers all the parasitic components; even a +40 dB/dec slope is present at extremely high-frequency regions. In other words, the high-frequency components of the input signal will be detected at the output terminals.
Clearly, it is very difficult to reduce the parasitic components on the filter; practically, it is impossible to eradicate them. Elsewise, in order to counteract the high-frequency current generated by the parasitic capacitance on the inductor, the literature [1] proposes an external circuit. The inductor is connected in parallel to a transformer or a secondary side winding, and a compensating capacitor is connected in series to the secondary side. By adjusting the transformer turns ratio to produce an appropriate compensating current, the transient current evoked from the parasitic capacitance is neutralized. Although the method claims limited extra circuitry components or volume/weight required to depress the switching noise, its performance will be seriously impaired due to the inevitable leakage inductance accompanying the additionally coupled winding, which is not accounted for in the theory. Another paper [2] proposed a different improved compensation circuit to reduce the effect of leakage inductance. In this external circuit, the compensation capacitor is connected to both sides of the extra coupled inductor, and the effect of leakage inductance will be greatly reduced. For both of the above methods, an accurate inductor parasitic capacitance value is indispensable. However, this itself is a difficult task. Many researchers endeavor to construct inductor parasitic capacitance models and several parameter assignments have been proposed [1,2,3], even though the thickness, pitch or tightness deviation of the winding under realistic industrial mass production will affect the parasitic capacitance. Neither way is appropriate to reliably compensate for all the products under mass production.
On the other hand, elimination of parasitic inductance on the output capacitor is another remedy for reducing the high-frequency voltage noise. Reference [3] proposes a technique for eliminating the capacitor’s equivalent series inductance (ESL) and ESR.
As shown in Figure 4, the two non-ideal capacitors are connected in diagonal form. From circuit theorem, if the compensation impedance Z1 is equal to that of ESL and ESR, there is an equivalent pure capacitance located in the middle point. For high-frequency signals, the inductor exhibits high impedance while the capacitor exhibits low impedance. Therefore, the high-frequency noise can no longer pass through to the output. Although the compensation impedance Z1 in this method is of limited value and can be implemented by using printed circuit board (PCB) trace, the internal parasitic elements inside capacitors are divergent due to several reasons. Therefore, there are still many difficulties to solve before mass production is possible. Nevertheless, the tolerance allowed for this method is wider than the compensation of inductor parasitic capacitance methods.
Since the elimination of parasitic components in a filter circuit is very difficult, the remnant prescription is to reduce the voltage transient across the inductor. The commonly developed ZVS techniques indeed reduce the voltage transient since the inductor voltage transits over a longer commutation time as the switch voltage falls to zero. This simple idea just launches a much wider possibility for switching noise alleviation.
A synchronous rectified step-down converter operated in the triangular-current mode (TCM) [4,5,6] is a common way to achieve ZVS without introduction of auxiliary resonant components. For TCM operation, the inductor current is usually designed to operate in boundary conduction mode (BCM) at full load; therefore, TCM can be assured under the entire load range. However, this means that the inductance should be small so that the peak inductor current doubles the output current at full load. This seriously impairs the converter efficiency, especially at light load.
There are many proposed ZVT converters with auxiliary switches or resonant circuitry to achieve ZVS benefits [7,8,9,10,11]. However, the ZVS feature cannot be maintained within the overall load and voltage range. In recent years, the literature [12,13,14,15] lists many novel bidirectional converters applying various methods to achieve soft switching. However, most of them suffer from the range limitation of ZVS, i.e., ZVS is only achievable within a small range of load level, or even output voltage in some applications. A method proposed in [16] is capable of retaining ZVS switching at any load and wide output voltage range while reducing the switching losses of the auxiliary switch by a coupled inductor. However, from the detailed discussion in the next section, it is clear that the output switching noise could be further reduced if soft switching of switching-off is considered. Unfortunately, the aforementioned papers only focus on ZVS turn-on; i.e., those methods only alleviate the rising slope of the filter input voltage, but without solving the sharp noise of the falling edge. In this paper, a new circuit architecture is proposed to achieve bilateral ZVS over a wide load range and wide output voltage. This architecture can reduce the output switching noise by controlling the resonant capacitor to simultaneously adjust the rise and fall slope of the voltage across the main switch. The voltage change rate of these is the same and does not change with the output voltage and the output current. It is not necessary to detect the voltage signal to determine the opening timing of the main switch, which is beneficial to the application of high-frequency switching. This architecture is especially suitable for instrument power which characterizes the low switching noise trait over wide load/voltage range.
The remaining arrangement of this paper is as follows: Section 2 discusses the Fourier analysis of the filter’s input voltage. Section 3 shows the structure and operation principle of the proposed circuit. Detailed analyses of the circuit and the requirement for ZVS are described in Section 4. Section 5 is about the design consideration and equations of this architecture. Section 6 presents the simulation and measured results to verify the correctness and feasibility. Finally, the conclusion follows.

2. Fourier Analysis on Filter Input Voltage Waveforms

As for the discussion on the influence of frequency spectra of the input voltage waveform, take a buck converter as an example again. Ideally, the voltage at the LC filter’s input port is a rectangular waveform. From the definition of the Fourier series, the Fourier series expansion of a rectangular waveform, frect(t) is:
f r e c t ( t ) = V i n D + 1 C n , r e c t cos ( 2 π n t T s )
where
C n , r e c t = 2 V i n sin ( n π D ) n π  
Practically, there is always a small rise/fall time in the waveform. To simplify the analysis, let us assume an identical rise and fall time, tr/tf. Then we have a trapezoidal waveform. By dissecting the waveform into a rectangle and two triangles, the Fourier series expansion of a trapezoidal waveform, ftrap(t) is:
f t r a p ( t ) = C 0 + 1 2 | C n | cos ( n ω s t + C n )
where
C 0 = 1 T s D T s / 2 t r / 2 T s D T s / 2 t r / 2 f t r a p ( t ) d t
C n = 1 T s D T s / 2 t r / 2 T s D T s / 2 t r / 2 f t r a p ( t ) e j n ω s t d t
ω s = 2 π T s
Figure 5 is the Fourier spectrum of a rectangular and two trapezoidal waveforms. “Rect. Wave” represents a rectangular waveform, “Trap. Wave-1” represents a trapezoidal waveform of tr = tf = 500 ns, and “Trap. Wave-2” represents a trapezoidal wave of tr = 500 ns, tf = 50 ns. The amplitudes of the three waveforms are all 300 V, the equivalent duty ratio is 0.2, and the switching frequency is 200 kHz. The rectangular wave’s spectrum turning point is the switching frequency. After the switching frequency, the maximum value of each harmonic decreases with a slope of −20 dB/dec. However, there are two turning points in the trapezoidal waveform’s spectrum: one is the switching frequency fs, and the other is fr*, which is the control by the trapezoidal wave. Beyond the fr frequency ( f r * = 1 / π t r t f ), the maximum value of each harmonic decreases with a slope of −40 dB/dec. If the slope of the rising and falling of a trapezoidal wave can be properly designed, the high frequency component will be rapidly attenuated after a suitable frequency. Even with non-ideal LC filters, the high-frequency components of the output voltage can still be properly attenuated.
From the time-domain analysis, slowing down the voltage variation slope also reduces the instantaneous charging current iCp of the parasitic capacitance Cp of the non-ideal LC filter in Figure 2b. Figure 6 shows the simulation results for the three kinds of input voltage waveforms used in Figure 5 fed into the non-ideal LC filter respectively. The results show that the rectangular waveform generates the maximum switching noise in both root mean square (rms) and peak–peak values. A trapezoidal waveform with alleviated rising slope did prove attenuated switching noise; however, high switching noise was still present due to the steep falling edge. The bilateral trapezoidal one that slows down both the rising and falling slopes has the smallest switching noise.

3. Circuit Topology and Operation Principle

Figure 7 shows the proposed bilateral ZVS synchronous rectified step-down converter. The main switches Qsr1 and Qsr2 cooperate with the output inductor Lo and the output capacitor Co to form a conventional synchronous rectified step-down converter. In order for the high-side switch to achieve ZVS, CossQsr1 must be completely discharged before Qsr1 is turned on. To achieve this purpose, a resonant inductor Lr is added to supply the discharging current at suitable timing. The bidirectional switch Qaux is turned on shortly before the turn-off of Qsr1/Qsr2, and is turned off after Qsr1/Qsr2 is turned on. The turn-on of Qaux will create a charging path for Lr to generate the current required for ZVS operation. CossD1/CossD2 represents the sum of the applied capacitance of the diode D1/D2 and its own parasitic capacitance. Cr1 is the sum of CossD1 and CossQsr1, and Cr2 is the sum of CossD2 and CossQsr2. CossD1 and CossD2 are much larger than the parasitic output capacitance of Qsr1, Qsr2, Q1 and Q2. By adjusting Cr1, Cr2 and the resonant inductor Lr, the voltage transition rate across the switches, Qsr1 and Qsr2, as well as the resonant current magnitude can be adjusted.
This architecture can be a bidirectional topology that uses the same switching signal to achieve natural commutation, and forward and reverse operation has similar behavior. This paper gives a detailed explanation of the forward operation, and the reverse part is presented with an action timing diagram. The complete circuit operation can be divided into 10 intervals as described later. The theoretical waveforms of forward mode are depicted in Figure 8, while the corresponding circuit operation diagrams are illustrated in Figure 9. Due to the length limitation, this paper does not elaborate on the action intervals of the reverse power flow operation. A timing diagram, Figure 10, is attached to illustrate the reverse power flow operation as a reference. For the convenience of analysis, the resonant capacitors Cr1 and Cr2 are assumed to be identical, i.e., Cr1 = Cr2 = Cr.
Interval 1 (t0t1): Before t0, switches Q2 and Qsr2 are conducting. The output inductor current keeps flowing through Qsr2, and the resonant current iLr freewheels through D2. Therefore, the voltage across Qaux is zero, and vGS_Qaux can be pulled high at t0 to turn on Qaux at zero voltage. Shortly following the turn-on of Qaux, Q2 is turned off. After Q2 is turned off, the resonant current detours to the body diode of Q1. Since the voltage across the resonant inductor is Vin, the resonant inductor current rises linearly. Q1 can be turned on during this interval to achieve ZVS.
Interval 2 (t1–t2): At t1, iLr is equal to the output inductor current iL, such that both the body diode of Qsr2 and diode D2 turn off. Since voltage vDS_Qsr2 is no longer clamped at zero, resonant inductor Lr begins to resonate with Cr1 and Cr2. The resonance continues until vDS_Qsr1 drops to zero.
Interval 3 (t2–t3): At t2, both the body diode of Qsr1 and diode D1 are forward biased. The resonant inductor is then short-circuited since Q1 also conducts. Because of the zero voltage across Qsr1, it is ready for ZVS. Herein, iLr just freewheels during this interval, while the resonant inductor current continues to circulate in this interval. The power is passed from the input source to the output, and the output inductor current rises linearly.
Interval 4 (t3–t4): At t3, switch Qaux cuts off. Since the voltage across switch Qaux is still kept at zero after the cutoff, the turn-off loss is trivial. Although it seems unnecessary to turn off Qaux during this operation interval, in order to ease the gating signal generation for future bidirectional operations and natural commutation characteristics, the gating sequence is set to be the current form.
Interval 5 (t4–t5): At t4, Qaux is re-conducted. Again, Qaux turns on at zero voltage and with ignorable switching loss. Immediately after the turn-off of Qaux, switch Q1 is turned off, and the resonant current iLr begins to discharge CossQ2.
Interval 6 (t5–t6): Since the voltage on the CossQ2 resonates to zero, finally the body diode of Q2 is forward biased. Thereafter, the voltage across Lr is −Vin, and the current through it rapidly drops linearly. Meanwhile, switch Q2 can be turned on during this interval to reach ZVS.
Interval 7 (t6–t7): The resonant current is equal to the output current at t6, and the body diode of Qsr1 and diode D1 are reverse-biased. Due to the reverse-recovery of the diodes, iLr will drop too much and be less than iL, which forces Cr1 to get charged and Cr2 discharged to compensate for the current difference.
Interval 8 (t7–t8): At t7, the voltage on Cr2 drops to zero and forward-biases the body diode of Qsr2 and diode D2. Again, voltage across Lr is zero and iLr flows constantly. Since the body diode of the switch Qsr2 is already forward-biased, Qsr2 can readily reach ZVS during this interval.
Interval 9 (t8–t9): At t8, switch Qaux is turned off; accordingly, iLr discharges Cr1 and charges Cr2. The voltage across Cr1 finally drops to zero and forward biases diode D1. However, since the voltage applies on Lr negatively, iLr declines linearly.
Interval 10 (t9–t10): At t = t9, diode D1 naturally turns off because the resonant inductor current is zero. Similarly, due to reverse-recovery, the overshoot current triggers the resonant oscillation between Cr1, Cr2 and Lr. At t10, vDS_Q2 drops to zero, and resonant current freewheels between Q2 and D2.

4. Circuit Analysis

For the simplicity of analysis, some assumptions are made as follows:
  • Because the switch Qaux is a series of two switches, its overall parasitic capacitance is much smaller than Cr and CossD. The switch’s parasitic capacitance is omitted to simplify the analysis.
  • Since the focus of this paper is on the input waveform improvement, parasitic capacitance or inductance of the output filter is not discussed.
  • The on-resistance of the switch and the impedance on the trace are not considered.

4.1. ZVS on Main Switches at Wide Load Range

The ZVS energy requirement over full-load current range can be satisfied by designing the resonant inductor. Figure 11 shows the equivalent circuit of the resonant period (t1–t2). At t1, the initial condition of the circuit is: iLr (t1) = iL and vCr2 (t1) = 0.
The capacitor voltage vCr2 can be obtained as:
v C r 2 = ( L r V o + L o V i n ) ( 1 cos ω C r t ) L o + L r
where ω C r = L o + L r 2 C r L o L r .
To meet ZVS energy requirements over the complete load current range, without considering the diode clamping effect, the peak voltage of vCr2 needs to be higher than Vin to satisfy ZVS at t = π / ω C r . Thus:
2 ( L r V o + L o V i n ) L o + L r V i n
Equation (9) can be derived from (8); in addition, a wide range of output voltage is considered:
L r L o V i n V i n 2 V o max
From the equations, the conditions for achieving ZVS depend on the design of Lr and Lo, regardless of the output load. So, this circuit can be ZVS from no load to full load.

4.2. Robust Control

In the literature [16,17], the ZVS timing requirement is satisfied over the full load range by using the variable zero-voltage detection timing control. Zero-voltage detection timing is influenced by signal detection and signal synthesis time. Therefore, not only is the switching frequency of the application limited, but the detection circuit is also susceptible to the switching noise and diminishes the reliability of the control.
For the operation proposed in this paper, once the body diode of switch Qsr1 is forward-biased, the resonant inductor current passes through the body diode of Qsr1 as during (t1t3) in Figure 8. Due to the conduction of Q1, the voltage drop in this circulation loop consists only of the conduction voltages of the diode and Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET); basically, the resonant inductor current, iLr, changes quite little. In other words, the ZVS turn-on window for Qsr1 is generously wide. This feature allows Qsr1 to turn on at a fixed timing without employing any detection circuitry, making the control simpler and more robust.

4.3. ZVS on All Switches

Ideally, the hard-switching happening on the auxiliary switches Q1 and Q2 would not interfere with the output voltage at all. However, in the real-circuit operation, additional switching noise induced by the hard-switching of Q1 and Q2 is observed. In that case, additional snubber circuitry must be added to suppress the voltage noise. This deployment, however, increases unnecessary loss. In this paper, Q1 and Q2 can also achieve ZVS under certain load conditions as illustrated during (t0–t1) and (t5–t6) in Figure 8, which further reduces the switching noise.
Referring to Figure 8, we can observe that there are two platforms on the resonant inductor current, i.e., ILr_PP and ILr_NP. The value of ILr_PP is (IL_Max i L r ), where IL_Max is the peak value of the output inductor current, and Δ i L r is the amplitude of the resonant inductor current designed by us. In other words, the value of ILr_PP will change with the load current. The value of ILr_PP results in two different operation cases, which in turn affects the value of ILr_NP, since ILr_NP is closely related to the ZVS of Q1. It turns out that the value of ILr_NP directly determines whether Q1 can reach ZVS.
For the first case, ILr_PP ILr_D1_ON, where ILr_D1_ON is the critical current that would forward-bias D1, and it can be expressed as:
I L r _ D 1 _ O N = V i n 2 C o s s D L r
While ILr_PP is greater than ILr_D1_ON, D1 turns on and then asserts −Vin across Lr, forcing iLr to linearly decline to zero. Afterwards, iLr flows reversely via D2. Finally, iLr completely discharges CossD2 and is locked to −ILr_NP. The value of ILr_NP is converted into the form of inductor current by the energy stored on CossD2. Since CossD1 and CossD2 have equal capacitance and are equivalently paralleled together as before, the value of ILr_NP, in this case, is equivalent to ILr_D1_ON. In other words, ILr_NP has a constant negative value and does not change with load.
From the time interval (t1–t2), the minimum resonant inductor current value −ILr_ Q1_ZV required for zero-voltage switching of the Q1 switch can be derived. Its value can be expressed by the following formula:
I L r _ Q 1 _ Z V = V i n 2 C o s s Q L r
Because CossD is greater than CossQ, according to Equations (10) and (11), ILr_D1_ON is larger than ILr_Q1_ZV. When ILr_PP is greater than ILr_D1_ON, ILr_NP is fixed to −ILr_D1_ON, so we can see that when ILr_PP is greater than ILr_D1_ON, all the switches in the converter can achieve ZVS.
For the second case ILr_PP ILr_D1_ON, iLr is insufficient to forward-bias D1 during the interval (t9–t10). In this case, the value of ILr_NP will be equal to ILr_PP, and the ZVS achievement depends on the value of ILr_NP. If ILr_NP ILr_Q1_ZV, all switches in this converter still work with zero-voltage switching.

5. Design Considerations

For the main switch to achieve ZVS, the maximum inductance for Lr is given in Equation (9). However, besides satisfying Equation (9), dead time between switches Qsr1 and Qsr2 should also be considered. Figure 12 is a magnified timing diagram to narrate the switching operation. As seen in the figure, there are three main parts within the dead time zone. They are distinguished according to the value of iLr. Among them, only tB is directly affected by the resonant inductor. After determining tB, the resonant inductor Lr is designed according to Equation (9).
The resonant capacitance affecting the ZVS of the main switches Qsr1 and Qsr2 includes two parts, CossQsr and CossD; their sum is defined as Cr in previous section. There are two criteria to be considered on design of Cr: the change rate of vDS_Qsr2 and the overshoot ∆iLr.
From Equation (7), the time required for vDS_Qsr2 to rise from zero to Vin, defined as tC in Figure 12, can be deduced. tC can be expressed as the following equation:
t C = 2 cos 1 [ 1 V i n ( L o + L r ) L o V o + L o V i n ] L o + L r C r L o L r
To keep a suitable voltage stress and elapsed time, we first determine the time required for tC, which is, say tC_design. tC_design is then used to calculate the desired value of Cr. The design rule of Cr can be deduced by Equation (13):
C r = t C _ d e s i g n ( L o + L r ) 2 L o L r cos 1 [ 1 V i n ( L o + L r ) L r V o + L o V i n ] 2
The value of Cr concurrently affects the overshoot of iLr. The overshoot ∆iLr is depicted as follows:
Δ i L r = 2 C r L o L o + L r C r L o L r ( L o + L r ) 2 { L r ( V i n V o ) cos 1 ( L r V o L r V i n L r V o + L o V i n )   ( L r V o + L o V i n ) V i n ( L o + L r ) [ 2 L r V o + V i n ( L o L r ) ] ( L r V o + L o V i n ) 2 }
Since the overshoot of iLr must be greater than the ripple of the output inductor current, the voltage vDS_Qsr2 can be slowly reduced from Vin to zero volts when the Qsr1 switch is turned off. Consider the forward bias VF of the circulating current diode D1. The minimum value of the ∆iLr to make sure the end value of iLr is larger than iL when Q1 cuts off in the worst case scenario is:
Δ i L r _ M i n = Δ i L _ M a x + D Δ i L _ M a x V F T s L r
The Δ i L _ M a x represents the maximum output inductor current ripple of the converter. In the case of the step-down converter, it occurs when duty = 0.5. While D Δ i L _ M a x T s represents the time when the actual resonant inductor current is clamped by the D1 diode, this time can be approximated as the duty cycle time of the step-down converter. However, too large ∆iLr will increase the circuit’s unnecessary conduction loss. It is generally recommended that the final design value be close to the minimum value, taking only necessary margins for some component uncertainties. After Cr is determined, CossD is obtained by subtracting the parasitic capacitance of CossQsr from the value of Cr. As a matter of general design, the value of CossD requires additional shunt capacitance in addition to the parasitic capacitance of the diode itself. Although the parasitic capacitance of semiconductor devices changes with the voltage across it, the designed value of Cr is higher than the parasitic capacitance of the diodes and MOSFETs. In other words, the externally paralleled capacitors determine the criteria of ZVS, while the effect from the parasitic capacitances can be ignored. After the Cr design is completed, the minimum value of ILr_NP is known from Equation (10), i.e., ILr_D1_ON can be obtained. Then tA can be approximated as:
t A = I L r _ D 1 _ O N L r V i n
The overall minimum dead time is tA + tB + tC. The actual dead time must be greater than this minimum value to ensure that the circuit can properly achieve ZVS.

6. Simulation and Experimental Results

For verification that the topology has the ability to naturally transform the power flow, and the switch Qsr1/Qsr2 can achieve bilateral zero voltage switching under any load conditions, the results of the simulation analysis are as follows. The key simulation parameters are listed in Table 1. The simulation conditions are input voltage = 330 V, output voltage = 50 V, and output current = 20 A to −20 A. Figure 13, Figure 14 and Figure 15 show the simulation results of forwarding output = 20 A, output = 0 A, and reverse output = −20 A. Respectively, it can be seen that under any load conditions, both Qsr1 and Qsr2 can achieve bilateral zero-voltage switching and slow down the rate of voltage change. The auxiliary switch Qaux can also achieve full-range zero voltage switching, and the switches Q1 and Q2 can achieve zero voltage switching after a certain load, reducing switching losses.
Figure 16 shows the simulation results for an extreme forward-to-reverse conversion. At t = 0.5 ms, the output current is converted from 20 A to −20 A. The ripple, ∆iLr, is designed to be 10 A. It can be seen from the figure that the output inductor current iL follows the behavior of the output current iO and the current changes from forward to reverse. Under each switching cycle, the resonant inductor current iLr automatically follows the output inductor current iL to achieve the Qsr1 and Qsr2 bilateral zero voltage switching function. After the zero-voltage switching action, the resonant inductor current iLr resets to the initial current value cycle by cycle. It can also be seen from the observation of switch signal that the switching signals of the auxiliary switches Qaux, Qsr1, and Qsr2 are the same regardless of the forward or reverse operation. It represents the function of naturally transforming the power flow without adding additional detection circuits and changing different control modes.
In order to verify the theoretical analysis, a prototype circuit of input voltage Vin = 330 V, output voltage VO = 50–250 V and output power Po = 1 kW is implemented.
Figure 17 shows the switch’s vGS signal waveform of Q1, Qsr1, Qsr2 and Qaux under the test conditions (output voltage = 250 V and output current = 4 A). In addition to verifying the relative position between the switching signals, it can be seen that all vGS signals have no Miller platform, and it can be seen that all switches have zero voltage switching.
Figure 18 shows the Qsr1 switch’s vGS signal, Qsr2 switch’s vDS voltage, resonant inductor current and output inductor current waveform under the test conditions (output voltage = 50 V and output current = 20 A). The converter operates in continuous current mode. It can be seen that the waveform rise and fall speeds of vDS_Qsr2 are simultaneously controlled and have the same slope of change.
Figure 19 shows the Qsr1 switch’s vGS signal, Qsr2 switch’s vDS voltage, resonant inductor current and output inductor current waveform under the test conditions (output voltage = 250 V and output current = 4 A). The converter operates in continuous current mode. It can be seen that the waveform rise and fall speeds of vDS_Qsr2 are simultaneously controlled and have the same slope of change. Figure 20a,b show the output voltage ripple with and without the enabling of the auxiliary switching circuit; that is, Qsr1 is hard/soft switching. Test conditions are output voltage = 250 V and output power = 1 kW. The switching noise observed in Figure 20a is 266 mV, while it is 66 mV in Figure 20b. Under the same operation conditions, the output voltage switching noise is greatly reduced by the proposed circuit.
Figure 21a,b represents similar comparisons on switching noise, except that the output voltage = 50 V in this case. The switching noise measured in Figure 21a is 200 mV, compared to 144 mV in Figure 21b. Again, switching noise can also be greatly reduced by the proposed scheme. From the experimental results, it is verified that the proposed auxiliary switching circuit can improve the switching noise under adjustable output voltage and current level. This feature is particularly useful for instrument power supplies.

7. Conclusions

This paper proposed a bidirectional converter operating at wide output voltages and load variation applications. By the auxiliary circuit, the main switches can achieve bilateral zero-voltage switching and the switching noise on the output voltage can be effectively reduced. Through the simulation and implementation results, the feasibility of the proposed architecture can be verified. A prototype of 1 kW with an output voltage of 50 V to 250 V has been implemented. Since the higher output voltage and higher load level will cause a higher voltage feeding into the output filter, the proposed method benefits even more from reducing the voltage slopes during both rising and falling. In the measured results, the best noise reduction is in the 250 V/1 kW output test condition. The switching noise of the output voltage is reduced from 266 mV to 66 mV; the reduction rate reaches about 75.18%.

Author Contributions

The author C.-C.H. is responsible for conceiving the architecture and control methods, proposing the design method and verifying with simulation and writing the thesis. T.-L.T. is responsible for the erection and implementation of the physical circuit and uses DSP to realize the control signal. Y.-C.H. and H.-J.C. are responsible for research supervising.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflicts of interest.

References

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Figure 1. Output voltage ripple (Vp-p,ripple) and switching noise (Vp-p,noise).
Figure 1. Output voltage ripple (Vp-p,ripple) and switching noise (Vp-p,noise).
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Figure 2. LC low-pass filter (a) ideal model; (b) non-ideal model.
Figure 2. LC low-pass filter (a) ideal model; (b) non-ideal model.
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Figure 3. Bode plots of ideal and non-ideal filters.
Figure 3. Bode plots of ideal and non-ideal filters.
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Figure 4. The equivalent series inductance (ESL) and equivalent series resistance (ESR) elimination concept for capacitors [3]. Z1 = compensation impedance. Z2 = non-ideal capacitor equivalent circuit.
Figure 4. The equivalent series inductance (ESL) and equivalent series resistance (ESR) elimination concept for capacitors [3]. Z1 = compensation impedance. Z2 = non-ideal capacitor equivalent circuit.
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Figure 5. Fourier spectrum of a rectangular and trapezoidal waveform. Rect. Wave = a rectangular waveform; Trap. Wave-1 = a trapezoidal waveform of tr = tf = 500 ns; Trap. Wave-2 = a trapezoidal wave of tr = 500 ns, tf = 50 ns; fs = switching frequency; fr* = control by the trapezoidal wave.
Figure 5. Fourier spectrum of a rectangular and trapezoidal waveform. Rect. Wave = a rectangular waveform; Trap. Wave-1 = a trapezoidal waveform of tr = tf = 500 ns; Trap. Wave-2 = a trapezoidal wave of tr = 500 ns, tf = 50 ns; fs = switching frequency; fr* = control by the trapezoidal wave.
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Figure 6. Simulation result of switching noise under different input voltage waveforms. pk-pk = peak–peak; Vrms = rms value of voltage ripple.
Figure 6. Simulation result of switching noise under different input voltage waveforms. pk-pk = peak–peak; Vrms = rms value of voltage ripple.
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Figure 7. Bilateral zero-voltage switching (ZVS) synchronous rectified step-down converter.
Figure 7. Bilateral zero-voltage switching (ZVS) synchronous rectified step-down converter.
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Figure 8. Bilateral ZVS synchronous rectified step-down converter operation waveform (forward mode).
Figure 8. Bilateral ZVS synchronous rectified step-down converter operation waveform (forward mode).
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Figure 9. Topology operation intervals of the proposed converter.
Figure 9. Topology operation intervals of the proposed converter.
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Figure 10. Bilateral ZVS synchronous rectified step-down converter operation waveform (reverse mode).
Figure 10. Bilateral ZVS synchronous rectified step-down converter operation waveform (reverse mode).
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Figure 11. Equivalent circuit of the resonant period (t1t2).
Figure 11. Equivalent circuit of the resonant period (t1t2).
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Figure 12. Detailed timing diagram of the switching operation.
Figure 12. Detailed timing diagram of the switching operation.
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Figure 13. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = 20 A.
Figure 13. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = 20 A.
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Figure 14. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = 0 A.
Figure 14. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = 0 A.
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Figure 15. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = −20 A.
Figure 15. Simulation results: vGS and vDS waveforms of each switch, resonant inductor and output inductor current waveform at VO = 50 V, Io = −20 A.
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Figure 16. Simulation results: vGS waveforms of each switch, resonant inductor, output inductor current and output current waveform at VO = 50 V, Io = 20 A to −20 A.
Figure 16. Simulation results: vGS waveforms of each switch, resonant inductor, output inductor current and output current waveform at VO = 50 V, Io = 20 A to −20 A.
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Figure 17. Switch gating signals (scale vGS_Q1 (Ch1): 20 V/div; vGS_Qsr1 (Ch2): 20 V/div; vGS_Qsr2 (Ch3): 20 V/div; vGS_aux (Ch4): 20 V/div; time: 1 µs/div).
Figure 17. Switch gating signals (scale vGS_Q1 (Ch1): 20 V/div; vGS_Qsr1 (Ch2): 20 V/div; vGS_Qsr2 (Ch3): 20 V/div; vGS_aux (Ch4): 20 V/div; time: 1 µs/div).
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Figure 18. Resonant inductor current and output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 50 V, Io = 20 A (scale iL (Ch1): 20 A/div; iLr (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
Figure 18. Resonant inductor current and output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 50 V, Io = 20 A (scale iL (Ch1): 20 A/div; iLr (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
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Figure 19. Resonant inductor current and output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 250 V, Io = 4 A (scale iL (Ch1): 10 A/div; iLr (Ch2): 10 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
Figure 19. Resonant inductor current and output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 250 V, Io = 4 A (scale iL (Ch1): 10 A/div; iLr (Ch2): 10 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
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Figure 20. Switching noise performance: output voltage ripple, output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 250 V, Io = 4 A (a) without peration of auxiliary circuit (b) with peration of auxiliary circuit (scale vo ripple (Ch1): 200mV/div; iL (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
Figure 20. Switching noise performance: output voltage ripple, output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 250 V, Io = 4 A (a) without peration of auxiliary circuit (b) with peration of auxiliary circuit (scale vo ripple (Ch1): 200mV/div; iL (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
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Figure 21. Switching noise performance: output voltage ripple, output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 50 V, Io = 20 A (a) without peration of auxiliary circuit (b) with peration of auxiliary circuit (scale vo ripple (Ch1): 200 mV/div; iL (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
Figure 21. Switching noise performance: output voltage ripple, output inductor current waveform, Qsr1 switch’s vGS signal and Qsr2 switch’s vDS voltage at VO = 50 V, Io = 20 A (a) without peration of auxiliary circuit (b) with peration of auxiliary circuit (scale vo ripple (Ch1): 200 mV/div; iL (Ch2): 20 A/div; vGS_Qsr1 (Ch3): 20 V/div; vDS_Qsr2 (Ch4): 500 V/div; time: 1 µs/div).
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Table 1. The key simulation parameters.
Table 1. The key simulation parameters.
ParameterSymbolSpecification
Switching frequencyfsw200 kHz
Dead time between Qsr1 and Qsr2-500 nS
Resonant inductorLr2.3 μH
Output inductorLo82.5 μH
Output capacitorCo1.36 mF
Switching parasitic capacitanceCossQ*/CossQsr*150 pF
Diode parallel capacitorCossD*40 + 1160 pF

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