Article Versions Notes

Wang H, Wang J, Hu H, Li G, Hu S, Yu Q, Liu Z, Chen T, Zhou S, Liu Y. Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory. Sensors. 2023; 23(5):2401. https://doi.org/10.3390/s23052401

Wang, Hongzhe, Junjie Wang, Hao Hu, Guo Li, Shaogang Hu, Qi Yu, Zhen Liu, Tupei Chen, Shijie Zhou, and Yang Liu. 2023. "Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory" Sensors 23, no. 5: 2401. https://doi.org/10.3390/s23052401

Wang, H., Wang, J., Hu, H., Li, G., Hu, S., Yu, Q., Liu, Z., Chen, T., Zhou, S., & Liu, Y. (2023). Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory. Sensors, 23(5), 2401. https://doi.org/10.3390/s23052401