Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application
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Institute of Computer Systems, Odessa National Polytechnic University, 65044 Odessa, Ukraine
2
Faculty of Electrical and Computer Engineering, Cracow University of Technology, 31-155 Cracow, Poland
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Faculty of Transport, Electrical Engineering and IT, Kazimierz Pulaski University of Technology and Humanities in Radom, 26-600 Radom, Poland
4
Research Institute for Intelligent Computer Systems, West Ukrainian National University, 46027 Ternopil, Ukraine
*
Author to whom correspondence should be addressed.
Sensors 2021, 21(3), 792; https://doi.org/10.3390/s21030792
Received: 29 November 2020
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Revised: 15 January 2021
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Accepted: 22 January 2021
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Published: 25 January 2021
(This article belongs to the Special Issue Convergence of Intelligent Data Acquisition and Advanced Computing Systems)
This paper presents a power-oriented monitoring of clock signals that is designed to avoid synchronization failure in computer systems such as FPGAs. The proposed design reduces power consumption and increases the power-oriented checkability in FPGA systems. These advantages are due to improvements in the evaluation and measurement of corresponding energy parameters. Energy parameter orientation has proved to be a good solution for detecting a synchronization failure that blocks logic monitoring circuits. Key advantages lay in the possibility to detect a synchronization failure hidden in safety-related systems by using traditional online testing that is based on logical checkability. Two main types of power-oriented monitoring are considered: detecting a synchronization failure based on the consumption and the dissipation of power, which uses temperature and current consumption sensors, respectively. The experiments are performed on real FPGA systems with the controlled synchronization disconnection and the use of the computer-aided design (CAD) utility to estimate the decreasing values of the energy parameters. The results demonstrate the limited checkability of FPGA systems when using the thermal monitoring of clock signals and success in monitoring by the consumption current.
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Keywords:
safety-related system; component; FPGA-designing; logical and power-oriented checkability; hidden faults; clock signal; consumed and dissipated power; temperature and current consumption sensors
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MDPI and ACS Style
Drozd, O.; Nowakowski, G.; Sachenko, A.; Antoniuk, V.; Kochan, V.; Drozd, M. Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application. Sensors 2021, 21, 792. https://doi.org/10.3390/s21030792
AMA Style
Drozd O, Nowakowski G, Sachenko A, Antoniuk V, Kochan V, Drozd M. Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application. Sensors. 2021; 21(3):792. https://doi.org/10.3390/s21030792
Chicago/Turabian StyleDrozd, Oleksandr, Grzegorz Nowakowski, Anatoliy Sachenko, Viktor Antoniuk, Volodymyr Kochan, and Myroslav Drozd. 2021. "Power-Oriented Monitoring of Clock Signals in FPGA Systems for Critical Application" Sensors 21, no. 3: 792. https://doi.org/10.3390/s21030792
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