Search Results (8)

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs. Full article

This study introduces a novel, non-rotationally symmetrical auxiliary electrode design aimed at mitigating localized hotspots and enhancing the deposition uniformity in wafer-level electroplating for advanced large-scale chip packaging. The formation of hotspots and deposition non-uniformity, particularly at the wafer edge and in regions with complex die layouts, presents significant challenges in electroplating processes. To address these issues, the proposed auxiliary electrode incorporates a dynamic angle control mechanism, which facilitates the precise, localized modulation of the current density. This innovative design improves the regulation of current distribution in hotspot-prone regions, without compromising the overall stability and uniformity of the wafer-level electroplating process. Extensive numerical simulations were conducted to assess the electrode’s effectiveness in redistributing current density, resulting in a marked reduction in current density at the wafer edge, thereby mitigating over-deposition and enhancing overall uniformity. The simulation results also demonstrated the electrode’s capability for dynamic current flow regulation, enabling localized adjustments only when necessary and minimizing disruptions to the electroplating process. Experimental validation further corroborated the simulation findings, with repeated trials confirming the electrode’s consistent performance in reducing localized over-deposition in hotspot regions while maintaining uniform plating in unaffected areas. These findings underscore the potential of the auxiliary electrode as a robust solution for addressing hotspot formation and deposition uniformity challenges in electroplating, providing a solid foundation for its industrial implementation in advanced chip packaging and related fields. Full article

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver’s sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm² with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively. Full article

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV⁻¹ bar⁻¹. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors. Full article

Solder joint fatigue is one of the critical failure modes in ball-grid array packaging. Because the reliability test is time-consuming and geometrical/material nonlinearities are required for the physics-driven model, the AI-assisted simulation framework is developed to establish the risk estimation capability against the design and process parameters. Due to the time-dependent and nonlinear characteristics of the solder joint fatigue failure, this research follows the AI-assisted simulation framework and builds the non-sequential artificial neural network (ANN) and sequential recurrent neural network (RNN) architectures. Both are investigated to understand their capability of abstracting the time-dependent solder joint fatigue knowledge from the dataset. Moreover, this research applies the genetic algorithm (GA) optimization to decrease the influence of the initial guessings, including the weightings and bias of the neural network architectures. In this research, two GA optimizers are developed, including the “back-to-original” and “progressing” ones. Moreover, we apply the principal component analysis (PCA) to the GA optimization results to obtain the PCA gene. The prediction error of all neural network models is within 0.15% under GA optimized PCA gene. There is no clear statistical evidence that RNN is better than ANN in the wafer level chip-scaled packaging (WLCSP) solder joint reliability risk estimation when the GA optimizer is applied to minimize the impact of the initial AI model. Hence, a stable optimization with a broad design domain can be realized by an ANN model with a faster training speed than RNN, even though solder fatigue is a time-dependent mechanical behavior. Full article

To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to replace current chip on board (COB) packages. In this paper, a WLCSP with the size of 5.82 mm × 5.22 mm and thickness of 850 μm was developed for the backside illumination (BSI) CIS chip using a 65 nm node with a size of 5.8 mm × 5.2 mm. The packaged product has 1392 × 976 pixels and a resolution of up to 60 frames per second with more than 120 dB dynamic range. The structure of the 3D package was designed and the key fabrication processes on a 12” inch wafer were investigated. More than 98% yield and excellent optical performance of the CIS package was achieved after process optimization. The final packages were qualified by AEC-Q100 Grade 2. Full article

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved. Full article

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. Full article