Search Results (419)

Battery cell balancing is crucial in series-connected lithium-ion packs to maximize usable capacity, ensure safe operation, and prolong cycle life. This paper presents a comprehensive study and a novel adaptive duty-cycled hybrid balancing system that combines passive bleed resistors and an active switched-capacitor (SC) balancer, specifically designed for a 4-cell series-connected battery pack. This work also explored open circuit voltage (OCV)-driven adaptive pulse-frequency modulation (PFM) active balancing to achieve higher efficiency and better balancing speed based on different system requirements. Finally, this paper compares passive, active (SC-based), and adaptive duty-cycled hybrid balancing strategies in detail, including theoretical modeling of energy transfer and efficiency for each method. Simulation showed that the adaptive hybrid balancer speeds state-of-charge (SoC) equalization by 16.24% compared to active-only balancing while maintaining an efficiency of 97.71% with minimal thermal stress. The simulation result also showed that adaptive active balancing was able to achieve a high efficiency of 99.86% and provided an additional design degree of freedom for different applications. The results indicate that the adaptive hybrid balancer offered an excellent trade-off between balancing speed, efficiency, and implementation simplicity for 4-cell Li-ion packs, making it highly suitable for applications such as high-voltage portable chargers. Full article

This paper presents two classic analog oscillators: a relaxation oscillator and a Wien bridge one, where a memristor replaces a resistor. The circuits are simulated in TopSPICE 7.12 using a memristor emulation circuit and commercially available components to evaluate the memristor’s impact. In the case of the relaxation oscillator, which includes the memristor, a notable increase in oscillation frequency was observed compared to the classical circuit, with a nearly 10-fold increase from 790 Hz to 7.78 kHz while maintaining a constant amplitude. This confirms the influence of the memristor’s dynamic resistance on the circuit time constant. On the other hand, the Wien-bridge oscillator exhibits variations in specific parameters, such as peak voltage, amplitude, and frequency. In this case, the oscillation frequency decreased from 405 Hz to 146 Hz with the addition of the memristor, a characteristic introduced by the proposed memristive element’s nonlinear interactions. Experimental results confirm the feasibility of incorporating memristors into classical oscillator circuits, enabling frequency changes while maintaining stable oscillations, allowing reconfigurable and adaptable analog designs that leverage the properties of memristive devices. Full article

This paper presents a microstrip active quasi-circulator designed for low-power wireless communication systems. The circuit consists of a second-order Wilkinson power divider and two power amplifiers with high gain and ultra-low noise characteristics. By leveraging the unidirectional transmission characteristics of the transistors and the isolation provided by resistors within the power divider, the interference between the transmitter (TX) and receiver (RX) is effectively suppressed. Additionally, thanks to the dual-amplifier architecture, no extra power amplification circuitry is required, thereby reducing the overall complexity and power consumption of the communication system. The detailed design procedure of the proposed quasi-circulator is presented. The measurement results show that, within the frequency range of 4.75 GHz to 6.11 GHz, the isolation between the TX and RX ports exceeds 20 dB, the return loss at each port is greater than 10 dB, and the transmission gains from the TX port to the antenna and from the antenna to the RX port are 3.1–8.7 dB and 2.7–4.0 dB, respectively, demonstrating a relative bandwidth of 25%. Full article

A bias-free antenna tuning technique that eliminates conventional DC biasing networks is presented. The tuning mechanism is based on a Light-Dependent Resistor (LDR) embedded within the antenna structure. Optical illumination is used to modulate the LDR’s resistance, thereby altering the antenna’s effective electrical length and enabling tuning of its resonant frequency and operating bands. By removing the need for bias lines, RF chokes, blocking capacitors, and control circuitry, the proposed approach minimizes parasitic effects, losses, biasing energy, and routing complexity. This makes it particularly suitable for compact and energy-constrained platforms, such as Internet of Things (IoT) devices. As proof of concept, an LDR is integrated into a ring monopole antenna, achieving tri-band operation in both high and low resistance states. In the high-resistance (OFF) state, the fabricated prototype operates across 2.1–3.1 GHz, 3.5–4 GHz, and 5–7 GHz. In the low-resistance (ON) state, the LDR bridges the two arcs of the monopole, extending the current path and shifting the lowest band to 1.36–2.35 GHz, with only minor changes to the mid and upper bands. The antenna maintains linear polarization across all bands and switching states, with measured gains reaching up to 5.3 dBi. Owing to its compact, bias-free, and low-cost architecture, the proposed design is well-suited for integration into portable wireless devices, low-power IoT nodes, and rapidly deployable communications systems where electrical biasing is impractical. Full article

This paper presents a new compact and efficient first-order all-pass filter in voltage mode based on a second-generation voltage conveyor, along with two resistors, and a capacitor. This circuit delivers an all-pass response from the low-impedance node and eliminates the need for a voltage buffer in cascading configurations. A thorough non-ideal analysis, accounting for parasitic impedances and the non-ideal gains of the active module, shows negligible effects on the filter performance. Furthermore, a sensitivity analysis with respect to both active and passive components further validates the robustness of the design. The proposed all-pass filter is validated by Cadence PSPICE simulations, utilizing 0.18 µm TSMC CMOS process parameter and ±0.9 V power supply, including Monte Carlo analysis and temperature variations. Additionally, experimental validation is carried out using commercially available IC AD844, showing great consistency between theoretical and experimental results. Resistor-less realization of the proposed filter provides tunability feature. A quadrature sinusoidal oscillator is presented to validate the proposed structure. The introduced circuit provides a simple and effective solution for low-power and compact analog signal processing applications. Full article

This paper offers a comprehensive methodology for the synthesis and analysis of active filters, including low-pass, high-pass, and band-pass configurations, utilizing operational amplifiers and multi-loop negative feedback systems. The approach involves deriving explicit analytical expressions for the design and optimization of eight distinct filter circuit solutions: one low-pass, one high-pass, and six band-pass filters with varying specifications. These derivations include the calculation of normalized and denormalized component values (resistors and capacitors), enabling precise tuning and practical implementation of the filters. Furthermore, the methodology encompasses the determination of key filter parameters such as passband gain, pole quality factor (Q-factor), and cut-off/center frequency, after selecting standard resistor and capacitor values suitable for the target application. The analytical framework facilitates a systematic approach to filter design, ensuring that the resulting circuits meet specific frequency response criteria while maintaining optimal stability and performance. The proposed methodology can be effectively applied in the development of various active filtering systems for signal processing, communication, and instrumentation, offering engineers a reliable foundation for designing high-performance, tailored filter solutions. Full article

Closing resistors in ultra-high-voltage (UHV) gas-insulated circuit breakers (GCBs) are critical components designed to suppress inrush currents and transient overvoltages during switching operations. However, in practical service, these resistors are subjected to repeated mechanical impacts and transient electrical stresses, leading to degradation of their electrical contact interfaces, fluctuating resistance values, and potential failure of the entire breaker assembly. Existing studies mostly simplify the closing resistor as a constant resistance element, neglecting the coupled electro-thermal–mechanical effects that occur during transient events. In this work, a comprehensive modeling framework is developed to investigate the dynamic electrical contact characteristics of a 750 kV GCB closing resistor under transient closing impacts. First, an electromagnetic transient model is built to calculate the combined inrush and power-frequency currents flowing through the resistor during its pre-insertion period. A full-scale mechanical test platform is then used to capture acceleration signals representing the mechanical shock imparted to the resistor stack. These measured signals are fed into a finite element model incorporating the Cooper–Mikic–Yovanovich (CMY) electrical contact correlation to simulate stress evolution, current density distribution, and temperature rise at the resistor interface. The simulation reveals pronounced skin effect and current crowding at resistor edges, leading to localized heating, while transient mechanical impacts cause contact pressure to fluctuate dynamically—resulting in a temporary decrease and subsequent recovery of contact resistance. These findings provide insight into the real-time behavior of closing resistors under operational conditions and offer a theoretical basis for design optimization and lifetime assessment of UHV GCBs. Full article

This paper presents a three-segment interpolating Digital-to-Analog Converter (DAC) that employs a redundancy-based interpolation scheme and digital calibration to enhance linearity. The proposed architecture consists of a Most Significant Bit (MSB) resistor string DAC, an Intermediate Significant Bit (ISB) resistor string DAC, and a Least Significant Bit (LSB) interpolating differential buffer. The MSB segment uses a split-unit resistor structure ($r_A,r_B$) to improve post-calibration differential nonlinearity (DNL) by minimizing voltage step errors. A fully digital calibration algorithm is implemented to compensate for process variations, component mismatches, and finite switch resistance, ensuring a highly linear DAC output. The proposed 16-bit DAC is implemented in a 180 nm CMOS process and is segmented into a 5-bit MSB stage, a 5-bit ISB stage, and a 6-bit LSB stage. The structure achieves post-calibration integral nonlinearity (INL) and differential nonlinearity (DNL) values of less than ±1 LSB. Simulation results validate the proposed design, demonstrating enhanced linearity and reduced area overhead compared with conventional segmented architectures. Full article

This paper presents a W-band high-efficiency and high-output-power power amplifier (PA) based on a 130 nm AlGaN/GaN-on-SiC HEMT process. The PA is designed to deliver optimal output power and gain performance across the entire W-band. A balanced architecture is adopted, combining two amplifier units through Lange couplers. High- and low-impedance microstrip lines are employed for input, output, and inter-stage matching. Each amplifier core adopts a three-stage configuration with gate width ratios of 1:2:4 to enhance gain. The bias network incorporates MIM capacitors and thin-film resistors to improve stability. Measured results indicate a small signal gain exceeding 17 dB under a gate voltage of −2.2 V and a drain voltage of +20 V. Within the 80–86 GHz frequency range, the PA achieves an output power above 34 dBm with a 22 dBm input power, corresponding to a power gain above 12 dB and a power-added efficiency (PAE) greater than 20%. The chip occupies a compact area of 2.65 mm × 3.75 mm. Compared with previously reported works, the proposed PA demonstrates the highest PAE within the 80–86 GHz band. Full article

This paper presents the design and implementation of an ultra-wideband (UWB) and flat gain low noise amplifier (LNA) using 0.15 µm GaAs pHEMT technology, specifically tailored for applications that benefit from multi-band capability, such as satellite communication. The designed LNA consists of three stages: Two stages are cascoded using source degeneration with a resistor for low noise and high linearity, and the third cascaded stage is utilized for high gain. The designed UWB LNA exhibits a measured gain of 17.4 ± 1 dB between 312 and GHz and a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz). It achieves a noise figure (NF) of 2.5–4.3 dB and an output P1dB of 15 dBm. The chip size is $3\times 1$${\mathrm{mm}}^2$, and it operates without the need for any external components. When compared to LNAs in the literature, the proposed design stands out for its flat gain in the specified frequency band, making the LNA particularly attractive for volume-limited and power-constrained applications. Full article

Accurate parametric modeling of lithium-ion batteries is essential for battery management system (BMS) design in electric vehicles and broader energy storage applications, enabling reliable state estimation and effective thermal control under diverse operating conditions. This study presents a detailed characterization of lithium-ion cells to support advanced BMS in electric vehicles and stationary storage. A second-order equivalent circuit model is developed to capture instantaneous and dynamic voltage behavior, with parameters extracted through Hybrid Pulse Power Characterization over a broad range of temperatures (−10 °C to 45 °C) and state-of-charge levels. The method includes multi-duration pulse testing and separates ohmic and transient responses using two resistor–capacitor branches, with parameters tied to physical processes like charge transfer and diffusion. A weakly coupled electro-thermal model is presented to support real-time BMS applications, enabling accurate voltage, temperature, and heat generation prediction. This study also evaluates open-circuit voltage and direct current internal resistance across pulse durations, leading to power capability maps (“fish charts”) that capture discharge and regenerative performance across SOC and temperature. The analysis highlights performance asymmetries between charging and discharging and confirms model accuracy through curve fitting across test conditions. These contributions enhance model realism, thermal control, and power estimation for real-world lithium-ion battery applications. Full article

The bulk linearization technique is a design strategy used to extend the linear region of a metal oxide semiconductor field effect transistor (MOSFET) by increasing its saturation voltage through a composite structure and a gate biasing circuit. This allows us to develop compact and flexible pseudo-resistor elements for integrated circuit designs. In this paper we propose a new simple yet effective design approach, focused on the biasing circuit, that optimizes area, offset, and power consumption without altering the design complexity of the original solution. Post-layout simulations verify the presented design strategy, which is then applied for designing a band-pass filter for neural action potential acquisition. Results of harmonic distortion and noise analysis strengthen the validity of the proposed strategy. Full article

Non-nutritive sucking (NNS) is an instinctive behavior in newborns, consisting of two stages: sucking and expression. It plays a critical role in preparing the infant for oral feeding. In neonatal and pediatric units, NNS assessment is routinely performed to determine feeding readiness. However, these evaluations are often subjective and rely heavily on the clinician’s experience. While other medical devices that support the development of NNS skills exist, they are not specifically designed for the comprehensive assessment of NNS, and their high cost limits accessibility for many hospitals and tertiary care units globally. This paper presents the development and pilot testing of a low-cost, portable device and accompanying software for assessing NNS in newborns hospitalized in neonatal care units. Methods: The device uses force-sensitive resistors to capture expression pressure and a differential pressure sensor to measure NNS. Data were acquired through the analog–digital converter of a microcontroller and transmitted via Bluetooth for real-time graphical analysis. Pilot testing was conducted with six hospitalized preterm newborns, measuring intensity, number of bursts, and sucks per burst. Results demonstrated that the system reliably captures both stages of NNS. Significance: This device provides an affordable, portable solution to support clinical decision-making in clinical units, facilitating accurate, objective monitoring of feeding readiness and developmental progression. Full article

A square patch metasurface is designed, simulated, fabricated, and experimentally tested to investigate polarization characteristics quantitatively. The metasurface consists of one layer unit cell in the form of a square patch with one via and a lumped resistor, which is used for harvesting RF (radio frequency) energy. FR4 dielectric is used as a substrate supported by a metal ground plane. Polarization-dependent properties with specific surface current patterns and voltage dip are obtained when simulating under normal incidence of a plane wave. This characteristic results from changes in surface current conditions when the polarization angle is varied. A voltage dip appears at a specific polarization angle when the surface current pattern is symmetrical. This condition occurs when the position of the lumped resistor from the center of the patch is perpendicular to the linearly polarized incident electric field. A couple of 10 × 10 arrays with different resistor positions are fabricated and tested. The experimental results are in good agreement with the simulated results. The proposed design demonstrates a symmetric unit cell structure with one via and a resistor that exhibits polarization-dependent behavior for linear polarization. An asymmetric patch design is explored through both simulation and measurement to mitigate polarization dependence by suppressing the dip behavior, albeit at the expense of reduced absorption efficiency. This study provides a complete polarization analysis for both symmetric and asymmetric patch metasurfaces with a single via and a single lumped resistor, and introduces a predictive relation between the position of the resistor relative to the center of the patch and the resulting voltage dip behavior. Full article

In high-precision Hemispherical Resonator Gyroscope (HRG) control systems, readout circuit noise critically determines resonator displacement detection precision. Addressing noise issues, this paper compares the noise characteristics and contribution mechanisms of the Transimpedance Amplifier (TIA) and Charge-Sensitive Amplifier (CSA). By establishing a noise model and analyzing circuit bandwidth, the dominant role of feedback resistor thermal noise in the TIA is revealed. These analyses further demonstrate the significant suppression of high-frequency noise by the CSA capacitive feedback network. Simulation and experimental results demonstrate that the measured noise of the TIA and CSA is consistent with the theoretical model. The TIA output noise is 25.8 $\mathsf{\mu }{V}_{\mathrm{rms}}$, with feedback resistor thermal noise accounting for 99.8%, while CSA output noise is reduced to 13.2 $\mathsf{\mu }{V}_{\mathrm{rms}}$, a reduction of 48.8%. Near resonant frequency, the equivalent displacement noise of the CSA is $1.69\times {10}^{-14}\mathrm{m}/\sqrt{\mathrm{Hz}}$, a reduction of 86.7% compared to the TIA’s $1.27\times {10}^{-13}\mathrm{m}/\sqrt{\mathrm{Hz}}$, indicating the CSA is more suitable for high-precision applications. This research provides theoretical guidance and technical references for the topological selection and parameter design of HRG readout circuits. Full article