MDPI - Publisher of Open Access Journals

14 pages, 4125 KiB

Open AccessFeature PaperArticle

New Resistor-Less Electronically Controllable ±C Simulator Employing VCII, DVCC, and a Grounded Capacitor

by Giuseppe Ferri, Leila Safari, Gianluca Barile, Massimo Scarsella and Vincenzo Stornelli

Electronics 2022, 11(2), 286; https://doi.org/10.3390/electronics11020286 - 17 Jan 2022

Cited by 25 | Viewed by 2912

In this paper, a new realization of electronically controllable positive and negative floating capacitor multiplier (±C) is presented. The peculiarity of the presented topology is that, for the first time, it implements a floating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII^±) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage V_C which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µm and ±0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ±10 to ±25.4 with a maximum error of 0.56%. As an example, the application of the achieved floating capacitor as a standard high pass filter is also included. Full article

(This article belongs to the Section Circuit and Signal Processing)

► Show Figures

Figure 1

15 pages, 7417 KiB

Open AccessArticle

A New Simulated Inductor with Reduced Series Resistor Using a Single VCII±

by Erkan Yuce, Leila Safari, Shahram Minaei, Giuseppe Ferri, Gianluca Barile and Vincenzo Stornelli

Electronics 2021, 10(14), 1693; https://doi.org/10.3390/electronics10141693 - 15 Jul 2021

Cited by 25 | Viewed by 3987

Abstract

This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be significantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard fifth-order high-pass ladder filter is also given. SPICE simulations using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V as well as experimental verifications, are carried out to support the theory. Full article

(This article belongs to the Section Circuit and Signal Processing)

► Show Figures

Figure 1

16 pages, 24016 KiB

Open AccessFeature PaperArticle

Electronically Tunable First Order AP/LP and LP/HP Filter Topologies Using Electronically Controllable Second Generation Voltage Conveyor (CVCII)

by Gianluca Barile, Leila Safari, Leonardo Pantoli, Vincenzo Stornelli and Giuseppe Ferri

Electronics 2021, 10(7), 822; https://doi.org/10.3390/electronics10070822 - 30 Mar 2021

Cited by 28 | Viewed by 2989

Abstract

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or [...] Read more.

V_{LP}

I_{AP}

V_{AP}

and in the second topology

I_{LP}

V_{LP}

I_{HP}

V_{HP}

outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (

I_{con}

) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (

f_{0}

) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (

V_{con}

). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing

I_{con}

from 0.5 µA to 50 µA,

f_{0}

is varied from 89 kHz to 1 MHz. Similarly, for a

V_{con}

variation from −0.9 V to 0.185 V, the gains of

I_{AP}

and

I_{HP}

vary from 30 dB to 0 dB and those of

V_{AP}

and

V_{HP}

vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW. Full article

(This article belongs to the Section Power Electronics)

► Show Figures

Figure 1

Search Results (3)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Saved Queries

Search Filter Reset All

Years

Feature Papers

Subjects

Journals

Article Types

Countries / Regions

Search Results (3)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI