Electronically Tunable First Order AP/LP and LP/HP Filter Topologies Using Electronically Controllable Second Generation Voltage Conveyor (CVCII)

Abstract

In this paper two new first order filter topologies realizing low-pass/all-pass (LP/AP) and low-pass/high-pass (LP/HP) outputs using electronically controllable second generation voltage conveyors (CVCIIs) are presented. Unlike second generation voltage conveyors (VCII), in CVCII each performance parameter, including ports, parasitic impedances, current and/or voltage gains can be electronically varied. Here, in particular, the proposed filter topologies are based on two CVCIIs, one resistor and one capacitor. In the first topology ${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{AP}}$/${\mathrm{V}}_{\mathrm{AP}}$ and in the second topology ${\mathrm{I}}_{\mathrm{LP}}$/${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{HP}}$/${\mathrm{V}}_{\mathrm{HP}}$ outputs are achievable, respectively. However, the current and voltage outputs are not achievable simultaneously and a floating capacitor is used. A control current (${\mathrm{I}}_{\mathrm{con}}$) is used to change the first CVCII Y port impedance, which sets the filter −3 dB frequency (${\mathrm{f}}_0$) of all the outputs. Moreover, in the second topology, the gains of HP and AP outputs are electronically adjusted by means of a control voltage (${\mathrm{V}}_{\mathrm{con}}$). Favorably, no restricting matching condition is necessary. PSpice simulations using 0.18 µm CMOS technology and supply voltages of ±0.9V show that by changing ${\mathrm{I}}_{\mathrm{con}}$ from 0.5 µA to 50 µA, ${\mathrm{f}}_0$ is varied from 89 kHz to 1 MHz. Similarly, for a ${\mathrm{V}}_{\mathrm{con}}$ variation from −0.9 V to 0.185 V, the gains of ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{I}}_{\mathrm{HP}}$ vary from 30 dB to 0 dB and those of ${\mathrm{V}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$ vary from 100 dB to 20 dB. The total harmonic distortion (THD) is about 8%. The power consumption is from 0.385 mW to 1.057 mW.

1. Introduction

First order filters are fundamental building blocks in analog signal processing since they find wide applications in realizing higher order filter topologies [1,2,3,4,5,6,7]. The first order low-pass (LP) and high-pass (HP) filters are used to separate signals according to their frequency in various applications. However, the first order all-pass (AP) type has a different function. It is used to shift signal phase while its amplitude is kept constant. In addition, the first order AP type is also used to equalize the undesired phase change that occurs during signal processing. Other applications are high quality factor frequency selective filters and synthesizing quadrature and multiphase oscillators.

Due to many advantages given by current mode signal processing, in recent times various current mode active building blocks (ABBs) have been employed in the realization of first order filters [8,9,10,11,12,13,14,15,16,17,18,19]. The main benefits achieved by processing signals in current domain are high frequency operation, reduced complexity, low voltage operation, etc. Specifically, after the introduction of the second generation current controlled current conveyor (CCCII) [20], the new age of electronically tunable filter design has begun. In the electronically tunable filters, natural frequency and/or gain can be tuned using a control voltage or current. Therefore, not only the number of passive components is reduced but also the possibility of full integration is provided.

The literature survey shows that the electronically tunable first order filters reported so far [21,22,23,24,25,26,27,28,29,30,31,32] suffer from a number of shortcomings. In [21], a first order AP filter using simple current mirrors is reported. Using two control voltages of (+VA and −VA), the bias current of the current mirrors is varied, so its input impedance is electronically varied, resulting in an electronically variable −3 dB frequency (${\mathrm{f}}_0$). Unfortunately, it lacks electronic tunability of gain. In [22], a new implementation of the first order AP/HP/LP filter is reported using inverting type second generation current conveyor (ICCII). Here, to change ${\mathrm{f}}_0$, an electronically variable resistor implemented by a single MOS transistor is used, but its main limitation is that the value of the gain is not electronically controllable. In [23], BJT current mirrors are used to implement first order AP/HP filter. Similar to [21], ${\mathrm{f}}_0$ is changed by varying the input impedance through a suitable variation of the bias current. However, it is not fully electronically controllable because its gain is fixed. In the topology reported in [24], CCCII is used as active building block. The impedance at X port of CCCII is varied through the control current, resulting in the electronic tuning of ${\mathrm{f}}_0$. However, the filter gain is constant. In [25], a first order AP filter using current differencing transconductance amplifier (CDTA) is reported. In this circuit, the electronic tuning of ${\mathrm{f}}_0$ is achieved through the control current, which tunes the value of CDTA transconductance. Nevertheless, its gain is unitary and uncontrollable. In [26], two current controlled current conveyor transconductance amplifiers (CCCCTA) implemented in BJT technology and a capacitor are used to design a first order AP filter. In this approach the first control current is used to tune ${\mathrm{f}}_0$ while the second control current sets the filter gain. Unfortunately, the CCCCTA implementation requires 51 BJT transistors and high supply voltage. In [27], a first order AP filter is introduced using BJT based modified CCCII where the impedance at X port is varied by the control current. Its correct operation relies on the accuracy of the used current mirrors employed in the internal structure of CCCII. In addition, it can only provide gain value of unity. Other CCCII based AP filters, such as that described in [28], suffer from matching conditions, which are not easy to fulfil, and in which the value of parasitic impedance at the X port must be half of the used passive resistor. The topology reported in [29] using dual output CCCII suffers from matching condition restriction and no gain controllability. In [30], the used ABB is CCCTA and it provides full electronic controllability over all-pass current. In [31], a current follower cascaded transconductance amplifier (CFCTA) is used to produce first order positive/negative low-pass current with fully electronic controllability. Unfortunately, it suffers from high power consumption. In [32], an adjustable current amplifier (CA) and two current buffers (CBs) are used to produce fully differential first order AP current output. The circuit of [32] suffers from high power consumption. In summary, apart from other limitations, the common drawback of all of the electronically tunable first order filters reported in [18,19,20,21,22,23,24,25,26,27,28,29,30,31,32] is that the output signals are in current form so they are limited to current output applications.

Recently, for applications requiring voltage output, a new active building block called second generation voltage conveyor (VCII), which is the dual of CCII, has been used [33,34,35,36,37,38]. The advantage of this new ABB over CCII and other current mode ABBs is the possibility of processing signals in the current domain while producing the output signals in both the forms of voltage and of current. This new ABB has a low impedance current input port, a high impedance current output port and a low impedance voltage output port. Recently, voltage output second order BP/LP and first order AP filter topologies using VCII have been reported [37,38]. The VCII based filter of [38] produces first order all-pass voltage using one dual output VCII, two resistors and one capacitor. It has two main problems: first, its operation relies on matching conditions between the resistors; second, it lacks electronic tuning capability.

The aim of this paper is the design of versatile voltage and current output electronically tunable first order LP/AP/HP filters without any matching condition requirement. Two topologies are introduced based on two electronically controllable VCIIs (CVCIIs), two external resistors and one capacitor. The first filter topology can produce first order ${\mathrm{V}}_{\mathrm{LP}}$, ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ outputs. However, ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ are not reachable simultaneously. The second topology produces first order ${\mathrm{I}}_{\mathrm{LP}}$, ${\mathrm{V}}_{\mathrm{LP}}$, ${\mathrm{I}}_{\mathrm{HP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$ outputs simultaneously. It must be mentioned that ${\mathrm{I}}_{\mathrm{LP}}$ and ${\mathrm{V}}_{\mathrm{LP}}$ are not simultaneously available as ${\mathrm{I}}_{\mathrm{HP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$. The outputs ${\mathrm{V}}_{\mathrm{LP}}$, ${\mathrm{V}}_{\mathrm{HP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ are available at low impedance Z ports while ${\mathrm{I}}_{\mathrm{HP}}$, ${\mathrm{I}}_{\mathrm{LP}}$ and ${\mathrm{I}}_{\mathrm{AP}}$ are available at high impedance X ports. Using a control current, the impedance at Y port of first CVCII is varied, resulting in the electronic tunablity of ${\mathrm{f}}_0$. In addition, a control voltage is used to electronically control the gain value of the HP/AP outputs through setting the current gain of second CVCII. Compared to other works, the achieved results are the follows: wider frequency range, no matching condition requirement, electronic tunability of both frequency and gain of HP/AP outputs, no need for extra current or voltage buffers for produced output signals, producing both current and voltage outputs. The noticeable novelty of this paper is that for the first time CVCII is introduced and used in the design of the filters. In fact, the results of this study could open a new era for CVCII based electronically tunable filters. The organization of this paper is as follows. In Section 2 the proposed filters are introduced. In Section 3 nonideal analysis is given. Section 4 includes internal circuit implementation of the used CVCIIs. The simulation results are reported in Section 5. Finally, section VI concludes the paper.

2. The Proposed Filters

Symbolic representations of CVCII with electronically tunable Y port impedance and electronically tunable current gain at X terminal are shown in Figure 1a,b, respectively. The operation matrix of CVCII with electronically variable impedance at Y port is given in (1a). Here, the current gain between the Y and X ports and the voltage gain between X and Z ports are ±1 (+1 for CVCII+ and −1 for CVCII−). The impedance at Y port is shown by ${\mathrm{r}}_{\mathrm{Y}}$ which can be tuned by ${\mathrm{I}}_{\mathrm{con}}$. The operation of CVCII with electronically variable current gain is given in (1b). In this case, the impedance value at the Y port is ideally zero, the value of the voltage gain between the X and Z ports is unity, while the value of current gain between Y and X ports is ±K (+K for CVCII+ and −K for CVCII−) which is adjusted by the control voltage ${\mathrm{V}}_{\mathrm{con}}$.

$$\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ {\mathrm{V}}_{\mathrm{Y}}\end{array}\right]=\left[\begin{array}{c}\pm 1 0 0\\ 0 1 0\\ {\mathrm{r}}_{\mathrm{Y}} 0 0\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\begin{array}{c}\mathrm{X}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}}\end{array}\right]$$

(1a)

$$\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ {\mathrm{V}}_{\mathrm{Y}}\end{array}\right]=\left[\begin{array}{c}\pm \mathrm{K} 0 0\\ 0 1 0\\ 0 0 0\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\begin{array}{c}\mathrm{X}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}}\end{array}\right]$$

(1b)

Figure 1. Symbolic representation of second generation voltage conveyor (CVCII+) with (a) variable impedance at Y port and (b) variable current gain.

The proposed LP/AP filter topology is shown in Figure 2. It is based on one CVCII₁⁺ with electronically variable impedance at Y port and one CVCII₂⁺ with electronically variable current gain, one capacitor ${\mathrm{C}}_1$ and two external resistors R₁ and R₂. The input signal is in current form and the produced outputs are ${\mathrm{V}}_{\mathrm{LP}}$, ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$. The voltages ${\mathrm{V}}_{\mathrm{LP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ are available at the low impedance Z ports, while the current ${\mathrm{I}}_{\mathrm{AP}}$ is available at the high impedance X port.

Figure 2. The proposed CVCII based low-pass/all-pass (LP/AP) filter topology.

By assuming Y port of CVCII₂+ at ground (since in ideal case ${\mathrm{r}}_{\mathrm{Y}2}=0$), and performing the Kirchhoff current law (KCL) at input port (named as “in”) results:

$${\mathrm{I}}_1=\frac{1}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(2)

$${\mathrm{I}}_2=\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(3)

Using (1) and (2), ${\mathrm{V}}_{\mathrm{LP}}={\mathrm{V}}_{\mathrm{X}1}$ is found as:

$${\mathrm{V}}_{\mathrm{LP}}={\mathrm{V}}_{\mathrm{X}1}=-\frac{{\mathrm{R}}_1}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(4)

Performing KCL at node 1 and using (1) and (3) result:

$${\mathrm{I}}_{\mathrm{AP}}=\mathrm{K}\frac{1-{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(5)

$${\mathrm{V}}_{\mathrm{AP}}={\mathrm{KR}}_2(\frac{1-{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}){\mathrm{I}}_{\mathrm{in}}$$

(6)

As is seen from Equations (5) and (6), the AP pole frequency is expressed by (7a) which is electronically controlled by ${\mathrm{r}}_{\mathrm{Y}1}$, while the low frequency gain of ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ are expressed in (7b) and (7c), respectively:

$${\mathrm{f}}_0=\frac{1}{2{\mathsf{\pi }\mathrm{C}}_1{\mathrm{r}}_{\mathrm{Y}1}}$$

(7a)

$${\mathrm{Gain}}_{{\mathrm{I}}_{\mathrm{AP}}}=\mathrm{K}$$

(7b)

$${\mathrm{Gain}}_{{\mathrm{V}}_{\mathrm{AP}}}={\mathrm{KR}}_2$$

(7c)

From Equation (7b,c), we can say that the gain is also electronically controllable by $\mathrm{K}$.

The proposed LP/HP filter topology is shown in Figure 3. In this topology the outputs are ${\mathrm{V}}_{\mathrm{LP}}$, ${\mathrm{I}}_{\mathrm{LP}}$, ${\mathrm{V}}_{\mathrm{HP}}$ and ${\mathrm{I}}_{\mathrm{HP}}$. Repeating the same analysis gives Equation (4) for ${\mathrm{V}}_{\mathrm{LP}}$ while ${\mathrm{I}}_{\mathrm{LP}}$ is found as in the previous topology:

$${\mathrm{I}}_{\mathrm{AP}}=\mathrm{K}\frac{1-{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(8)

Figure 3. The proposed LP/HP filter topology.

The HP current and voltage outputs are found as:

$${\mathrm{I}}_{\mathrm{HP}}=\mathrm{K}\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(9)

$${\mathrm{V}}_{\mathrm{HP}}=-{\mathrm{KR}}_2\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{\mathrm{I}}_{\mathrm{in}}$$

(10)

From Equations (9) and (10) it is seen that both of the gain and center frequency are electronically controllable while in the LP output only ${\mathrm{f}}_0$ is electronically controllable. Fortunately, the voltage and current outputs are available at low impedance Z ports and high impedance X ports of the used CVCIIs, respectively. It must be mentioned that although outputs in both the forms of current and voltage signals are produced, current and voltage signals of the same type are not simultaneously available. This can be considered as the main limitation of the proposed circuit. It also employs a floating capacitor, which is not desirable from the integration point of view.

3. Nonideal Analysis

The matrix operation of the used CVCII+s in a nonideal condition is shown in (11). Here, current gain between Y and X ports for CVCII₁⁺ is shown by $\mathsf{\beta }$, which has a close to unity value and it is shown by K for CVCII₂⁺, which is controllable by ${\mathrm{V}}_{\mathrm{con}}$. The nonideal voltage gain between the X and Z ports for CVCII₁⁺ and CVCII₂⁺ is shown by $\mathsf{\alpha }$ with a value close to unity. The parameters ${\mathrm{r}}_{\mathrm{x}}$ and ${\mathrm{r}}_{\mathrm{z}}$ are the parasitic impedances at the X and Z ports. In CVCII₁⁺ ${\mathrm{r}}_{\mathrm{y}}$ is the parasitic impedance at Y port which is controllable by ${\mathrm{I}}_{\mathrm{con}}$. For CVCII₂⁺ ${\mathrm{r}}_{\mathrm{y}}$ is a nonzero constant value in the range of a few Ω.

$$\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ {\mathrm{V}}_{\mathrm{Y}}\end{array}\right]=\left[\begin{array}{c}\mathsf{\beta }\left(K\right) 1/{\mathrm{r}}_{\mathrm{x}} 0\\ 0 \mathsf{\alpha } { \mathrm{r}}_{\mathrm{z}}\\ {\mathrm{r}}_{\mathrm{Y}} 0 0\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\mathrm{X}}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}\right]$$

(11)

Figure 4 shows the proposed LP/AP filter of Figure 2 in nonideal condition where all parasitic elements are modeled. The parasitic elements related to the CVCII₁⁺ are named ${\mathrm{r}}_{\mathrm{Y}1}$ and ${\mathrm{r}}_{\mathrm{X}1}$ while those related to the CVCII₂⁺ are named ${\mathrm{r}}_{\mathrm{Y}2}$ and ${\mathrm{r}}_{\mathrm{X}2}$.

Figure 4. The proposed LP/AP filter topology (shown in Figure 2) in nonideal condition.

By assuming ${\mathrm{r}}_{\mathrm{Y}2}\ll {\mathrm{R}}_1$ and ${\mathrm{r}}_{\mathrm{Y}2}\ll {\mathrm{r}}_{\mathrm{X}1}$, we have:

$${\mathrm{I}}_1=\frac{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}2}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(12)

$${\mathrm{I}}_2=\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(13)

Using (11)–(13) and assuming ${\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}2}\ll 1$, ${\mathrm{V}}_{\mathrm{x}1}$ and ${\mathrm{V}}_{\mathrm{LP}}$ are found, respectively, as:

$${\mathrm{V}}_{\mathrm{X}1}\approx -{\mathsf{\beta }}_1{\mathrm{R}}_1\left[\frac{1}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}\right]{\mathrm{I}}_{\mathrm{in}}$$

(14)

$${\mathrm{V}}_{\mathrm{LP}}\approx -{\mathsf{\beta }}_1{\mathsf{\alpha }}_1{\mathrm{R}}_1\left[\frac{1}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}\right]{\mathrm{I}}_{\mathrm{in}}$$

(15)

where ${\mathsf{\alpha }}_1$ and ${\mathsf{\beta }}_1$ are related to CVCII₁⁺.

Performing KCL at node 1 and using (14) and (15) results in:

$${\mathrm{I}}_{\mathrm{AP}}\approx {\mathsf{\beta }}_1\mathrm{K}\left[\frac{1-{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}-{\mathsf{\beta }}_1{\mathrm{r}}_{\mathrm{Y}2}\right)}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}\right]{\mathrm{I}}_{\mathrm{in}}$$

(16)

$${\mathrm{V}}_{\mathrm{AP}}\approx {\mathsf{\beta }}_1{\mathrm{K}\mathsf{\alpha }}_2({\mathrm{R}}_2//{\mathrm{r}}_{\mathrm{X}2})\left[\frac{1-{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}-{\mathsf{\beta }}_1{\mathrm{r}}_{\mathrm{Y}2}\right)}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}\right]{\mathrm{I}}_{\mathrm{in}}$$

(17)

where $\mathrm{K}$ and ${\mathsf{\alpha }}_2$ are current gain and voltage gains related to CVCII₂^+, respectively. The corresponding phase for the AP outputs is:

$$\mathsf{\phi }\left(\mathsf{\omega }\right)=180°-\arctan \left[{\mathsf{\omega }\mathrm{C}}_1\left({\mathrm{r}}_{\mathrm{Y}1}-{\mathsf{\beta }}_1{\mathrm{r}}_{\mathrm{Y}2}\right)\right]-\arctan \left[{\mathsf{\omega }\mathrm{C}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)\right]$$

(18)

From (18), it is noted that to reduce the effect of parasitic and nonideal elements on AP response, we must have ${\mathrm{r}}_{\mathrm{Y}1}\gg {\mathrm{r}}_{\mathrm{Y}2}$. This condition is easily met because ${\mathrm{r}}_{\mathrm{Y}1}$ and ${\mathrm{r}}_{\mathrm{Y}2}$ are in the range of a few kΩ and a few tens of Ω, respectively. The value of ${\mathsf{\beta }}_1$ is also close to unity.

Performing similar nonideal analysis for the LP/HP filter of Figure 3 results:

$${\mathrm{I}}_{\mathrm{LP}}={\mathsf{\beta }}_1\frac{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}2}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(19)

$${\mathrm{V}}_{\mathrm{LP}}=-{\mathsf{\beta }}_1{\mathrm{R}}_1{\mathsf{\alpha }}_1\frac{1+{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}2}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(20)

$${\mathrm{I}}_{\mathrm{HP}}=\mathrm{K}\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(21)

$${\mathrm{V}}_{\mathrm{HP}}=-\mathrm{K}({\mathrm{R}}_2//{\mathrm{r}}_{\mathrm{X}2}){\mathsf{\alpha }}_2\frac{{\mathrm{sC}}_1{\mathrm{r}}_{\mathrm{Y}1}}{1+{\mathrm{sC}}_1\left({\mathrm{r}}_{\mathrm{Y}1}+{\mathrm{r}}_{\mathrm{Y}2}\right)}{\mathrm{I}}_{\mathrm{in}}$$

(22)

4. Internal Implementation of the Used CVCIIs

A possible CMOS implementation of the used CVCII₁⁺ is shown in Figure 5a. Although here the current sources are shown as ideal for simplicity, in simulations they are implemented by simple current mirrors. The input section at the Y port is composed of the common gate transistor ${\mathrm{M}}_2$. The current sources ${\mathrm{I}}_{\mathrm{B}1}$ and ${\mathrm{I}}_{\mathrm{B}2}$ are used for biasing purposes, while ${\mathrm{I}}_{\mathrm{con}}$ is a variable current source which is used to set the value of impedance at the Y port. The diode connected transistor ${\mathrm{M}}_1$ provides proper bias voltage at ${\mathrm{M}}_1$ gate. The impedance at Y port can be expressed as:

$${\mathrm{r}}_{\mathrm{Y}1}=\frac{1}{{\mathrm{gm}}_{\mathrm{M}2}}$$

(23)

where ${\mathrm{gm}}_{\mathrm{M}2}$ (with usual meaning of symbols) is:

$${\mathrm{gm}}_{\mathrm{M}2}=\sqrt{{\mathsf{\mu }\mathrm{C}}_{\mathrm{ox}}\frac{{\mathrm{W}}_{\mathrm{M}2}}{{\mathrm{L}}_{\mathrm{M}2}}{\mathrm{I}}_{\mathrm{con}}}$$

(24)

Figure 5. CMOS implementation of the used (a) CVCII₁⁺ and (b) CVCII₂⁺.

As is seen from (24), the value of ${\mathrm{gm}}_{\mathrm{M}2}$ is controllable by ${\mathrm{I}}_{\mathrm{con}}$. Therefore, the appropriate value of the Y port impedance can be achieved by setting the value of ${\mathrm{I}}_{\mathrm{con}}$. To set zero offset voltage at the Y port, ${\mathrm{I}}_{\mathrm{con}}$ is also applied to the drain of ${\mathrm{M}}_1$, so the DC value of gate–source voltage of ${\mathrm{M}}_1$ and ${\mathrm{M}}_2$ is kept equal, resulting in zero DC offset voltage at Y port.

The input current applied to the Y terminal is transferred to the X terminal through a simple current mirror made of ${\mathrm{M}}_3–{\mathrm{M}}_4$. The voltage produced at the X port is transferred to the Z port through voltage buffer made of ${\mathrm{M}}_5–{\mathrm{M}}_9$ transistors. Here, the low impedance at the Z port is provided by negative feedback loop realized by ${\mathrm{M}}_9$. The CVCII₂⁺ shown in Figure 5b is formed by a series connection of a current buffer made of ${\mathrm{M}}_1–{\mathrm{M}}_7$, ${\mathrm{M}}_{6\mathrm{C}}–{\mathrm{M}}_{7\mathrm{C}}$ transistors and a voltage buffer formed by ${\mathrm{M}}_8–{\mathrm{M}}_{12}$ transistors. The required low impedance at the Y terminal is provided by negative feedback loop established with ${\mathrm{M}}_5$. By connecting the gate of ${\mathrm{M}}_1$ at the ground, the DC value of the Y port offset voltage is set at ground. The used degenerated current mirror, made of ${\mathrm{M}}_6$, ${\mathrm{M}}_{6\mathrm{C}}$, ${\mathrm{M}}_7$, ${\mathrm{M}}_{7\mathrm{C}}$ transistors, transfers the input current from Y to X terminals. As it was previously used in [39,40], by setting the value of ${\mathrm{V}}_{\mathrm{con}}$, the gain of the current mirror is tuned resulting in a variable current gain between Y and X ports. The current gain between X and Y terminals ($\mathrm{K}$) is expressed by (25) with usual meaning of symbols.

$$\mathrm{K}=\frac{{\mathrm{gm}}_{\mathrm{M}6}}{{\mathrm{gm}}_{\mathrm{M}7}}\frac{1+{\mathrm{gm}}_{\mathrm{M}6}{\mathrm{rds}}_{\mathrm{M}6\mathrm{C}}}{1+{\mathrm{gm}}_{\mathrm{M}7}{\mathrm{rds}}_{\mathrm{M}7\mathrm{C}}}$$

(25)

Similar to CVCII₁⁺ of Figure 5a, in the voltage buffer section, the voltage produced at the X terminal is transferred to the Z terminal through voltage buffer formed by the ${\mathrm{M}}_8–{\mathrm{M}}_{12}$ transistors. The negative feedback loop made of ${\mathrm{M}}_{12}$ provides low impedance at the Z port.

being:

$${\mathrm{rds}}_{\mathrm{M}7\mathrm{c}}=\frac{1}{{\mu \mathrm{C}}_{\mathrm{ox}}\frac{{\mathrm{W}}_{\mathrm{M}7\mathrm{C}}}{{\mathrm{L}}_{\mathrm{M}7\mathrm{C}}}\left({\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{con}}-\left|{\mathrm{V}}_{\mathrm{THP}}\right|\right)}$$

(26a)

$${\mathrm{rds}}_{\mathrm{M}6\mathrm{c}}=\frac{1}{{\mu \mathrm{C}}_{\mathrm{ox}}\frac{{\mathrm{W}}_{\mathrm{M}6\mathrm{C}}}{{\mathrm{L}}_{\mathrm{M}6\mathrm{C}}}\left({\mathrm{V}}_{\mathrm{dd}}-\left|{\mathrm{V}}_{\mathrm{THP}}\right|\right)}$$

(26b)

5. Simulation Results

The proposed electronically tunable LP/AP filter of Figure 2 and LP/HP filter of Figure 3 has been simulated using SPICE and 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V. The used transistors aspect ratios are reported in Table 1. The values of the bias current sources which are realized by simple current mirrors are reported in Table 2. The performance parameters of CVCII₁⁺ and CVCII₂⁺ are summarized in Table 3. The variation of CVCII₁⁺ Y port impedance (${\mathrm{r}}_{\mathrm{Y}1}$) by ${\mathrm{I}}_{\mathrm{con}}$ is shown in Figure 6. As is seen, by increasing ${\mathrm{I}}_{\mathrm{con}}$ from 0.5 µA to 50 µA the value of ${\mathrm{r}}_{\mathrm{Y}1}$ varies from 45 kΩ to 3.5 kΩ. The variation of CVCII₁⁺ power consumption is from 0.101 mW to 0.423 mW for ${\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA and ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA, respectively. The variation of CVCII₂⁺ current gain $\mathrm{K}$ versus ${\mathrm{V}}_{\mathrm{con}}$ is shown in Figure 7. As is seen, $\mathrm{K}$ falls from 30 to 1 while ${\mathrm{V}}_{\mathrm{con}}$ varies from −0.9 V to 0.185 V. The variation of CVCII₂⁺ power consumption is 0.284 mW and 0.634 mW for ${\mathrm{V}}_{\mathrm{con}}$ = 0.185 V and ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V, respectively.

Table 1. CVCII₁⁺ and CVCII₂⁺ main transistors aspect ratio and bias currents.

	W, L
	CVCII1+	CVCII2+
${\mathrm{M}}_1$$, {\mathrm{M}}_2$	4.5 µm, 4.5 µm	7.2 µm, 1.8 µm
${\mathrm{M}}_3$$, {\mathrm{M}}_4$	90 µm, 1.8 µm	9 µm, 1.8 µm
${\mathrm{M}}_5$	3.6 µm, 1.8 µm	270 µm, 0.9 µm
${\mathrm{M}}_6$	3.6 µm, 1.8 µm	5.04 µm, 0.54 µm
${\mathrm{M}}_7$	9 µm, 1.8 µm	50.4 µm, 0.54 µm
${\mathrm{M}}_8$	9 µm, 1.8 µm	7.2 µm, 1.8 µm
${\mathrm{M}}_9$	360 µm, 0.9 µm	7.2 µm, 1.8 µm
${\mathrm{M}}_{12}$	-	270 µm, 0.9 µm
${\mathrm{M}}_{6\mathrm{c}}$	-	0.9 µm, 0.54 µm
${\mathrm{M}}_{7\mathrm{c}}$	-	9 µm, 0.54 µm
${\mathrm{M}}_{10}$$, {\mathrm{M}}_{11}$	-	9 µm, 1.8 µm
${\mathrm{I}}_{\mathrm{b}1}$, ${\mathrm{I}}_{\mathrm{b}2}$	30 µA,30 µA	28 µA,7 µA
${\mathrm{I}}_{\mathrm{b}3}$, ${\mathrm{I}}_{\mathrm{b}4}$$, {\mathrm{I}}_{\mathrm{b}5}$	-	70 µA, 28 µA, 7 µA

Table 2. Performance parameters of the designed CVCII₁⁺ and CVCII₂⁺.

	CVCII1+	CVCII2+
${\mathrm{R}}_{\mathrm{Y}}$	$\mathrm{From} 45 \mathrm{K}\mathsf{\Omega } ({\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA) to $3.5 \mathrm{K}\mathsf{\Omega } ({\mathrm{I}}_{\mathrm{con}}$ = 50 µA)	81 Ω
${\mathrm{R}}_{\mathrm{X}}$	$\mathrm{From} 1.6 \mathrm{M}\mathsf{\Omega } ({\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA) to $286 \mathrm{K}\mathsf{\Omega } ({\mathrm{I}}_{\mathrm{con}}$ = 50 µA)	$\mathrm{From} 1 \mathrm{M}\mathsf{\Omega } ({\mathrm{V}}_{\mathrm{con}}$ = 0 V) to $96 \mathrm{k}\mathsf{\Omega } ({\mathrm{V}}_{\mathrm{con}}$ = −0.9 V)
${\mathrm{C}}_{\mathrm{Y}}$	$\mathrm{From} 117 \mathrm{fF} ({\mathrm{I}}_{\mathrm{con}}$ = 5 µA) to $123 \mathrm{fF} ({\mathrm{I}}_{\mathrm{con}}$ = 50 µA)	3.3 fF
${\mathrm{R}}_{\mathrm{Z}}$	54 Ω	57 Ω
DC offset at Y	11 mV	2.6 mV
DC offset at Z	5 mV	6 mV
DC offset at X	6 mV	−2.4 mV
$\mathsf{A}$	0.985	0.989
$\mathsf{{\rm B}}$	$0.993 \mathrm{for} {\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA and $0.965 \mathrm{for} {\mathrm{I}}_{\mathrm{con}}$ = 50 µA	9.5
Power	$101 \mu \mathrm{W} \mathrm{for} {\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA to $423 \mu \mathrm{W} \mathrm{for} {\mathrm{I}}_{\mathrm{con}}$ = 50 µW	$\mathrm{From} 284 \mu \mathrm{W} \mathrm{for} {\mathrm{V}}_{\mathrm{con}}$ = 0.185 V to $634 \mu \mathrm{W} \mathrm{for} {\mathrm{V}}_{\mathrm{con}}$ = −0.9 V

Table 3. Comparison between proposed circuit and other circuits reported in the literature.

Ref	ABB	#R	Floating C	# Transistors	VDD VSS	Pd (W)	Output	Match	Electronic Tunability		${\mathbf{f}}_0\left(\mathbf{Hz}\right)$
									${\mathbf{f}}_0$	G
[1]	1DXCCII	2	Yes 1	20	±1.25 V	2.1 m	${\mathrm{V}}_{\mathrm{AP}}$2	Yes	No	No	1.59 M
[2]	1DDCCII	1	Yes/No 3	18	±2.5 V	NA 4	${\mathrm{V}}_{\mathrm{AP}}$2	No	No	No	10 M
[10]	DV-DXCCII	2	Yes 1	30	±1.25 V	NA	${\mathrm{V}}_{\mathrm{AP}}$2	Yes	No	No	6.133 M
[12]	3CA	1	Yes	120	±5 V	25.7 m	${\mathrm{I}}_{\mathrm{AP}}$	No	No	Yes	100 k
[17]	1Dx-MOCCII	1	Yes	40	±1.25 V	NA	$\pm {\mathrm{I}}_{\mathrm{AP}}$$/{\mathrm{I}}_{\mathrm{HP}}$$/{\mathrm{I}}_{\mathrm{LP}}$	No	No	No	7.962 M
[18]	2OFCC	2	No	42	±1.5 V	NA	${\mathrm{I}}_{\mathrm{HP}}$$/{\mathrm{I}}_{\mathrm{LP}}$$/{\mathrm{I}}_{\mathrm{AP}}$	Yes	No	No	159 K
[19]	1DD-DXCCII	3	Yes	30	±1.2 V	NA	${\mathrm{I}}_{\mathrm{HP}}$$/{\mathrm{I}}_{\mathrm{LP}}$$/{\mathrm{I}}_{\mathrm{AP}}$	Yes	No	No	6.43 M
[21]	Current Mirror	0	No	10	±0.9 V	0.266 m	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	No	3 M
[22]	1ICCII	0	Yes	44	±0.75 V	2.75 m	${\mathrm{I}}_{\mathrm{LP}}$$/{\mathrm{I}}_{\mathrm{AP}}$$/{\mathrm{I}}_{\mathrm{HP}}$	No	Yes	No	2.6 M
[23]	Current Mirror	0	No	8	+1.5	0.169 m	${\mathrm{I}}_{\mathrm{AP}}$$/{\mathrm{I}}_{\mathrm{HP}}$	No	Yes	No	159 k
[24]	2CCCII	0	Yes	35	±2.5 V	NA	$+{\mathrm{I}}_{\mathrm{AP}}$$/-{\mathrm{I}}_{\mathrm{AP}}$	No	Yes	No	4.8 M
[25]	2CDTA	0	Yes	84	±2 V	9 m	$+{\mathrm{I}}_{\mathrm{AP}}$$/-{\mathrm{I}}_{\mathrm{AP}}$	No	Yes	No	1 M
[26]	2CCCCTA	0	No	54	±2.5 V	NA	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	Yes	<1 M
[27]	Modified CCCII	0	No	42	±2.5 V	NA	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	No	1 M
[28]	2CCCII	0	Yes	38	NA	NA	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	No	58 k 200 kHz
[29]	1Do-CCCII	0	Yes 1	42	±3 V	NA	$+{\mathrm{I}}_{\mathrm{AP}}$$/-{\mathrm{I}}_{\mathrm{AP}}$	Yes	Yes	No	1.632 M
[30]	1CCCTA	1	Yes 1	25	±1.5 V	NA	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	Yes	1.66 M
[31]	1CFCTA	1	No	35	±1.25 V	5.5 m	$\pm {\mathrm{I}}_{\mathrm{LP}}$	No	Yes	Yes	2 M
[32]	1CA+2CB	0	Yes	46	±1.2 V	3.88 m 5.29 m	${\mathrm{I}}_{\mathrm{AP}}$	No	Yes	Yes	1.41 M
[35]	1VCII±+1VCII+	3	No	34	±0.9 V	0.489 m	${\mathrm{V}}_{\mathrm{AP}}$$/{\mathrm{I}}_{\mathrm{AP}}$	Yes	No	No	1 M
Proposed#1	2CVCII+	2	Yes	36	±0.9 V	0.385 m 1.057 m	${\mathrm{I}}_{\mathrm{AP}}$$/{\mathrm{V}}_{\mathrm{AP}}$$/{\mathrm{V}}_{\mathrm{LP}}$	No	Yes 5	Yes	89 K–1 M
Proposed#2	2CVCII+	2	Yes	36	±0.9 V	0.385 m 1.057 m	${\mathrm{I}}_{\mathrm{HP}}$$/{\mathrm{V}}_{\mathrm{HP}}$$/{\mathrm{V}}_{\mathrm{LP}}$$/{\mathrm{I}}_{\mathrm{LP}}$	No	Yes	Yes	89 K–1 M

¹ Two floating compensation capacitors are used in the internal structure of the used active building blocks (ABB); ² Additional voltage buffer is required for ${\mathrm{V}}_{\mathrm{AP}}$ output; ³ There are two structures one with floating C and one without; ⁴ Not Available; ⁵ Only for AP outputs.

Figure 6. Variation of ${\mathrm{r}}_{\mathrm{Y}1}$ as a function of ${\mathrm{I}}_{\mathrm{con}}$ for CVCII₁⁺.

Figure 7. Variation of $\mathrm{K}$ as a function of ${\mathrm{V}}_{\mathrm{con}}$ for CVCII₂⁺.

In the filters presented in Figure 2 and Figure 3 we have set the values of ${\mathrm{C}}_1$, ${\mathrm{R}}_1$ and ${\mathrm{R}}_1$ as 20 pF, 15 kΩ and 1 kΩ, respectively. The frequency performance of LP output for three different values of ${\mathrm{I}}_{\mathrm{con}}$ is shown in Figure 8. It is seen that the −3 dB frequency is 89 kHz, 370 kHz and 1 MHz for ${\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA, ${\mathrm{I}}_{\mathrm{con}}$ = 5 µA and ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA, respectively. The low frequency gain value is about 83 dB. To test the time domain response of LP output, a sinusoidal input signal with peak to peak value of 10 µA and frequency of 1 MHz is used as input signal with ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA. The resulted total harmonic distortion (THD) is shown in Figure 9, which shows maximum value of 8% for THD at LP output.

Figure 8. Frequency performance of LP output for different values of ${\mathrm{I}}_{\mathrm{con}}$ for the filters represented in Figure 2a and Figure 3b.

Figure 9. Low-pass (LP) output total harmonic distortion (THD) value for a sinusoidal input signal with frequency of 1 MHz (${\mathrm{I}}_{\mathrm{con}}$ = 50 µA) at different values of input signal for the filter reported in Figure 2.

Figure 10 shows the gain and phase frequency performances of the ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ outputs for different values of ${\mathrm{I}}_{\mathrm{con}}$ and ${\mathrm{V}}_{\mathrm{con}}$ from which the electronic tunability of both frequency and gain is evident. To examine the time domain performance of the proposed AP filter, a sinusoidal input with peak-to-peak amplitude of 2 μA and frequency of 1 MHz is applied to the proposed circuit. For ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA and ${\mathrm{V}}_{\mathrm{con}}$ = 0 V, the input and output signals are shown in Figure 11, where an 87° phase shift for both produced ${\mathrm{I}}_{\mathrm{AP}}$ and ${\mathrm{V}}_{\mathrm{AP}}$ is found. In this case, THD is 2%.

Figure 10. Gain and phase frequency response of (a) ${\mathrm{V}}_{\mathrm{AP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = 0 V, (b) ${\mathrm{V}}_{\mathrm{AP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V, (c) ${\mathrm{I}}_{\mathrm{AP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = 0 and (d) ${\mathrm{I}}_{\mathrm{AP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V.

Figure 11. Time domain outputs for (a) ${\mathrm{I}}_{\mathrm{AP}}$ and (b) ${\mathrm{V}}_{\mathrm{AP}}$ in the case of ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA and ${\mathrm{V}}_{\mathrm{con}}$ = 0 V.

Figure 12 reports the frequency performances of ${\mathrm{I}}_{\mathrm{HP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$ outputs for different values of ${\mathrm{I}}_{\mathrm{con}}$ and ${\mathrm{V}}_{\mathrm{con}}$. The value of ${\mathrm{f}}_0$ for HP outputs is 81 kHz, 360 kHz and 1 MHz for ${\mathrm{I}}_{\mathrm{con}}$ = 0.5 µA, 5 µA and 50 µA, respectively. The gain of ${\mathrm{I}}_{\mathrm{HP}}$ varies from 0.980 dB to 29 dB for ${\mathrm{V}}_{\mathrm{con}}$ variation from 0.185 V to −0.9 V. For ${\mathrm{V}}_{\mathrm{HP}}$ gain, variation is from 60 dB to 88.9 dB. The THD values are 7.7% and 10% for ${\mathrm{I}}_{\mathrm{HP}}$ and ${\mathrm{V}}_{\mathrm{HP}}$ for input signal of 1 MHz and 5 µA peak to peak value and ${\mathrm{I}}_{\mathrm{con}}$ = 50 µA and ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V.

Figure 12. Gain frequency response of (a) ${\mathrm{I}}_{\mathrm{HP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = 0.185 V (b) ${\mathrm{I}}_{\mathrm{HP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V (c) ${\mathrm{V}}_{\mathrm{HP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = 0.185 V and (d) ${\mathrm{V}}_{\mathrm{HP}}$ for ${\mathrm{V}}_{\mathrm{con}}$ = −0.9 V at three different values of ${\mathrm{I}}_{\mathrm{con}}$ for the filter proposed in Figure 3.

A comparison between the proposed circuit and other previously reported ones is given in Table 3. As is seen, the proposed circuit offers many advantages, such as full electronic controllability, being free from any matching condition, versatility for providing both current and voltage signals, providing both LP and AP outputs and simple implementation compared to the available works. However, the proposed circuit employs a floating capacitor, which is not desirable from an integration point of view.

6. Conclusions

Two new electronically tunable first order LP/AP and LP/HP filter topologies based on two CVCIIs, two resistors and one capacitor have been presented. The first topology produces ${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{AP}}$/${\mathrm{V}}_{\mathrm{AP}}$ outputs and second topology produces ${\mathrm{I}}_{\mathrm{LP}}$/${\mathrm{V}}_{\mathrm{LP}}$/${\mathrm{I}}_{\mathrm{HP}}$/${\mathrm{V}}_{\mathrm{HP}}$ outputs. The ${\mathrm{f}}_0$ of LP output is electronically tunable while both ${\mathrm{f}}_0$ and gain of AP and HP outputs are fully electronically tunable using electronically variable VCII. The value of ${\mathrm{f}}_0$ is controlled by ${\mathrm{I}}_{\mathrm{con}}$, which is used to vary the Y port impedance of the first CVCII. The gains are also controlled by ${\mathrm{V}}_{\mathrm{con}}$, which is used to change the current gain of the second CVCII. The circuit is free from any matching condition. The total number of used transistors is only 36. Due to the circuit’s simplicity, the proposed circuit enjoys high frequency performance compared to its counterparts. The only drawback of the proposed circuit is that it employs a floating capacitor.