New Resistor-Less Electronically Controllable ± C Simulator Employing VCII, DVCC, and a Grounded Capacitor

: In this paper, a new realization of electronically controllable positive and negative ﬂoating capacitor multiplier ( ± C) is presented. The peculiarity of the presented topology is that, for the ﬁrst time, it implements a ﬂoating equivalent capacitor between its two input terminals, rather than a grounded one. To achieve the best performance, we simultaneously use the advantages provided by the current conveyor and its dual circuit, the voltage conveyor. The proposed topology is resistor free and employs one dual-output second-generation voltage conveyor (VCII ± ) and one electronically tunable differential voltage current conveyor (E-DVCC) as active building blocks (ABBs) and a single grounded capacitor. The value of the simulated capacitor is controlled by means of a control voltage V C which is used to control the current gain between X and Z terminals of E-DVCC. The circuit is free from any matching condition. A complete non-ideal analysis by considering parasitic impedances as well as non-ideal current and voltage gains of the used ABBs is presented. The proposed circuit is designed at the transistor level in 0.18 µ m and ± 0.9 V supply voltage. Simulation results using the SPICE program show a multiplication factor ranging from ± 10 to ± 25.4 with a maximum error of 0.56%. As an example, the application of the achieved ﬂoating capacitor as a standard high pass ﬁlter is also included.


Introduction
The advantages of capacitance multipliers in realizing large value capacitors in the CMOS process regarding the cost and chip size reduction are well known [1][2][3][4][5][6]. Capacitance multipliers find wide use in applications requiring large time constants, such as low-frequency filters in biomedical applications. In recent years, capacitor multiplier implementation has become a more important topic and several techniques have been developed to realize capacitor multipliers [7][8][9][10][11][12][13][14][15][16][17][18][19]. The feature of electronic tuning is considered a great advantage because it gives suitable tuning of filters, oscillators, and other circuits employing the simulated capacitor. Based on the intended application, simulated capacitors can be either grounded or floating.
In this paper, we intend to use the intrinsic capabilities of VCII in designing highperformance floating capacitor multipliers. To this aim, we introduce a new topology to implement a floating capacitor using a dual output VCII, an electronically controllable DVCC (which we call E-DVCC), and a grounded capacitor. In order to have an electronic tuning capability, the current gain between the X and Z terminals of E-DVCC is controlled using a control voltage, V C . Employing both VCII and DVCC in the proposed topology, the benefits of voltage conveyors and current conveyors are combined to achieve the desired properties of floating capacitance multiplication, low-voltage low-power operations, reduced associated parasitic elements, electronic tunability, low error, no matching condition, and simple circuitry. Both positive and negative multiplications can be implemented by the proposed circuit. A complete non-ideal analysis is given, and the SPICE simulation results are reported. The application of the proposed floating capacitor as a standard high pass filter is also given, as an application of study.
The organization of this paper is as follows: in Section 2, the proposed circuit is introduced; in Section 3, non-ideal analysis is performed; Section 4 shows the implementation of the active blocks; Section 5 includes the simulation results; and finally, Section 6 concludes the paper.

The Proposed VCII-Based Floating ±C Multiplier
The proposed VCII-based floating +C multiplier is shown in Figure 1. It is composed of one VCII ± , one E-DVCC, and a single grounded capacitor. Here, we use the intrinsic potential of voltage conveyors and current conveyors to achieve a high-performance floating capacitor multiplier. In the E-DVCC, the current gain between the X and Z terminals can be regulated by the voltage V C which allows us to electronically control the value of simulated +C. Consequently, as it will be shown, the value of the simulated floating capacitor can be varied by V C .
In this paper, we intend to use the intrinsic capabilities of VCII in designing highperformance floating capacitor multipliers. To this aim, we introduce a new topology to implement a floating capacitor using a dual output VCII, an electronically controllable DVCC (which we call E-DVCC), and a grounded capacitor. In order to have an electronic tuning capability, the current gain between the X and Z terminals of E-DVCC is controlled using a control voltage, VC. Employing both VCII and DVCC in the proposed topology, the benefits of voltage conveyors and current conveyors are combined to achieve the desired properties of floating capacitance multiplication, low-voltage low-power operations, reduced associated parasitic elements, electronic tunability, low error, no matching condition, and simple circuitry. Both positive and negative multiplications can be implemented by the proposed circuit. A complete non-ideal analysis is given, and the SPICE simulation results are reported. The application of the proposed floating capacitor as a standard high pass filter is also given, as an application of study.
The organization of this paper is as follows: in Section 2, the proposed circuit is introduced; in Section 3, non-ideal analysis is performed; Section 4 shows the implementation of the active blocks; Section 5 includes the simulation results; and finally, Section 6 concludes the paper.

The Proposed VCII-Based Floating ±C Multiplier
The proposed VCII-based floating +C multiplier is shown in Figure 1. It is composed of one VCII ± , one E-DVCC, and a single grounded capacitor. Here, we use the intrinsic potential of voltage conveyors and current conveyors to achieve a high-performance floating capacitor multiplier. In the E-DVCC, the current gain between the X and Z terminals can be regulated by the voltage VC which allows us to electronically control the value of simulated +C. Consequently, as it will be shown, the value of the simulated floating capacitor can be varied by VC.  In the following, we perform the analysis of the proposed circuit: operation the VCII ± is ideally expressed by the equations: while the following matrix represents the ideal operation of E-DVCC: Being K, the tunable current gain between the X and Z terminals. Using Equation (3a,b) for V Z+ and V Z− we have: where V 1 and V 2 are the input voltages. Using (2) and (3a,b) the voltage across C is: From Equation (4), the produced current across C is found as: The current produced across C is conveyed to the E-DVCC Z terminal while it is amplified by the gain of K as follows: As the Z terminal of E-DVCC is directly connected to the Y terminal of VCII ± , we have I Y = I Z . According to Equation (1), the current at Y terminal of VCII ± is conveyed to the X+ and X− terminals by gains of (+1) and (−1), respectively, so for I 1 and I 2 we have: From Equation (7a,b), the input impedance is found as: From which the equivalent capacitor is ideally: Figure 2 shows the realization of a floating negative capacitance simulator where, differently from Figure 1, Z+ and Z− terminals of VCII ± are respectively connected to Y 2 and Y 1 terminals of the E-DVCC. For Figure 2, it can be easily shown that the equivalent floating capacitor is ideally given C eq = −KC (10) Figure 3 shows a more detailed representation of the used ABBs showing the parasitic impedances associated with each port of VCII ± and E-DVCC. In non-ideal conditions, by considering these non-idealities, the operation of VCII ± is expressed by the following matrix:

Non-Ideal Analysis
where βv1 and βv2 are current gains between the Y and X+ terminals and between the Y and X− terminals, respectively, αv1 and αv2 are voltage gains between the X+ and Z+ terminals and between the X− and Z− terminals, respectively, with ideal values of unity. Parameters rY, rX+, rX−, rZ+, and rZ− are the low-frequency impedances at the Y, X+, X−, Z+, and Z− terminals, respectively. The ideal values of rY, rX+, rX−, rZ+, and rZ− are zero, infinite, infinite, zero, and zero, respectively. Matrix Equation (12) represents the real operation of E-DVCC: where αc1 is voltage gain between the Y1 and X terminals and αc2 is voltage gain between Y2 and X terminals, K is tunable current gain between the X and Z terminals, and rx and rz are low-frequency parasitic impedances at the X and Z terminals, respectively. The ideal value of αc1, αc2, rx, and rz are unity, unity, zero, and infinite, respectively. Figure 4 shows the proposed positive floating C simulator while all low-frequency parasitic impedances are considered.  Figure 3 shows a more detailed representation of the used ABBs showing the parasitic impedances associated with each port of VCII ± and E-DVCC. In non-ideal conditions, by considering these non-idealities, the operation of VCII ± is expressed by the following matrix:

Non-Ideal Analysis
where β v1 and β v2 are current gains between the Y and X+ terminals and between the Y and X− terminals, respectively, α v1 and α v2 are voltage gains between the X+ and Z+ terminals and between the X− and Z− terminals, respectively, with ideal values of unity. Parameters r Y , r X+ , r X− , r Z+ , and r Z− are the low-frequency impedances at the Y, X+, X−, Z+, and Z− terminals, respectively. The ideal values of r Y , r X+ , r X− , r Z+ , and r Z− are zero, infinite, infinite, zero, and zero, respectively. Matrix Equation (12) represents the real operation of E-DVCC:  where α c1 is voltage gain between the Y 1 and X terminals and α c2 is voltage gain between Y 2 and X terminals, K is tunable current gain between the X and Z terminals, and r x and r z are low-frequency parasitic impedances at the X and Z terminals, respectively. The ideal value of α c1 , α c2 , r x , and r z are unity, unity, zero, and infinite, respectively. Figure 4 shows the proposed positive floating C simulator while all low-frequency parasitic impedances are considered.
In Figure 4, for V Z+ and V Z− we have: Using Equation (13) and considering the fact that r Y1 >> r Z+ and r Y2 >> r Z− , for V Y1 and V Y2 we have: Using Equations (12)- (14), I C is found as: Assuming r Y << r Z , using Equations (12) and (15) we have:    According to Equation (11), neglecting the parasitic components (that is 1/r x± ∼ = 0), the current at Y terminal of VCII ± is conveyed to the X+ and X− terminals by gains of (+β v1 ) and (−β v2 ), respectively, and for I 1 and I 2 we have: In the worst case, β v1 and β v2 can be expressed as the following where ε << 1: Inserting Equation (18a) into Equation (17a) and Equation (18b) into Equation (17b) gives: Using Equation (19), the input admittance of the proposed circuit is found as: The parameters α c1 , α c2 , α v1 , and α v2 can be defined as Equation (21a-d) in which ε c << 1 and ε v << 1: Inserting Equation (21a-d) into Equation (20) and simplifying the equation gives: From Equation (22), the value of C eq is found as: As can be seen, the non-ideal gains have a negligible effect on the value of C eq , and in addition, using K, the value of C eq is adjustable.
The value of the series of the parasitic capacitance of the simulated capacitor is found as: As can be seen from Equation (24), the value of R seri is reduced by increasing multiplication factor K. The equivalent circuit of the proposed capacitor multiplier is shown in Figure 5 where C eq is the proposed electronically tunable equivalent floating capacitance. r x± is the parasitic parallel resistances of the X± terminals, and R seri is the parasitic series resistance of the simulated capacitor. A similar analysis can be performed for negative floating C.

= (1 ∓ )
Inserting Equation (21a-d) into Equation (20) and simplifying the equation g = 1 + 1 ± ± = 1 1 ± ± + 1 ± ± From Equation (22), the value of Ceq is found as: As can be seen, the non-ideal gains have a negligible effect on the value of Ceq addition, using K, the value of Ceq is adjustable.
The value of the series of the parasitic capacitance of the simulated capacitor i as:

= 1 ± ±
As can be seen from Equation (24), the value of Rseri is reduced by increasing plication factor K. The equivalent circuit of the proposed capacitor multiplier is sh Figure 5 where Ceq is the proposed electronically tunable equivalent floating capa rx± is the parasitic parallel resistances of the X± terminals, and Rseri is the parasiti resistance of the simulated capacitor. A similar analysis can be performed for n floating C.

The CMOS Implementation of VCII ± and E-DVCC
A realization of the internal structure of VCII ± is shown in Figure 6. The low ance at the Y port is provided by the negative feedback loop made by the M1-M5 tors. The input current to the Y port is transferred to the X+ port by a simple curren M6-M7. The voltage produced at the X+ node is transferred to the Z+ port by voltag made by M8-M12. Similarly, the Y port input current is reversed by the current M14-M15, and transferred to the X− port. The voltage at the X− port is transferred t port by M16-M20. The transistor-level implementation of an electronically tunable E is shown in Figure 7. The difference between input voltages V1 and V2 is produced impedance X port utilizing the negative feedback loop established by differentia

The CMOS Implementation of VCII ± and E-DVCC
A realization of the internal structure of VCII ± is shown in Figure 6. The low impedance at the Y port is provided by the negative feedback loop made by the M 1 -M 5 transistors. The input current to the Y port is transferred to the X+ port by a simple current mirror M 6 -M 7 . The voltage produced at the X+ node is transferred to the Z+ port by voltage buffer made by M 8 -M 12 . Similarly, the Y port input current is reversed by the current mirror, M 14 -M 15 , and transferred to the X− port. The voltage at the X− port is transferred to the Z − port by M 16 -M 20 . The transistor-level implementation of an electronically tunable E-DVCC is shown in Figure 7. The difference between input voltages V 1 and V 2 is produced at low impedance X port utilizing the negative feedback loop established by differential pairs, M 1 -M 2 and M 3 -M 4 , along with M 5 -M 7 transistors as reported in [27]. In the previously reported works, DVCC is used while the gain between the X and Z terminals is unity. Here, we add a gain cell between the X and Z terminals to electronically tune the current at the Z terminal. The used gain cell is a variable gain current mirror previously reported in [35].
M1-M2 and M3-M4, along with M5-M7 transistors as reported in [27]. In the previously reported works, DVCC is used while the gain between the X and Z terminals is unity. Here, we add a gain cell between the X and Z terminals to electronically tune the current at the Z terminal. The used gain cell is a variable gain current mirror previously reported in [35].
The current of the X terminal is transferred to the gain cell using the current mirror made of M7-M7C and M8-M8C. As was described in [35], the current gain between the X and a Z terminal is tunable by control voltage VC, expressed as: being: where, according to the usual meaning of symbols, gmi and rdsi represent the transconductance and the drain-source resistance of the ith transistor, respectively, µ is the mobility of the carriers, Cox represents the capacitance per unit of area of the specific fabrication technology, W/Li is the ratio between the width and the length of the ith transistor, and VTH is the threshold voltage that is a technology-dependent parameter.
As it is seen from (26a), the current gain is controllable by VC.

Simulation Results
The proposed floating capacitor of Figure 1 is simulated in 0.18 µm CMOS technology and supply voltage of ±0.9 V using the SPICE program. The used aspect ratios are reported in Table 1. All current sources are implemented by simple current mirrors with aspect ratio of W = 9 µm and L = 0.72 µm with the values of IB1 = IB2 = IB3 = 30 µA, IB4 = 31.4 µA. The performance parameters of VCII and E-DVCC are reported in Table 2.  The current of the X terminal is transferred to the gain cell using the current mirror made of M 7 -M 7C and M 8 -M 8C . As was described in [35], the current gain between the X and a Z terminal is tunable by control voltage V C , expressed as: being: and where, according to the usual meaning of symbols, gm i and rds i represent the transconductance and the drain-source resistance of the ith transistor, respectively, µ is the mobility of the carriers, C ox represents the capacitance per unit of area of the specific fabrication technology, W/L i is the ratio between the width and the length of the ith transistor, and V TH is the threshold voltage that is a technology-dependent parameter.
As it is seen from (26a), the current gain is controllable by V C .

Simulation Results
The proposed floating capacitor of Figure 1 is simulated in 0.18 µm CMOS technology and supply voltage of ±0.9 V using the SPICE program. The used aspect ratios are reported in Table 1. All current sources are implemented by simple current mirrors with aspect ratio of W = 9 µm and L = 0.72 µm with the values of I B1 = I B2 = I B3 = 30 µA, IB4 = 31.4 µA. The performance parameters of VCII and E-DVCC are reported in Table 2.
The value of C is set at 10 pF. To verify the functionality of the proposed circuit, the plot of impedance magnitude and phase response of the simulated floating capacitor and the ideal one are shown in Figure 8. By changing the value of V C from −0.9 V to 0 V, different multiplication factors are set. The frequency operation range of the proposed circuit results is equal to about two decades (from 10 kHz to 1 MHz). The maximum error value for different control voltages is shown in Table 3. As can be seen, the maximum error value is only 0.56%. The application of the proposed floating capacitor as a high pass filter is shown in Figure 9. The frequency response of the high pass filter for different control voltages is shown in Figure 10             A comparison between the proposed circuit and other previously reported ones is presented in Table 4. As can be seen, the proposed circuit outperforms previous works in terms of reduced supply voltage, resistor-free structure, electronic tunability, reduced error, and simplicity.

Conclusions
In this paper, we present a new resistor-free topology for implementing either a positive or negative floating capacitor multiplier with electronic tuning capability. One VCII ± , one E-DVCC, and a single grounded capacitor are used. Using an electronically tunable current gain stage between the X and Z terminals of the E-DVCC, various multiplication factors are achieved. The circuit enjoys low voltage operation and offers reduced error compared with other works. A non-ideal analysis is given by taking into account non-ideal gains and parasitic impedances of the used active elements. The proposed circuit is free from any restricting matching requirements. The application of the proposed circuit as a standard high pass filter is also given to verify its functionality.