Search Results (6)

The recent trend in analog design to replace typical analog circuits with digital implementations has led to the use of resistive feedback to pull a CMOS inverter into the switching threshold region to achieve gain, which is ideal for analog operations. Here, we report a three-transistor (3T) CMOS resistive-feedback inverter-based amplifier capable of achieving high gain paralleled with reduced noise, low power consumption, and enhanced stability. Unlike conventional resistive-feedback inverter-based amplifiers, the transistors are operated in the subthreshold region, which allows for a lower supply voltage and current, leading to lower power consumption. Subthreshold conduction also reduces typical amplifier noise sources. This design provides a novel approach to resistive feedback in the inverter amplifier, allowing for a large gain while occupying minimal layout area. The reported amplifier design facilitates unique capabilities, e.g., detection of ultra-low (fC) charges or sub-pA currents for newly emerging PHz electronic and optoelectronic devices driven by few-cycle laser pulses. As proof of concept, the specifications of the proposed amplifier are successfully measured and verified by multiple test chips designed and fabricated in TSMC’s 180 nm CMOS process. The fabricated amplifier operates at a 1.35 V power supply with a measured voltage gain of 53.61 dB (or 480 V/V), a bandwidth of 94 kHz, and an equivalent input voltage noise of 6.4 nV/$\sqrt{\mathrm{Hz}}$, consuming only 13.5 µW. Full article

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 $\mathsf{\mu }$m × 65 $\mathsf{\mu }$m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 $\mathsf{\mu }{V}_{rms}$. Power consumption is also tested, with a measured value of 3.77 $\mathsf{\mu }$W per channel, corresponding to an overall consumption of about 60 $\mathsf{\mu }$W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results. Full article

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a $1/f$ noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 $\mathrm{n}$$\mathrm{m}$ CMOS technology. The cascaded receiver achieves a conversion-gain from 26 $\mathrm{d}$$\mathrm{B}$ to 36 $\mathrm{d}$$\mathrm{B}$, a double-sideband noise-figure (NFDSB) from $1.4$ $\mathrm{d}$$\mathrm{B}$ to $3.9$ $\mathrm{d}$$\mathrm{B}$, ${\mathrm{S}}_{11}<$$-10$ $\mathrm{d}$$\mathrm{B}$ and an IIP3 from $-7.5$ $\mathrm{d}$$\mathrm{Bm}$ to $-10.5$ $\mathrm{d}$$\mathrm{Bm}$, over the RF operating band from $0.4$ $\mathrm{G}$$\mathrm{Hz}$ to 12 $\mathrm{G}$$\mathrm{Hz}$. The stacked receiver achieves a conversion-gain from $34.5$ $\mathrm{d}$$\mathrm{B}$ to 36 $\mathrm{d}$$\mathrm{B}$, a NFDSB from $4.6$ $\mathrm{d}$$\mathrm{B}$ to $6.2$ $\mathrm{d}$$\mathrm{B}$, ${\mathrm{S}}_{11}<$$-10$ $\mathrm{d}$$\mathrm{B}$, and an IIP3 from $-21$ $\mathrm{d}$$\mathrm{Bm}$ to $-17.5$ $\mathrm{d}$$\mathrm{Bm}$, over the RF operating band from $2.2$ $\mathrm{G}$$\mathrm{Hz}$ to $3.2$ $\mathrm{G}$$\mathrm{Hz}$. The cascaded receiver consumes 11 m from a 1 $\mathrm{V}$ supply voltage, while the stacked receiver consumes $2.4$ m from a $1.2$ $\mathrm{V}$ supply voltage. Full article

In a recent work (Antonov et al., Physical Review Letters 123, 243903 (2019)), it was shown that it is possible to amplify a train of attosecond pulses, which are produced from the radiation of high harmonics of the infrared field of the fundamental frequency, in the active medium of a plasma-based X-ray laser modulated by a replica of the infrared field of the same frequency. In this paper, we show that much higher amplification can be achieved using the second harmonic of the fundamental frequency for modulating of a hydrogen-like active medium. The physical reason for such enhanced amplification is the possibility to use all (even and odd) sidebands induced in the gain spectrum in the case of the modulating field of the doubled fundamental frequency, while only one set of sidebands (either even or odd) could participate in amplification in the case of the modulating field of the fundamental frequency due to the fact that the spectral components of the high-harmonic field are separated by twice the fundamental frequency. Using the plasma of hydrogen-like C⁵⁺ ions with an inverted transition wavelength of 3.38 nm in the water window as an example, it is shown that the use of a modulating field at a doubled fundamental frequency makes it possible to increase the intensity of amplified attosecond pulses by an order of magnitude in comparison with the previously studied case of a fundamental frequency modulating field. Full article

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm². The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm². The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V. Full article

An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power. Full article