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Keywords = full well capacity (FWC)

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26 pages, 4969 KiB  
Review
A Review of Recent Advances in High-Dynamic-Range CMOS Image Sensors
by Jingyang Chen, Nanbo Chen, Zhe Wang, Runjiang Dou, Jian Liu, Nanjian Wu, Liyuan Liu, Peng Feng and Gang Wang
Chips 2025, 4(1), 8; https://doi.org/10.3390/chips4010008 - 3 Mar 2025
Cited by 1 | Viewed by 5395
Abstract
High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and [...] Read more.
High-dynamic-range (HDR) technology enhances the capture of luminance beyond the limits of traditional images, facilitating the capture of more nuanced and lifelike visual effects. This advancement has profound implications across various sectors, such as medical imaging, augmented reality (AR), virtual reality (VR), and autonomous driving systems. The evolution of complementary metal-oxide semiconductor (CMOS) image sensor (CIS) manufacturing techniques, particularly through backside illumination (BSI) and advancements in three-dimensional (3D) stacking architectures, is driving progress in HDR’s capabilities. This paper provides a review of the technologies developed over the past six years that augment the dynamic range (DR) of CIS. It systematically introduces and summarizes the implementation methodologies and distinguishing features of each technology. Full article
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12 pages, 4414 KiB  
Article
Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity
by Ken Miyauchi, Toshiyuki Isozaki, Rimon Ikeno and Junichi Nakamura
Sensors 2023, 23(21), 8847; https://doi.org/10.3390/s23218847 - 31 Oct 2023
Cited by 2 | Viewed by 2504
Abstract
In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical [...] Read more.
In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement. Full article
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13 pages, 4443 KiB  
Communication
A Thin-Film Pinned-Photodiode Imager Pixel with Fully Monolithic Fabrication and beyond 1Me- Full Well Capacity
by Joo Hyoung Kim, Francois Berghmans, Abu Bakar Siddik, Irem Sutcu, Isabel Pintor Monroy, Jehyeok Yu, Tristan Weydts, Epimitheas Georgitzikis, Jubin Kang, Yannick Baines, Yannick Hermans, Naresh Chandrasekaran, Florian De Roose, Griet Uytterhoeven, Renaud Puybaret, Yunlong Li, Itai Lieberman, Gauri Karve, David Cheyns, Jan Genoe, Paweł E. Malinowski, Paul Heremans, Kris Myny, Nikolas Papadopoulos and Jiwon Leeadd Show full author list remove Hide full author list
Sensors 2023, 23(21), 8803; https://doi.org/10.3390/s23218803 - 29 Oct 2023
Cited by 2 | Viewed by 3954
Abstract
Thin-film photodiodes (TFPD) monolithically integrated on the Si Read-Out Integrated Circuitry (ROIC) are promising imaging platforms when beyond-silicon optoelectronic properties are required. Although TFPD device performance has improved significantly, the pixel development has been limited in terms of noise characteristics compared to the [...] Read more.
Thin-film photodiodes (TFPD) monolithically integrated on the Si Read-Out Integrated Circuitry (ROIC) are promising imaging platforms when beyond-silicon optoelectronic properties are required. Although TFPD device performance has improved significantly, the pixel development has been limited in terms of noise characteristics compared to the Si-based image sensors. Here, a thin-film-based pinned photodiode (TF-PPD) structure is presented, showing reduced kTC noise and dark current, accompanied with a high conversion gain (CG). Indium-gallium-zinc oxide (IGZO) thin-film transistors and quantum dot photodiodes are integrated sequentially on the Si ROIC in a fully monolithic scheme with the introduction of photogate (PG) to achieve PPD operation. This PG brings not only a low noise performance, but also a high full well capacity (FWC) coming from the large capacitance of its metal-oxide-semiconductor (MOS). Hence, the FWC of the pixel is boosted up to 1.37 Me- with a 5 μm pixel pitch, which is 8.3 times larger than the FWC that the TFPD junction capacitor can store. This large FWC, along with the inherent low noise characteristics of the TF-PPD, leads to the three-digit dynamic range (DR) of 100.2 dB. Unlike a Si-based PG pixel, dark current contribution from the depleted semiconductor interfaces is limited, thanks to the wide energy band gap of the IGZO channel material used in this work. We expect that this novel 4 T pixel architecture can accelerate the deployment of monolithic TFPD imaging technology, as it has worked for CMOS Image sensors (CIS). Full article
(This article belongs to the Section Sensing and Imaging)
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16 pages, 6991 KiB  
Article
An Optical Filter-Less CMOS Image Sensor with Differential Spectral Response Pixels for Simultaneous UV-Selective and Visible Imaging
by Yhang Ricardo Sipauba Carvalho da Silva, Rihito Kuroda and Shigetoshi Sugawa
Sensors 2020, 20(1), 13; https://doi.org/10.3390/s20010013 - 18 Dec 2019
Cited by 6 | Viewed by 7958
Abstract
This paper presents a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) capable of capturing UV-selective and visible light images simultaneously by a single exposure and without employing optical filters, suitable for applications that require simultaneous UV and visible light imaging, or UV imaging in [...] Read more.
This paper presents a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) capable of capturing UV-selective and visible light images simultaneously by a single exposure and without employing optical filters, suitable for applications that require simultaneous UV and visible light imaging, or UV imaging in variable light environment. The developed CIS is composed by high and low UV sensitivity pixel types, arranged alternately in a checker pattern. Both pixel types were designed to have matching sensitivities for non-UV light. The UV-selective image is captured by extracting the differential spectral response between adjacent pixels, while the visible light image is captured simultaneously by the low UV sensitivity pixels. Also, to achieve high conversion gain and wide dynamic range simultaneously, the lateral overflow integration capacitor (LOFIC) technology was introduced in both pixel types. The developed CIS has a pixel pitch of 5.6 µm and exhibits 172 µV/e conversion gain, 131 ke full well capacity (FWC), and 92.3 dB dynamic range. The spectral sensitivity ranges of the high and low UV sensitivity pixels are of 200–750 nm and 390–750 nm, respectively. The resulting sensitivity range after the differential spectral response extraction is of 200–480 nm. This paper presents details regarding the CIS pixels structures, doping profiles, device simulations, and the measurement results for photoelectric response and spectral sensitivity for both pixel types. Also, sample images of UV-selective and visible spectral imaging using the developed CIS are presented. Full article
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16 pages, 5782 KiB  
Article
A High Full Well Capacity CMOS Image Sensor for Space Applications
by Woo-Tae Kim, Cheonwi Park, Hyunkeun Lee, Ilseop Lee and Byung-Geun Lee
Sensors 2019, 19(7), 1505; https://doi.org/10.3390/s19071505 - 28 Mar 2019
Cited by 17 | Viewed by 9341
Abstract
This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel [...] Read more.
This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel and accumulated charges in a photodiode are transferred to the in-pixel capacitor multiple times depending on the maximum incident light intensity. In addition, the modulation transfer function (MTF) and radiation damage effect on the pixel, which are especially important for space applications, are studied and analyzed through fabrication of the CIS. The CIS was fabricated using a 0.11 μm 1-poly 4-metal CIS process to demonstrate the proposed techniques and pixel design. A measured FWC of 103,448 electrons and MTF improvement of 300% are achieved with 6.5 μm pixel pitch. Full article
(This article belongs to the Special Issue Advanced CMOS Image Sensors and Emerging Applications)
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13 pages, 8714 KiB  
Article
A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel
by Seiji Takahashi, Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu, Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Wei-Chieh Chiang, Chun-Hao Chuang, Keng-Yu Chou, Chi-Hsien Chung, Kuo-Yu Chou, Chien-Hsien Tseng, Chuan-Joung Wang and Dun-Nien Yaung
Sensors 2017, 17(12), 2816; https://doi.org/10.3390/s17122816 - 5 Dec 2017
Cited by 33 | Viewed by 15212
Abstract
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of [...] Read more.
A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e/s at 60 °C, an ultra-low read noise of 0.90 e·rms, a high full well capacity (FWC) of 4100 e, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. Full article
(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))
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