Search Results (6)

To solve the application limitations of conventional detectors caused by discrete phase distribution of high-order APSK signals, and the problem that the detection performance will degrade when the automatic control gain is unideal, a carrier synchronization lock detector based on weighted detection statistics is proposed for APSK signals. Based on the detection statistics of the Linn detector, the proposed detector calculates a weighted factor according to the amplitude difference of the signal on the APSK constellation to adjust the weight of detection statistics for different rings. The proposed detector solves the detection performance degradation problem of the Linn detector caused by uneven phase distribution. In order to further improve detection performance, the detection threshold and statistical signal length are reasonably designed. The expectation and variance properties are derived, and the lock detection probability is analyzed. The performance of the proposed detector is verified through simulations. Simulation results show that the proposed carrier synchronization lock detector has better performance than the Linn detector. Full article

This paper proposed a 5.42~6.28 GHz type-II phase locked loop (PLL) for the sake of both loop filter switching capability and extensive programmability. An on-chip loop filter is used in conjunction with off-chip one to form a switching filter pair for diverse application scenarios. In order to strike a balance between dead-zone elimination and noise contribution minimization, a 3-bit programmable reset time ranging from 25 ps to 200 ps with a step of 25 ps is brought into PFD (phase frequency detector) design while CP (charge pump) current is programmable from 200 μA to 900 μA with a 100 μA/step digital control. Power management units (PMU) including bandgap and low dropout regulators (LDO) are integrated on-chip with resistor string trimming which effectively counteracts fabrication variations. In addition, a piecewise linear VCO with 3-bit control is designed with a fully digital 6-bit multi-modulus divider (MMD) chain cascaded. The proposed PLL is implemented in a 40-nm bulk CMOS process and the power consumption is 8 mA@1.2 V, in which around 5 mA@1.2 V is consumed by output buffers. The fabricated PLL chip achieves a frequency tuning range of 5.42~6.28 GHz, a phase noise ranging from −107.2~−110.4 dBc/Hz@1 MHz offset from carrier, a reference spur of lower than −70 dBc when on-chip active loop filter bandwidth is set to be around 500 KHz. Its FoM is approximately −176.98~−180.18 dBc/Hz while FoM_T is approximately −180.32~−183.52 dBc/Hz@1 MHz offset from carrier. Its most specifications are comparable to or better than most existing literature. Full article

We present a new ultra-tightly coupled (UTC) integration architecture of a micro-electromechanical inertial measurement unit (MIMU) and global navigation satellite system (GNSS) to reduce the performance degradation caused by abrupt changes of frequency tracking errors. A large frequency error will lead to a decrease in the carrier-to-noise ratio (C/N₀) estimate and an increase in the code discriminator estimation error. The disruptive effects of frequency errors on the estimation of C/N₀ and on the code discriminator are quantitatively evaluated via theoretical analyses and Monte Carlo simulations. The new MIMU/GNSS UTC architecture introduces a large frequency error detector and a refined frequency processor based on a retuned frequency in each tracking channel. In addition, an adaptive channel prefilter with multiple fading factors is introduced as an alternate to the conventional prefilter. Numerical simulations based on a highly dynamic trajectory are used to assess performance. The simulation results show that when there is an abrupt step change in the frequency tracking error, the new UTC architecture can effectively suppress the divergence of navigation solutions and the loss of tracking lock, and can significantly reduce the deviation of the C/N₀ estimation. Full article

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm${}^2$ including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits. Full article

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier. Full article

Frequency-locked detector (FLD) has been widely utilized in tracking loops of Global Positioning System (GPS) receivers to indicate their locking status. The relation between FLD and lock status has been seldom discussed. The traditional PLL experience is not suitable for FLL. In this paper, the threshold setting criteria for frequency-locked detector in the GPS receiver has been proposed by analyzing statistical characteristic of FLD output. The approximate probability distribution of frequency-locked detector is theoretically derived by using a statistical approach, which reveals the relationship between probabilities of frequency-locked detector and the carrier-to-noise ratio (C/N₀) of the received GPS signal. The relationship among mean-time-to-lose-lock (MTLL), detection threshold and lock probability related to C/N₀ can be further discovered by utilizing this probability. Therefore, a theoretical basis for threshold setting criteria in frequency locked loops for GPS receivers is provided based on mean-time-to-lose-lock analysis. Full article