Search Results (74)

Photovoltaic (PV) energy is gaining traction due to its direct conversion of sunlight to electricity without harming the environment. It is simple to install, adaptable in size, and has low operational costs. The power output of PV modules varies with solar radiation and cell temperature. To optimize system efficiency, it is crucial to track the PV array’s maximum power point. This paper presents a novel fixed-point FPGA design of a nonlinear maximum power point tracking (MPPT) controller based on synergetic control theory for driving autonomously standalone photovoltaic systems. The proposed solution addresses the chattering issue associated with the sliding mode controller by introducing a new strategy that generates a continuous control law rather than a switching term. Because it requires a lower sample rate when switching to the invariant manifold, its controlled switching frequency makes it better suited for digital applications. The suggested algorithm is first emulated to evaluate its performance, robustness, and efficacy under a standard benchmarked MPPT efficiency (${\eta }_{MPPT}$) calculation regime. FPGA has been used for its capability to handle high-speed control tasks more efficiently than traditional micro-controller-based systems. The high-speed response is critical for applications where rapid adaptation to changing conditions, such as fluctuating solar irradiance and temperature levels, is necessary. To validate the effectiveness of the implemented synergetic controller, the system responses under variant meteorological conditions have been analyzed. The results reveal that the synergetic control algorithm provides smooth and precise MPPT. Full article

In this paper, we present the logic designs of two FPGA hardware programming algorithms implemented for a Coherent Doppler Lidar system used in wind sensing. The first algorithm divides the received time-domain signals into segments, each corresponding to a specific spatial resolution. It then calculates the power spectrum for each segment and accumulates these spectra over 10,000 pulse returns. The second algorithm computes the autocorrelation of the received signals and accumulates the results over the same number of pulses. Both signal pre-processing algorithms are initially developed as logic designs and compiled using the Xilinx System Generator toolset to produce a hardware VLSI image. This image is subsequently programmed into an FPGA. However, the hardware implementation of these algorithms presents several challenges: (1) bit growth: multiplication operations in the binary number system significantly increase the number of bits, complicating hardware implementation. (2) Memory constraints: onboard RAM arrays of sufficient size are lacking for accumulating vectors of the calculated Fast Fourier Transforms (FFTs) or autocorrelations. (3) Signal drive issues: large fan-out in the logic design leads to significant capacitance, restricting the driving capabilities of transistor output signals. This article discusses the solutions devised to overcome these challenges. Additionally, it presents atmospheric wind measurements obtained using the two algorithms. Full article

Multiple serial interfaces have emerged to meet system requirements across devices, ranging from slower-speed buses, such as I²C, to high throughput serial interfaces, like JESD204. To address the need for a medium-speed protocol and to resolve I²C shortcomings, the MIPI Alliance developed the I3C specification, which is a royalty-free next-generation version of I²C with new features and backward compatibility. Since the MIPI Alliance’s I3C work only includes the specifications, it depends on third-party vendors to develop their own cores according to the specifications. Only a few processing systems contain I3C Controllers, each with its own partial implementation of the specification, and there are no open-source controller cores. Thus, this work presents an open-source I3C Controller HDL framework that operates at the maximum specified SDR frequency and is compatible with the Linux kernel. Both the core and Linux kernel drivers are available under permissive open-source licenses. The solution is mostly aimed at development boards with Xilinx Zynq and Intel Cyclone SoC; nevertheless, the structure of the project allows it to be ported to other vendors and carriers. Full article

Nowadays, M-Quadrature Amplitude Modulation (M-QAM) techniques are widely used to modulate information by bit packets due to their ability to increase transfer rates. These techniques require more power when increasing the modulation index M to avoid interference between symbols. This article proposes a technique that does not suffer from interference between symbols, but instead uses memory elements to store the modulation symbols. In addition, the aim of this paper is to implement a four-dimensional reconfigurable chaotic oscillator that generates 16-Chaotic Phase Shift Keying (16-CPSK) modulation–demodulation carriers. An encryption and modulation transmitter module, a reception module, and a master–slave Hamiltonian synchronization module make up the system. A 16-CPSK modulation scheme implemented in Field Programmable Gate Array (FPGA) and applied to a red-green-blue (RGB) and grayscale image encryption system are the main contributions of this work. Matlab and Vivado were used to verify the modulation–demodulation scheme and synchronization. This proposal achieved excellent correlation coefficients according to various investigations, the lowest being $-15.9\times {10}^{-6}$ and $0.13\times {10}^{-3}$ for RGB and grayscale format images, respectively. The FPGA implementation of the 16-CPSK modulation–demodulation system was carried out using a manufacturer’s card, Xilinx’s Artix-7 AC701 (XC7A200TFBG676-2). Full article

This paper addresses critical gaps in the digital implementations of fractional-order memelement emulators, particularly given the challenges associated with the development of solid-state devices using nanomaterials. Despite the potentials of these devices for industrial applications, the digital implementation of fractional-order models has received limited attention. This research contributes to bridging this knowledge gap by presenting the FPGA realization of the memelements based on a universal voltage-controlled circuit topology. The digital emulators successfully exhibit the pinched hysteresis behaviors of memristors, memcapacitors, and meminductors, showing the retention of historical states of their constitutive electronic variables. Additionally, we analyze the impact of the fractional-order parameters and excitation frequencies on the behaviors of the memelements. The design methodology involves using Xilinx System Generator for DSP blocks to lay out the architectures of the emulators, with synthesis and gate-level implementation performed on the Xilinx Artix-7 AC701 Evaluation kit, where resource utilization on hardware accounts for about $1\%$ of available hardware resources. Further hardware analysis shows successful timing validation and low power consumption across all designs, with an average on-chip power of 0.23 Watts and average worst negative slack of 0.6 ns against a 5 ns constraint. We validate these results with Matlab 2020b simulations, which aligns with the hardware models. Full article

Advancements in technology have driven the miniaturization of embedded systems, making them more cost-effective and energy-efficient for wireless applications. As a result, the number of connectable devices in Internet of Things (IoT) networks has increased significantly, creating the challenge of linking them effectively and economically. The space industry has long recognized this challenge and invested in satellite infrastructure for IoT networks, exploiting the potential of edge computing technologies. In this context, it is of critical importance to enhance the onboard computing capabilities of satellites and develop enabling technologies for their advancement. This is necessary to ensure that satellites are able to connect devices while reducing latency, bandwidth utilization, and development costs, and improving privacy and security measures. This paper presents the GPU@SAT DevKit: an ecosystem for testing a high-performance, general-purpose accelerator designed for FPGAs and suitable for edge computing tasks on satellites. This ecosystem provides a streamlined way to exploit GPGPU processing in space, enabling faster development times and more efficient resource use. Designed for FPGAs and tailored to edge computing tasks, the GPU@SAT accelerator mimics the parallel architecture of a GPU, allowing developers to leverage its capabilities while maintaining flexibility. Its compatibility with OpenCL simplifies the development process, enabling faster deployment of satellite-based applications. The DevKit was implemented and tested on a Zynq UltraScale+ MPSoC evaluation board from Xilinx, integrating the GPU@SAT IP core with the system’s embedded processor. A client/server approach is used to run applications, allowing users to easily configure and execute kernels through a simple XML document. This intuitive interface provides end-users with the ability to run and evaluate kernel performance and functionality without dealing with the underlying complexities of the accelerator itself. By making the GPU@SAT IP core more accessible, the DevKit significantly reduces development time and lowers the barrier to entry for satellite-based edge computing solutions. The DevKit was also compared with other onboard processing solutions, demonstrating similar performance. Full article

One of the most common mitigations against network-borne security threats is the deployment of firewalls, i.e., systems that can observe traffic and apply rules to let it through if it is benign or drop packets that are recognized as malicious. Cheap and open-source (a feature that is greatly appreciated in the security world) software solutions are available but may be too slow for high-rate channels. Hardware appliances are efficient but opaque and they are often very expensive. In this paper, an open-hardware approach is proposed for the design of a firewall, implemented on off-the-shelf components such as an FPGA (the Xilinx KC705 development board), and it is tested using controlled Ethernet traffic created with a packet generator as well as with real internet traffic. The proposed system can filter packets based on a set of rules that can use the whitelist or blacklist approach. It generates a set of statistics, such as the number of received/transmitted packets and the amount of received/transmitted data, which can be used to detect potential anomalies in the network traffic. The firewall has been experimentally validated in the case of a network data throughput of 1 Gb/s, and preliminary simulations have shown that the system can be upgraded with minor modifications to work at 10 Gb/s. Test results have shown that the proposed firewall features a latency of 627 ns and a maximum data throughput of 0.982 Gb/s. Full article

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies. Full article

Marine diesel engines are the preferred power equipment for ships and are the most important component among the numerous electromechanical devices on board. Accidents involving these engines can potentially cause immeasurable damage to the vessel, making fault detection in marine diesel engines crucial. This design enables the detection and reporting of faults in marine diesel engines at the earliest possible time through the computation of convolutional neural networks, which is of great significance for ensuring the safe navigation of ships. For this functionality, the Xilinx ZYNQ-7000 XC7Z010 is selected as the main control chip, and the LoRa wireless network is used as the transmission module. The FreeRTOS embedded operating system is ported, with sensor data collection completed on the PS side of the ZYNQ chip and algorithm acceleration calculations on the PL side. Data are then transmitted to the host computer via the LoRa module paired with a custom protocol. Experimental test results show that the program provides stable data transmission, with each module of the algorithm generally accelerating by more than 95% and an accuracy rate of 92.86%. Additionally, the host computer can display the received data in real time. The custom protocol’s header also allows for precise judgments about the completeness and origin of messages, facilitating the expansion of other SOC’s message uplink and the host computer’s message downlink. Full article

Induction motors (IM) play a fundamental role in the industrial sector because they are robust, efficient, and low-cost machines. Changes in the environment, installation errors, or modifications to working conditions can generate faults in induction motors. The trend on IM fault detection is focused on the design techniques and sensors capable of evaluating multiple faults with various signals using non-invasive analysis. The methodology is based on processing electric current signals by applying the short-time Fourier transform (STFT). Additionally, the computation of the mean and standard deviation of infrared thermograms is proposed as main indicators. The proposed system combines both parameters by means of Support Vector Machine and k-nearest-neighbor classifiers. The development of the diagnostic system was done with digital hardware implementations using a Xilinx PYNQ Z2 card that integrates an FPGA with a microprocessor, thus taking advantage of the acquisition and processing of digital signals and images in hardware. The proposed method has proved to be effective for the classification of healthy (HLT), misalignment (MAMT), unbalance (UNB), damaged bearing (BDF), and broken rotor bar (BRB) faults with an accuracy close to 99%. Full article

Cryptographic primitives nowadays are not only implemented in high-performance systems but also in small-scale systems, which are increasingly powered by open-source processors, such as RISC-V. In this work, we leverage RISC-V’s modular base instruction set and architecture to propose a generic instruction set extension (ISE) for symmetric cryptography. We adapt the work from Engels et al. in ARITH’13, the non-linear/linear instruction set extension (NLU), which presents a generic hardware/software co-design solution for efficient symmetric crypto implementations through a hardware unit extending the 8-bit AVR instruction set. These new instructions realize non-linear and linear layers, which are widely used to implement the block ciphers in symmetric cryptography. Our proposal modifies and extends the NLU instructions to a 32-bit RISC-V architecture; hence, we call the proposed ISE ‘NLU-V’. The proposed architecture is integrated into the open-source RISC-V implementation ‘Icicle’ and synthesized on a Xilinx Kintex-7 XC7K160T FPGA. The area overhead for the proposed NLU-V ISE is 1088 slice registers and 4520 LUTs. As case studies, the PRESENT and AES block ciphers are implemented using the new ISE on RISC-V in assembly. Our evaluation metric to showcase the performance gain, Z ‘time-area-product (TAP)’ (the execution time in clock cycles times code memory consumption), reflects the impact of the proposed family of instructions on the performance of the cipher implementations. The simulations show that the NLU-V achieves 89% gain for PRESENT and 68% gain for AES. Further, the NLU-V requires 44% less lines of code for the PRESENT and 23% less for the AES implementation. Full article

This research investigates the implementation of complex-exponential-based neurons in FPGA, which can pave the way for implementing bio-inspired spiking neural networks to compensate for the existing computational constraints in conventional artificial neural networks. The increasing use of extensive neural networks and the complexity of models in handling big data lead to higher power consumption and delays. Hence, finding solutions to reduce computational complexity is crucial for addressing power consumption challenges. The complex exponential form effectively encodes oscillating features like frequency, amplitude, and phase shift, streamlining the demanding calculations typical of conventional artificial neurons through levering the simple phase addition of complex exponential functions. The article implements such a two-neuron and a multi-neuron neural model using the Xilinx System Generator and Vivado Design Suite, employing 8-bit, 16-bit, and 32-bit fixed-point data format representations. The study evaluates the accuracy of the proposed neuron model across different FPGA implementations while also providing a detailed analysis of operating frequency, power consumption, and resource usage for the hardware implementations. BRAM-based Vivado designs outperformed Simulink regarding speed, power, and resource efficiency. Specifically, the Vivado BRAM-based approach supported up to 128 neurons, showcasing optimal LUT and FF resource utilization. Such outcomes accommodate choosing the optimal design procedure for implementing spiking neural networks on FPGAs. Full article

Web applications and online business transactions have grown tremendously in recent years. As a result, cyberattacks have become a major threat to the digital services that are essential for our society. To minimize the risks of cyberattacks, many countermeasures are deployed on computing nodes and network devices. One such countermeasure is the firewall, which is designed with two main architectural approaches: software running on standard or embedded computers, or hardware specially designed for the purpose, such as (Application Specific Integrated Circuits) ASICs. Software-based firewalls offer high flexibility and can be easily ported to upgradable hardware, but they cannot handle high data rates. On the other hand, hardware-based firewalls can process data at very high speeds, but are expensive and difficult to update, resulting in a short lifespan. To address these issues, we explored the use of an (Field-Programmable Gate Array) FPGA architecture, which offers low latency and high-throughput characteristics along with easy upgradability, making it a more balanced alternative to other programmable systems, like (Graphics Processor Unit) GPUs or microcontrollers. In this paper, we presented a packet sniffer designed on the FPGA development board KC705 produced by Xilinx, which can analyze Ethernet frames, check the frame fields against a set of user-defined rules, and calculate statistics of the received Ethernet frames over time. The system has a data transfer rate of 1 Gbit/s (with preliminary results of increased data rates to 10 Gbit/s) and has been successfully tested with both ad hoc-generated Ethernet frames and real web traffic by connecting the packet sniffer to the internet. Full article

Recent advances in mobile connection technology have been involved in every aspect of modern life. Even vehicles are becoming more connected, with the ability to communicate without human intervention. The main idea of connected vehicles is to exchange information to avoid a potential collision or to warn the driver about stop signs/lights. To achieve a wide range of connections between vehicles, they must be equipped with connected devices such as Bluetooth, wi-fi, and cellular connectivity. However, communication raises security issues with regard to cybersecurity attacks that attempt to collect confidential information or to take control of the vehicle by forcing unintended braking or steering. In this paper, we proposed a secure vehicle-to-vehicle (V2V) communication approach by deploying a secure communication protocol based on a key management process and a cryptography system to encrypt exchanged data. The proposed key management process was designed to resist many attacks and eliminate connections to the infrastructure for key generation. Since vehicles are equipped with embedded devices with limited computation resources, a lightweight cryptography algorithm was used. The light encryption device (LED) block cipher was used to encrypt exchanged data. The LED has a low implementation area on hardware and low power consumption. It is considered to be a perfect solution for security issues in connected vehicles. The proposed data encryption algorithm was synthesized with VHDL on the Xilinx Zynq-7020 FPGA using the Vivado HLS tool. The encryption algorithm was implemented only on the logic of the device. The achieved results proved that the proposed algorithm is suitable for implementation in vehicles due to its low implementation requirements and low power consumption in addition to its high security level against cyber-attacks. Full article

The multilevel inverter (MLI) has been developed as a powerful power conversion scheme for several processes, including renewable energy, transmission systems, and electric drives. It has become popular across medium- to high-power operations due to its many advantages, including minimum harmonic content, low switching losses, and reduced electromagnetic interference (EMI). In this paper, the capacitor voltage balancing technique-based pulse width modulation (PWM) has been proposed. The proposed PWM strategy offers several advantages, such as high-quality output waveforms with reduced harmonic distortion, improved efficiency, and better control over the output voltage. The Xilinx ISE 10.1 software was used for synthesizing, and the VHDL code was written for the proposed method. MATLAB software was used to simulate and hardware was used to verify the proposed system. The SPARTAN 3E FPGA was used for the generation of the PWM. This paper developed a 2 kW single-phase 15-level inverter that created an AC wave from the DC input voltage, with a total harmonic distortion (THD) of 8.02%, which was less than the THD achieved from other conventional MLI. The results indicate that MLI topologies with low total harmonic currents, fewer switches, and higher output voltage levels are better stabilized during load disturbance circumstances. Full article