Search Results (139)

The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified. Full article

High Bandwidth Memory couples many DRAM dies to a host through independent channels, and a memory controller presents each channel to the workload as either available or isolated. This paper takes that binary service interface as the modeling primitive and builds a closed-form framework for evaluating stack and system behavior on top of it. Each die is treated as a binary component whose reliability is composed from DRAM, through-silicon via and micro-bump contributions, with the via bundle itself modeled as a threshold subsystem; the dies are then aggregated as a threshold structure over the stack, and stacks are aggregated over the system. The result is an evaluation whose cost grows linearly rather than exponentially with the number of dies, and which yields not only reliability but the full distribution of delivered bandwidth, its moments, and the sensitivity of system availability to each component. Three design questions are answered directly: where to direct reliability investment, how many stacks to provision for a given availability target, and which bandwidth threshold minimizes cost when bandwidth and reliability requirements are imposed together. The approximations the framework makes are bounded rather than assumed. A three-state baseline quantifies the error introduced by the binary representation and shows it is governed by a single measurable quantity, and distribution-free inequalities bound the effect of correlation among component failure mechanisms, which proves negligible in the regime where HBM parts are qualified. Application to a representative stack identifies DRAM cell reliability as the dominant bottleneck and shows that a single spare via per bundle is sufficient at typical defect rates. Full article

High-bandwidth memory (HBM) faces critical power integrity challenges in high-stack configurations due to elongated power delivery paths and increased parasitic inductance. This paper proposes a dual-interposer HBM architecture with an interposer–HBM stack–interposer configuration, integrating an additional top interposer embedded with chip capacitors. This topology redesigns the HBM’s power distribution network, reducing PDN impedance, and this technology enables bidirectional vertical power supply to DRAM chips during moments when they require current. The PDN impedance is systematically compared with a conventional trench-capacitance-enhanced structure (Structure A) and a deep-trench-capacitance-enhanced structure (Structure B). Results show that at 0.1–11.2 GHz, the proposed structure reduces peak PDN impedance by 66.41% and 65.7% versus Structures A and B, respectively, and decreases the loop inductance of the top-layer DRAM chip by 66.71%. The top interposer’s redistribution layer forms a parallel-plate capacitor complementing the embedded chip capacitors, achieving wideband impedance suppression. Without modifying existing protocols, this architecture provides a system-level PDN optimization strategy for high-stack HBM, offering quantitative insights for capacitor selection and layout design. Full article

Back-end-of-line-compatible oxide-semiconductor field-effect transistors (OSFETs) enable vertically stackable two-transistor zero-capacitor (2T0C) dynamic random-access memory (DRAM) cells, offering high densities while maintaining low write energy. The capacitorless 2T0C cell intrinsically benefits from decoupled read/write paths and a sub-fF storage-node (SN) capacitance $C_{\mathrm{SN}}$, reducing the stored charge to the sub-fC level. However, the control-line energy overhead introduced by the independent write word-line (WWL) activation can erode this advantage. The minimum write energy is ultimately bounded not by $C_{\mathrm{SN}}$ alone but also by the drive capability and leakage of the write transistor ${\mathrm{T}}_{\mathrm{W}}$ and the WWL and write bit-line (WBL) voltage configuration. A systematic co-optimization methodology addressing these coupled constraints has yet to be established. This work is built on the insight that the write-optimization target should be the stored-charge margin $\Delta Q_{\mathrm{SN}}$ rather than the storage-node voltage $V_{\mathrm{SN}}$ because $\Delta Q_{\mathrm{SN}}$ remains nearly constant across all phases and directly governs readout distinguishability. The methodology combines a coupled analysis of threshold voltage ($V_{\mathrm{th}}$), SS, and ${\mu }_{\mathrm{FE}}$ of ${\mathrm{T}}_{\mathrm{W}}$ with the adoption of $\Delta Q_{\mathrm{SN}}$ as the read-margin metric. On this basis, the write-overdrive margin, the WBL voltage, and $V_{\mathrm{th}}$ of ${\mathrm{T}}_{\mathrm{W}}$ are sequentially optimized. The three-step procedure reduces $\Delta V_{\mathrm{WWL}}$ from 3.0 V to 2.10 V while satisfying the 2 ns design-level write-time constraint, the 0.54 fC read-margin criterion, and the 1 ks retention benchmark. Under the assumptions of the present case study, the optimized 2T0C array yields a 2.5× reduction in array-level write-related energy relative to the unoptimized baseline and a 3.0× reduction relative to the LPDDR6 1T1C array reference. Full article

Main memory carries data outside the processor’s trust boundary, so commodity systems-on-chip (SoCs) increasingly encrypt it; yet, in-line memory encryption engine itself becomes a differential power analysis (DPA) target whose key, if recovered, unlocks all of dynamic random-access memory (DRAM). We present PACE, a page-adaptive, cache-anchored memory encryption engine for RISC-V that makes nth-order DPA resistance practical and keeps cryptographic latency off the cache eviction critical path. PACE inserts a TileLink adapter between the last-level cache and the memory port and applies, per physical page, one of four policies (plaintext/confidentiality/confidentiality+integrity/+masking-order-d) selected from RISC-V page table bits through a memory-mapped control plane. Confidentiality uses counter mode whose per-line keystream is precomputed during cache residency; integrity is tree-free at the embedded operating point via on-chip counters and tags, with a live split counter block-MAC Bonsai Merkle tree for scale-out. DPA resistance is layered: ISAP-style fresh re-keying caps the data complexity per key at $q\approx 1$, and domain-oriented masking (DOM, d + 1 shares) protects the sole key processing block to order d. We implement PACE in Chisel on a Rocket SoC (Chipyard) and evaluate it with open-source tooling. A deterministic TileLink-level harness proves ciphertext-in-memory and detects tamper/replay/splice, and the live Tier-B engine (DRAM counters and per-line message authentication codes (MACs) plus an on-chip-rooted block-MAC tree) is validated from end to end on full Rocket and BOOM SoCs and on the FPGA; the masked Ascon-p S-box is proven order-d secure (d = 1, 2) under a glitch- and transition-aware model by three independent formal tools (COCO, PROLEAD, and SILVER, the last also deciding the full composability lattice and confirming exact glitch-robust order-2 probing security), with COCO extending the exact verdict to the highest synthesized order d = 3 (secure at probing orders 1–3); a simulated trace correlation power analysis (CPA) recovers the full key from an unprotected core and is defeated by masking, with a mutual information analysis confirming the $N\propto {\sigma }^{2(d+1)}$ trace amplification law. We further realize PACE on field-programmable gate array (FPGA) silicon: the engine plus an on-chip ring oscillator power sensor is placed, routed, timing-closed at 100 MHz, and programmed on a Xilinx XC7Z020, and we drive a fixed-vs-random Test Vector Leakage Assessment (TVLA) campaign read back entirely over a JTAG (Joint Test Action Group). A multi-core configuration and a Linux control-plane driver are likewise validated. Across synthetic access patterns and named application kernels (AES, SHA-256, matrix multiplication, pointer chasing) on both in-order Rocket and out-of-order BOOM, application-level overhead is within measurement noise of plaintext for cache resident workloads (masking, in particular, is cycle-identical to plain confidentiality), and we characterize the cost of each policy, masking order, and re-keying interval, demonstrating side-channel-hardened memory encryption on open RISC-V hardware. Full article

As dynamic random-access memory (DRAM) continues to scale down and achieve higher integration density, the cell layout has transitioned to 6F², resulting in narrower spacing between adjacent word lines (WLs). Consequently, cell-to-cell disturbance has become more severe. In particular, the row-hammer effect (RHE) has emerged as a critical reliability issue that must be mitigated to ensure stable operation in next-generation DRAM devices. In this study, a novel DRAM cell structure is proposed, in which a low-k dielectric material is embedded beneath the storage node (SN) to mitigate the electric field. This structural modification effectively suppresses the RHE compared to the conventional partial-isolation type buried channel array transistor (Pi-BCAT). The feasibility and performance of the proposed structure were verified through 2D Sentaurus technology computer-aided design (TCAD) simulations. The device embedding the low-k dielectric beneath the SN exhibits a mitigation of approximately 20.45% in D0 failure and about 12.12% in D1 failure. This improvement is attributed to the reduced electric field in the region underneath the SN, which suppresses stored charge leakage. These results confirm that the proposed structure not only enhances DRAM reliability in advanced process nodes but also provides an effective design guideline for highly integrated and low-power memory devices. Full article

DRAM-based in-memory computing integrates computational regions into the main memory, enabling local data processing within the memory, thereby achieving faster and more efficient data computation. However, enhancing system performance requires addressing a critical challenge: achieving more general and sufficiently powerful data processing capabilities within DRAM-PIM. Existing DRAM-PIM implementations often suffer from limited computational capabilities due to the shared standard DRAM package area between memory cells and computational circuits or because the operator circuits are overly customized, which limits their ability to meet required data processing demands. To address this issue, in this paper, we propose a Super Memory Processing Unit (SMPU). The SMPU uses Hybrid Bonding technology to 3D-stack DRAM and many-core computational clusters, enabling large-bandwidth (0.25 TB/s per-bank, 2 TB/s for 8-bank system bandwidth) on-chip data transmission between DRAM and the computational cluster via copper interconnects, effectively breaking the memory wall bottleneck of existing computing architectures. The SMPU constructs a dual-channel fine-grained computational cluster at the logical computing layer, providing flexible and ample computility for various AI models, such as ResNet50 and Llama2. The SMPU uses standard DDR protocols and integrates a new memory space allocation and parsing controller to ensure system compatibility without modifying the host-end hardware, facilitating the integration and invocation of computility in memory particles. Additionally, the SMPU features an independent dual-channel memory-management mechanism within the memory particles, enabling simultaneous multi-channel, multi-modal AI model inference. We compared a CPU system equipped with an SMPU to current computing systems using FPGA simulations. The FPGA simulation results show that, under the same computational configuration, the system with the SMPU improves the performance of ResNet50-v1.5 by up to 5.1× and Llama by up to 27.43× compared to the base system, while reducing system power consumption by 71.6% (ResNet50-v1.5) to 77.8% (Llama 7B). Full article

Processing-in-memory and in-memory computing (PIM/IMC) are increasingly explored to mitigate the von Neumann data-movement bottleneck that limits deep neural network (DNN) performance and energy efficiency. Progress, however, remains fragmented across device substrates, architectural prototypes, mapping and scheduling methods, compiler toolchains, and benchmarking practices, making results hard to compare and slowing deployment. This survey synthesizes developments from 2019–2025 along four coupled axes: (i) memory substrates and architectural design, (ii) mapping, partitioning, and scheduling, including learning- and graph-based strategies, (iii) compilers and end-to-end deployment flows, and (iv) benchmarking datasets, metrics, and reporting norms. Drawing on over twenty representative platforms spanning static random-access memory (SRAM) and dynamic random-access memory (DRAM), emerging non-volatile, capacitive, and photonic substrates, we clarify the trade-offs separating analog/charge-domain IMC from digital SRAM/DRAM-centric PIM, including reported peaks up to 600 TOPS/W and 1.5 TOPS/mm². We organize mapping frameworks into a unified reference taxonomy, identify recurrent evaluation pitfalls that undermine reproducibility, and highlight persistent gaps in training support, robustness under non-idealities, and coverage of large-scale GNN workloads. Finally, we outline a five-phase roadmap from benchmark standardization to industrial validation toward compiler-integrated, GNN-informed PIM/IMC systems validated on production-scale workloads. Full article

Polymer-augmented waterflooding is a key enhanced oil recovery technique whose simulation remains computationally demanding at a high spatial resolution. This paper presents a fully GPU-resident parallel solver for the one-dimensional Buckley–Leverett polymer-flooding problem within an Implicit-Pressure–Explicit-Saturation framework. The solver combines Jacobi iteration for pressure, first-order upwind flux splitting for saturation, and a first-order upwind flux-splitting update for polymer mass with explicit concentration recovery inside a coupled Picard–IMPES iteration. Two CUDA implementations are compared: a global-memory baseline and a shared-memory variant that stages a per-block pressure tile with halo cells on chip. Both kernels were profiled on an NVIDIA GeForce RTX 2080 Ti over problem sizes from $N=65,536$ to $N=67,108,864$ and block sizes 128, 256, 512, and 1024. The two GPU implementations match the serial reference within $2\times {10}^{-8}$, and peak speed-ups are $20.2\times$ (global) and $20.1\times$ (shared). Per-kernel Nsight Compute profiling classifies every kernel in both builds as compute-bound: SM throughput is 54–83% of peak and DRAM throughput 3–29% of peak. The bottleneck is the FP64 pipeline of consumer Turing hardware (FP64 throughput is one thirty-second of FP32); three FP64 divisions per cell, from inline polymer-modified mobility recomputation, saturate the FP64 unit. Shared-memory tiling cannot improve performance because it acts on memory traffic rather than on compute throughput. The result therefore characterizes a specific regime, namely FP64 one-dimensional, low-reuse transport stencils on consumer-class NVIDIA GPUs with reduced FP64 throughput, and is not a universal property of CUDA shared memory. Full article

Two-transistor zero-capacitor (2T0C) DRAM has attracted attention as an alternative memory due to its high potential for monolithic 3D integration (M3D). However, conventional 2T0C DRAM consists of four terminals, requiring large contact and peripheral area in the array. Moreover, selective read-out in the array has not been sufficiently addressed, as half-selected cells are susceptible to unintended current. To address this, two types of three-terminal 2T0C DRAM, bit-line-shared (BLS) and word-line-shared (WLS), were implemented, together with an offset bias scheme that enables selective read by applying complementary biases to the read terminals. Both structures exhibited retention times exceeding 800 s, comparable to conventional 2T0C DRAM. Array-level read selectivity and sensing margin were evaluated through SPICE simulations under various parasitic capacitance and offset bias conditions. Under optimized conditions, read selectivity values of 1.63 × 10⁵ and 1.51 × 10⁵ were achieved for the BLS and WLS structures, respectively. Notably, the WLS structure exhibited a selected cell on-current of approximately 0.17 μA, one order of magnitude higher than that of the BLS structure. This on-current advantage is analytically attributed to the structural decoupling of write-induced V_SN drop and read-induced V_GS enhancement in the WLS configuration. These results establish the WLS three-terminal 2T0C DRAM with the offset bias scheme as a more favorable configuration for high-density array implementation. Full article

Adverse-weather image restoration is increasingly needed in edge vision systems, yet many recent methods are developed primarily for accuracy on server-class hardware rather than efficient deployment on resource-constrained platforms. This gap is particularly important for unified-memory edge GPUs, where memory traffic, activation movement, and latency variability can become major bottlenecks during inference. To address this issue, this paper presents an efficient adverse-weather restoration framework for unified-memory edge GPUs based on a memory-traffic-aware fusion strategy. Instead of relying on heavy multi-branch interaction or traffic-intensive feature aggregation, the proposed design emphasizes compact feature exchange, activation-aware computation, and hardware-friendly luminance modulation under constrained memory bandwidth. The framework is developed to preserve restoration quality while reducing unnecessary intermediate data movement, thereby improving runtime efficiency and practical deployability on edge devices. Experiments on ACDC show that the proposed MW-DSNet improves downstream semantic segmentation robustness to 49.8% mIoU under a fixed segmentation head, outperforming the no-restoration input by +6.9 points and TransWeather by +0.8 points. On the NVIDIA Jetson Orin Nano (NVIDIA Corporation, Santa Clara, CA, USA) under the 15 W mode, the FP16 TensorRT engine sustains 30.0 FPS at 720p with 35.1 ms p95 latency, 36.8 ms p99 latency, and 650 MB/frame DRAM traffic. INT8 deployment with night heavy calibration further improves throughput to 42.5 FPS and reduces DRAM traffic to 380 MB/frame while limiting the mIoU drop to 1.7 points. These measured results indicate that memory-traffic-aware fusion and luminance-conditioned modulation provide a practical accuracy–efficiency trade-off for unified-memory edge GPUs. Full article

With the continuous growth of data-intensive applications and artificial intelligence workloads, traditional dynamic random access memory (DRAM) is increasingly struggling to meet demands in terms of capacity scale, energy consumption constraints, and data retention after power failure. Consequently, non-volatile memory (NVM) has emerged as a crucial technology for bridging the gap between the memory and storage layers. However, due to inherent differences in write life, read–write performance variations, and consistency guarantee after failure, the systematic application of NVM still faces a series of challenges. Addressing these issues, this paper takes as its starting point the adaptation of medium characteristics and system design, and summarizes the research progress in aspects such as write optimization, consistency and security coordination mechanisms, data structure modification under hybrid memory architecture, and cross-layer resource collaboration. It also conducts an in-depth analysis of representative solutions and evaluation methods. The review results show that current research has shifted from improving a single performance bottleneck to multi-mechanism collaborative optimization. Various technical approaches have proven complementary in alleviating write amplification, enhancing persistence efficiency, and optimizing access patterns. This paper demonstrates that achieving stable and scalable application of NVM requires establishing a more systematic collaborative design concept between durability, security, and performance. As AI training workloads and big data analytics place increasing demands on memory bandwidth and persistence, the techniques surveyed here provide a foundational basis for next-generation memory-centric computing infrastructures. Full article

The explosive growth of temporal graph data has led to significant training overheads for Dynamic Graph Neural Networks (DGNNs), a bottleneck primarily driven by massive data movement between host processors and storage arrays across conventional PCIe I/O buses. While near-data processing with Computational Storage Devices (CSDs) can alleviate this bottleneck, a single CSD is inherently incapable of meeting the terabyte-scale capacity requirements and complex sequence modeling demands of modern large-scale DGNNs. Horizontal scaling with multi-CSD clusters over standard PCIe topologies presents a viable, cost-effective solution, yet our in-depth profiling identifies two critical architectural bottlenecks in naive multi-CSD architectures: host-bounced memory copies significantly compromise inter-device communication efficiency, and sparse graph sampling frequently exceeds the capacity of the tightly constrained local DRAM of CSDs, resulting in excessive flash I/O and performance degradation. To address these interconnected bottlenecks, we propose M-DGNN, a hardware–software co-designed architecture optimized for standard PCIe interconnects. First, M-DGNN orchestrates direct peer-to-peer (P2P) DMA dataflows for inter-CSD hidden state exchange, completely bypassing host operating system intervention and reducing the context-switching overhead. Second, we design a host-assisted caching strategy with a Host-Pinned Memory Extension (HPME) mechanism, which leverages host-pinned memory as an asynchronous DMA extension pool to shield resource-constrained CSDs from high-latency flash I/O during structural subgraph sampling. Extensive experimental evaluations across seven large-scale dynamic graph datasets demonstrate that M-DGNN delivers up to a 6.2× end-to-end speedup over the state-of-the-art DGNN systems. This work establishes an efficient, scalable near-data computing paradigm for large-scale DGNN training. Full article

This study investigates the impact of non-ideal wordline sidewall angles caused by photoresist profile variation during the wordline etching process in DRAMs employing a buried-channel array transistor (BCAT) structure. Using Technology Computer-Aided Design (TCAD), a two-dimensional (2D) BCAT-based DRAM cell was modeled to analyze the resulting variations in device characteristics as well as write and hold operations. The simulation results show that increased etch slope angles lead to degradation in device performance, including failure to meet the read pass/fail criterion and data retention during the 300 ms hold interval. To mitigate these issues, we inserted a buried oxide (BOX) layer beneath the active wordline (AWL). The incorporation of the BOX layer effectively improved overall device robustness and reduced the degradation induced by non-ideal etch slopes. Full article

Apache Spark has gained widespread adoption for large-scale data processing. However, conventional caching methods inadequately address the dual challenges of performance bottlenecks and escalating energy consumption in data-intensive workloads. This paper introduces a sustainable computing framework that integrates Directed Acyclic Graph (DAG) dependency analysis with garbage collection (GC) behavior monitoring to optimize data placement between DRAM and non-volatile memory (NVM). The proposed Intelligent Hybrid Caching Management Framework (IHCMF) dynamically predicts data access patterns and migrates cache blocks based on cost–benefit analysis, achieving a 37.5% execution time reduction over default Spark configurations in SparkBench evaluations. By improving throughput-per-watt and projecting potential benefits from NVM’s near-zero idle power and extended hardware lifespan, IHCMF provides a scalable, cost-effective caching solution for resource-constrained edge computing environments. This work demonstrates that high-performance computing can be reconciled with environmental sustainability through intelligent memory management. Full article