This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell w...
The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digita...
General-purpose graphics computing on processing units (GPGPUs) face significant performance limitations due to memory access latencies, particularly when traditional memory hierarchies and thread-switching mechanisms prove insufficient for complex a...
This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type p...
This research is to design a Q-selector-based prefetching method for a dynamic random-access memory (DRAM)/ Phase-change memory (PCM)hybrid main memory system for memory-intensive big data applications generating irregular memory accessing streams. S...
Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study...
In this article, we systematically analyze the electrical characteristics of 2T0C DRAM unit cells for compute-in-memory (CIM) applications, focusing on the on/off current ratio, coupling effects, and retention time, with respect to the NN (NMOS-NMOS)...
Predicting the price of a dynamic random access memory (DRAM) product is a critical task to the manufacturer. However, it is not easy to contend with the uncertainty of the price. In order to effectively predict the price of a DRAM product, an agent-...
A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level oper...
In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to...
As dynamic random-access memory (DRAM) continues to scale down and achieve higher integration density, the cell layout has transitioned to 6F2, resulting in narrower spacing between adjacent word lines (WLs). Consequently, cell-to-cell disturbance ha...
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). P...
DRAM-based in-memory computing integrates computational regions into the main memory, enabling local data processing within the memory, thereby achieving faster and more efficient data computation. However, enhancing system performance requires addre...
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM)...
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tool...
With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current sol...
As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlen...
The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed...
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market,...
The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedd...
The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip me...
In modern multi-core processors, memory request latency critically constrains overall performance. Prefetching, a promising technique, mitigates memory access latency by pre-loading data into faster cache structures. However, existing core-side prefe...
This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes...
Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Gen...
Recent developments have increased the demand for adequate security solutions, based on primitives that cannot be easily manipulated or altered, such as hardware-based primitives. Security primitives based on Dynamic Random Access Memory (DRAM) can p...
The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this iss...
Adverse-weather image restoration is increasingly needed in edge vision systems, yet many recent methods are developed primarily for accuracy on server-class hardware rather than efficient deployment on resource-constrained platforms. This gap is par...
In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D...
Processing-in-memory (PIM) architectures have emerged as promising alternatives to conventional von Neumann architectures for accelerating memory-bound applications, such as Graph Neural Networks (GNNs), by reducing data movement between memory and p...
Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access perfo...
Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demo...
These days, the demand on electronic systems operating at high temperature is increasing owing to bursting interest in applications adaptable to harsh environments on earth, as well as in the unpaved spaces in the universe. However, research on memor...
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume high...
With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing p...
Apache Spark has gained widespread adoption for large-scale data processing. However, conventional caching methods inadequately address the dual challenges of performance bottlenecks and escalating energy consumption in data-intensive workloads. This...
Emerging applications like deep neural networks require high off-chip memory bandwidth and low dynamic loaded Double Data Rate SDRAM (DDR) latency. However, under the stringent physical constraints of chip packages and system boards, it is extremely...
To address the performance and power concerns in Double-Data-Rate SDRAM (DDR) subsystems, this paper presents an innovative method for the DDR memory controller scheduler. This design aims to strike a balance between power consumption and performance...
This review summarizes the most widely used mechanisms in memory devices based on conjugated polymers, such as charge transfer, space charge traps, and filament conduction. In addition, recent studies of conjugated polymers for memory device applicat...
Deep neural networks (DNNs) are widely used in various artificial intelligence applications and platforms, such as sensors in internet of things (IoT) devices, speech and image recognition in mobile systems, and web searching in data centers. While D...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2...
For the first time, a novel germanium (Ge) bi-stable resistor (biristor) with a vertical pillar structure was implemented on a bulk substrate. The basic structure of the Ge pillar-typed biristor is a p-n-p bipolar junction transistor (BJT) with an op...
As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cyc...
This study investigates the impact of non-ideal wordline sidewall angles caused by photoresist profile variation during the wordline etching process in DRAMs employing a buried-channel array transistor (BCAT) structure. Using Technology Computer-Aide...
Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promising features of byte-addressability, high storage density, low cost per byte, and near-zero standby energy consumption. However, since NVMs have limit...
Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in...
This paper presents a one-transistor dynamic random-access memory (1T-DRAM) cell based on a gate-all-around junction-less field-effect transistor (GAA-JLFET) with a Si/SiGe heterostructure for high-density memory applications. The proposed 1T-DRAM ac...
To support multimedia and deep learning applications running on containers within a server, both processor cores and main memory space are critical resources for performance tuning. With the growing memory demands of applications to maintain intermed...
Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challen...
This paper presents an innovative prefetching algorithm for a hybrid main memory structure, which consists of DRAM and phase-change memory. To enhance the efficiency of hybrid memory hardware in serving big data technologies, the proposed design empl...
A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for...
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