A Fully Integrated Clocked AC-DC Charge Pump for Mignetostrictive Vibration Energy Harvesting

Abstract

This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm² fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits.

1. Introduction

In recent years, the Internet of things (IoT), in which information possessed by various machines and humans is collected by sensors and shared among objects via the Internet, has attracted attention. Since the IoT requires a lot of sensors, it is desirable for the edge devices to be battery-less in order to reduce maintenance costs. Thus, energy harvesting (EH) obtaining power from surrounding environmental energy is expected to become a power source for IoT sensor devices [1,2]. Vibration energy transducer (ET) converts vibration energy into AC electric power.

Table 1. Characteristics of vibration energy transducer.

	Piezoelectric [3]	Electrostatic [4]	Magnetostrictive [5]
Nominal output impedance	100 kΩ–1 MΩ	100 MΩ–1 GΩ	100 Ω–1 kΩ
Nominal output voltage	1 V–10 V	10 V–100 V	0.1 V–1 V
Output power (mW/cm3)	0.74–3 [7]	0.08–0.6 [7]	20 [5]

compares three different types in terms of physical characteristics: piezoelectric [3], electrostatic [4], and magnetostrictive [5]. The piezoelectric effect is a phenomenon in which a voltage proportional to the pressure applied to a material is generated. The AC power is extracted by applying vibration to the piezoelectric element. Since a voltage amplitude of 1 V or greater can be obtained, an AC-DC voltage down converter provides DC power to the sensor integrated circuit (IC). In the electrostatic induction power generation, the electrode plate of the capacitor charged by the electret is moved by vibration, and thus an AC power is generated. The output impedance of the generating element is very high, and the output voltage amplitude can be higher than 10 V. It requires high voltage rectifiers followed by a buck converter with many external components [6]. Magnetostrictive power is generated on the basis of the reverse magnetostrictive effect [5]. A high current can be obtained due to the low internal resistance. The amount of power generated per volume is larger than that of the other methods, as shown in Table 1.

The magnetostrictive elements are robust against large vibration acceleration. As a result, it is suitable as a power source for IoT sensors because of its simple structure and long lifetime. However, since the output voltage amplitude is as low as several hundred millivolts, a boosting circuit must be used to supply power to the IC.

Various circuit designs [8,9,10,11] have been proposed and developed for vibration EH (vEH). In Reference [8], an AC-DC charge pump (CP), which has been used for RF energy harvesting and radio frequency identification (RFID), is used for vEH as well. CP is a boosting circuit in which charges are transferred from one capacitor to the next by inputting a clock signal. Input AC voltage is also treated as a clock, as shown in Figure 1.

Accordingly, as the frequency of the AC input voltage increases, the output current of CP ($\overline{I_{\mathit{OUT}}}$) increases. In Reference [8], four discrete germanium Schottky barrier diodes and three chip capacitors with 1 μF each were built. AC-DC CPs have been integrated in RFID at HF or RF bands, as discussed in [12,13]. Conversely, AC-DC CPs have never been integrated in a chip for vEH because of its low frequency. When the capacitance per stage C is increased, the amount of charge that can be charged and discharged at one time increases, and thus $\overline{I_{\mathit{OUT}}}$ increases even at a low frequency. Figure 2 shows a simulated relationship between C of AC-DC CP and output power P_OUT.

Let us assume the power supply of the sensor requires 2 V and at least 1 μW at 2 V. When the input voltage amplitude V_DD = 0.5 V and V_OUT = 2 V, C of 700 pF is required to obtain P_OUT of 1 μW. If the AC-DC CP is integrated using metal-insulator-metal (MIM) capacitors with capacitance density of 2 fF/μm², the circuit area would be as large as 3 mm², and P_OUT per area is 0.3 μW/mm² when the number of stage is 9 and the AC frequency is 1 kHz. Such a design solution would be practically impossible for low-cost small form factor IoT edge devices. To solve the problem, AC-DC-DC conversion has been proposed and developed [9,10], which includes AC-DC conversion followed by DC-DC conversion using a CP (see Figure 3).

A rectifying device and an external capacitor are used for AC-DC conversion. Figure 4 shows rectifying devices for AC-DC conversion used in the AC-DC-DC converters.

In References [9,10], AC-DC conversion is performed by an active diode using an operational amplifier, as shown in Figure 4b. DC-DC CP was optimally designed to maximize the output power of the transducer. This solution requires a discrete capacitor C_REC to filter out AC components. In Reference [10], the AC-DC-DC circuit was designed in 0.35 μm complementary metal-oxide-semiconductor (CMOS) process technology. With active diodes, the circuit operated even at an input voltage of 0.5 V. In Reference [11], a switching regulator was designed to have a high output power of 1 mW with a power efficiency of 76%. However, it was not fully integrated due to the use of external capacitors and coils. Therefore, the clocked AC-DC CP was proposed in [14]. It can operate with a variety of transducers whose resonant frequencies can be in a wide range of 10 Hz to 100 kHz without any external components for low cost. Initial measurement results are shown in [15].

In this extended version of the paper, circuit modeling of the system including vibration ET and a clocked AC-DC CP is presented. Analysis of the input power to the charge pump and characteristics of the magnetostrictive ET are also discussed. Detailed measurement results and the comparison with the other systems are shown as well. Section 2 models the proposed circuit and entire system. Section 3 compares measurement results of the proposed circuit with the results of the formulas derived in Section 2 and simulation results. The proposed circuit was also measured with a magnetostrictive vibration ET. In Section 4, the proposed circuit is compared with the existing boosting circuits for vEH. Section 5 describes the future works of the proposed circuit. Section 6 summarizes this work.

2. Clocked AC-DC Charge Pump

2.1. A Modeling of the Intrinsic Part of the System

Figure 5 shows the clock waveforms used in the clocked AC-DC CP.

A sine wave is rectified and is modulated by a high frequency rectangular wave. As described in the Introduction, since the frequency of the AC voltage obtained from the transducer, f_IN, is about 10 Hz to 1 kHz, sufficient output power could not be obtained without using external devices. However, the clock frequency f_CLK of the clocked AC-DC CP is made much higher than f_IN. As long as the clock period is longer than RC time constant of switching diodes, the output current of CP is proportional to the clock frequency. Therefore, since the CP can operate at a high frequency, it is possible to obtain a sufficient output current even with a small sized capacitor to allow full integration. Furthermore, a discrete capacitor for smoothing the input voltage is not required. In this section, the equation for obtaining the input and output currents of the proposed circuit is modeled.

Figure 6 shows the waveforms of voltage and current in the proposed circuit. The input voltage is a sine wave with an amplitude of V_DD. θ_S is defined by the phase in which an average output current at θ, I_OUT(θ), starts to flow. I_OUT(θ) varies in amplitude according to the clock amplitude. Assuming that f_CLK is much higher than f_IN, the amplitudes at the rising and falling edges can be considered to be the same. Therefore, I_OUT(θ) is obtained by applying the I_OUT-V_OUT equation of the DC-DC charge pump [16].

$$I_{\mathit{OUT}}\left(\theta \right)=\frac{1}{R_{\mathit{TOT}}}\left\{\left(\frac{N}{1+\beta }+1\right)V_{\mathit{DD}}\mathit{sin}\theta -\left(N+1\right)V_{\mathit{TH}}^{\mathit{EFF}}{-V}_{\mathit{OUT}}\right\}$$

(1)

where N is the number of capacitors, β is the ratio of the parasitic capacitance to the pump capacitor C, $V_{\mathit{TH}}^{\mathit{EFF}}$ is the effective threshold voltage of the diode given by Equation (2) [16], and R_TOT is the output impedance of the entire system including ET and CP given by Equation (3) [17].

$$V_{\mathit{TH}}^{\mathit{EFF}}{=V}_T\mathit{ln}(\frac{4^{\frac{1}{N+1}}\left(1+\beta \right)f_{\mathit{CLK}}{\mathit{CV}}_T}{I_s})$$

(2)

$$R_{\mathit{TOT}}=\frac{N}{\left(1+\beta \right){Cf}_{\mathit{CLK}}}+{\left(N+1\right)}^2{R}_{\mathit{EH}}$$

(3)

where I_S is the saturation current of each diode and V_T is the thermal voltage.

When $I_{\mathit{OUT}}\left(\theta \right)$ becomes zero at θ = θ_S, θ_S can be given by Equation (4).

$${\theta }_s{=\mathit{sin}}^{-1}\left[\frac{1+\beta }{V_{\mathit{DD}}\left(1+\beta +N\right)}\left\{V_{\mathit{OUT}}+\left(N+1\right)V_{\mathit{TH}}^{\mathit{EFF}}\right\}\right]$$

(4)

Figure 7 shows an equivalent circuit for a converter system composed of a clocked AC-DC CP and transducer under the slow switching limit where I_OUT is proportional to f_CLK. R_EH, and R_PMP, which are the output impedance of energy transducer, that of CP, and that of entire system including the energy transducer, respectively [17].

Let us introduce k, which meets $\theta ={\theta }_s+k\times \frac{{2\pi f}_{\mathit{IN}}}{f_{\mathit{CLK}}}$. One can write down an average output current in the k-th pulse, I_OUT^k, as

$$I_{{\mathit{OUT}}^k}=\frac{1}{R_{\mathit{PMP}}}\left\{\left(\frac{N}{1+\beta }+1\right)V_{\mathit{DD}}\mathit{sin}\left({\theta }_s+k\times \frac{{2\pi f}_{\mathit{IN}}}{f_{\mathit{CLK}}}\right)-\left(N+1\right)V_{\mathit{TH}}^{\mathit{EFF}}{-V}_{\mathit{OUT}}\right\}$$

(5)

on the basis of Figure 7. The average output current $\overline{I_{\mathit{OUT}}}$ for one input cycle is obtained from Equation (6),

$$\overline{I_{\mathit{OUT}}}=\frac{2}{\pi }{\displaystyle \sum }_{k=1}^n{I}_{{\mathit{OUT}}^k}$$

(6)

where n is the number to meet π/2 = θ_S + n 2π f_IN/f_CLK, where I_OUTⁿ becomes the largest at $\theta =\pi /2$. ${\displaystyle \sum }_{k=0}^n\mathit{sin}\left(\theta +\varphi \right)$ can be calculated by Equation (7).

$${\displaystyle \sum }_{k=0}^n\mathit{sin}\left(\theta +\varphi \right)=\frac{\mathit{sin}\left(\frac{n+1}{2}\varphi \right)\mathit{sin}\left(\theta +\frac{n}{2}\varphi \right)}{\frac{\varphi }{2}}$$

(7)

Equation (6) can be simplified with Equation (7) as Equation (8).

$$\overline{I_{\mathit{OUT}}}=\frac{2}{\pi }\times \frac{1}{R_{\mathit{TOT}}}\left[\left(\frac{N}{1+\beta }+1\right)V_{\mathit{DD}}{\mathit{cos}\theta }_s-\left(\frac{\pi }{2}{-\theta }_s\right)\left\{\left(N+1\right)V_{\mathit{TH}}^{\mathit{EFF}}{+V}_{\mathit{OUT}}\right\}\right]$$

(8)

One can estimate an average output current per cycle $\overline{I_{\mathit{OUT}}}$ using Equations (2) and (8) under a specific condition of V_DD, V_OUT, f_CLK, N, C, β, I_S, and V_T.

Next, the input current I_CP and the input power P_CP are modeled. An equation for the input current of the DC-DC CP was obtained in [18]. By applying it to the proposed circuit, Equation (9) is obtained.

$$I_{\mathit{CP}}\left(\theta \right)=\left(\frac{N}{1+\beta }+1\right)I_{\mathit{OUT}}\left(\theta \right)+\left(\frac{\beta }{1+\beta }\right)f_{\mathit{CLK}}{\mathit{NCV}}_{\mathit{DD}}\mathit{sin}\theta$$

(9)

An average input current over one input cycle, $\overline{I_{\mathit{CP}}}$, can be given by integrating Equation (9) from θ_S to π/2, resulting in Equation (10).

$$\overline{I_{\mathit{CP}}}=\left(\frac{N}{1+\beta }+1\right)\overline{I_{\mathit{OUT}}}+\frac{2}{\pi }\left(\frac{\beta }{1+\beta }\right)f_{\mathit{CLK}}{\mathit{NCV}}_{\mathit{DD}}{\mathit{cos}\theta }_s$$

(10)

Similarly, an average input power P_CP, can be calculated as Equation (11).

$$\begin{array}{c}{P}_{\mathit{CP}}=\frac{2}{\pi }\times {{\displaystyle \int }}_{{\theta }_s}^{\frac{\pi }{2}}{I}_{\mathit{CP}}\left(\theta \right)V_{\mathit{DD}}\mathit{sin}\theta d\theta =\frac{2}{\pi }[\frac{1}{4}\left(\frac{1}{R_{\mathit{TOT}}}\right)\{{\left(\frac{N}{1+\beta }+1\right)}^2{V}_{\mathit{DD}}^2\left\{2\left(\frac{\pi }{2}{-\theta }_s\right){+\mathit{sin}2\theta }_s\right\}-\hfill \\ \left(\frac{N}{1+\beta }+1\right)V_{\mathit{DD}}\left(\left(N+1\right)V_{\mathit{TH}}^{\mathit{EFF}}{+V}_{\mathit{OUT}}\right){\mathit{cos}\theta }_s\}+\frac{1}{4}\left(\frac{\beta }{1+\beta }\right)f_{\mathit{CLK}}{\mathit{NCV}}_{\mathit{DD}}^2\left\{2\left(\frac{\pi }{2}{-\theta }_s\right){+\mathit{sin}2\theta }_s\right\}].\hfill \end{array}$$

(11)

Since V_OUT is a DC voltage, the output power P_OUT of the proposed circuit is determined by the product of $\overline{I_{\mathit{OUT}}}$ and V_OUT.

$$P_{\mathit{OUT}}{=V}_{\mathit{OUT}}\times \overline{I_{\mathit{OUT}}}$$

(12)

These equations are verified in Section 3.

2.2. Modeling of Additional Loss Components

The entire system for the proposed circuit is shown in Figure 8. A cross-coupled CMOS bridge circuit [19] is used for a full-wave bridge rectifier (FBR) to rectify the input voltage. A current-controlled ring oscillator (ROSC) is used to generate a clock waveform. f_CLK is proportional to a branch current I_OSC driving the inverter. The circuit is designed so that the value of I_OSC can be changed by externally applying the DC voltage V_CTRL. Therefore, it is possible to vary f_CLK by varying V_CTRL. For practical use, ROSC must be designed to have an optimum f_CLK for each specification without any external control such as V_CTRL. Diode-connected CMOS transistors [20] are used for the diode portion of CP. This configuration has the advantage of significantly reducing the reverse leakage current when reverse biased compared to conventional diode connections. Since the voltage of the CP diode is applied in the forward direction and the reverse direction every half cycle of the clock signal, reduction in the reverse current contributes to increasing the power efficiency of the CP [21].

An average power of ROSC is given by Equation (13).

$$\begin{array}{c}{P}_{\mathit{OSC}}=\frac{2}{\pi }{{\displaystyle \int }}_0^{\frac{\pi }{2}}\left(V_{\mathit{DD}}{\mathit{sin}\theta \times 2N}_{\mathit{OSC}}{f}_{\mathit{CLK}}{C}_{\mathrm{INV}}{V}_{\mathit{DD}}\mathit{sin}\theta \right)d\theta \\ {=N}_{\mathit{OSC}}{f}_{\mathit{CLK}}{C}_{\mathrm{INV}}{V}_{\mathit{DD}}^2\end{array}$$

(13)

where N_OSC is the number of stages of ROSC and C_INV is the gate capacitance of each stage.

Considering a power loss P_OFF due to the off-leak current of the NMOS and PMOS in FBR, the input power of the entire system, P_TOTAL, is obtained by summing Equations (11) and (13), and the power loss P_OFF.

$$P_{\mathit{TOTAL}}{=P}_{\mathit{CP}}{+P}_{\mathit{OSC}}{+P}_{\mathit{OFF}}$$

(14)

The power efficiency of the entire system η_TOT is obtained by Equation (15) together with Equations (11)–(14).

$${\eta }_{\mathit{TOT}}{=P}_{\mathit{OUT}}{/P}_{\mathit{TOTAL}}$$

(15)

A maximum available power of transducer, P_EH, can be realized under power matching,

$$P_{\mathit{EH}}=\frac{V_{\mathit{DD}}^2}{{8R}_{\mathit{EH}}}$$

(16)

The power efficiency η_SYS of the proposed circuit in this work is defined by Equation (17):

$${\eta }_{\mathit{SYS}}{=P}_{\mathit{OUT}}{/P}_{\mathit{EH}}$$

(17)

The values obtained from the above equations and the simulation values are compared with the measurement results in Section 3.

3. Validation

3.1. Validation with AC Power Source

The proposed circuit system was fabricated in 65 nm 1 V CMOS, as shown in Figure 9. Because the circuit operates at 1–10 MHz, 65 nm CMOS is not mandatory. One can design the circuit with less advanced technology such as 180 nm or 250 nm without significant performance degradation as far as low-Vt transistors are available. In order to achieve I_OUT > 1 μA at V_DD = 0.5 V and V_OUT = 2 V, we determined N and C to be 9 and 10 pF, respectively. The number of inverters in ROSC, N_OSC, was 17. In this experiment, the energy transducer was replaced with an AC voltage source with an amplitude of 0.5 V and an impedance of R_EH = 500 Ω. The output terminal was connected with an external resistor R_OUT and a capacitor C_OUT. C_OUT smooths V_OUT to DC and R_OUT controls V_OUT.

Figure 10 shows a chip micrograph. The total area of the whole circuit is about 0.11 mm². This size is small enough to fit in sensor ICs. The measured waveforms are shown in Figure 11, where R_OUT and C_OUT were 1 MΩ and 300 nF, respectively. V₁–V₂ is the input differential voltage to the circuit. V_REC is the supply voltage of CP and ROSC. Figure 11b shows focused clock waveform. Figure 11c shows the input and output voltages. The input voltage amplitude was 0.5 V while the output voltage V_OUT was about 2 V, indicating that the designed CP was functional as expected. P_OUT was about 4 μW.

I_OUT was measured with f_CLK and varied from 1 MHz up to about 5 MHz for a fabricated circuit and from 300 kHz up to about 8 MHz for a simulated one under V_DD = 0.5 V, V_OUT = 2 V, and f_IN = 1 kHz, as shown in Figure 12. The simulated and calculated values agreed within an error rate of 5% for fclk ≤ 1 MHz. As shown in Figure 11b, actual clock waveform had finite rise and fall times, which were ignored in the model equations. Therefore, the actual critical frequency to maximize $\overline{I_{\mathit{OUT}}}$ was lower than that with the model. As a result, the error increased at higher frequencies. The error rate between measured and calculated values was about 10%–40%. The frequency was saturated in the region of f_CLK ≥ 5 MHz.

Figure 13 shows P_TOT across f_CLK on the basis of the model (Equation (14)), measured (MEAS), and simulation (HSPICE). The error rate between the model (Equation (14)) and the simulation value was about 3–30%, and the error rate between the measured value and Equation (14) was about 5–15%. P_TOT also increased as f_CLK. Figure 13 includes each contributor to Equation (14): P_CP, P_OSC, and P_OFF as well. P_OFF became dominant at f_CLK < 500 kHz in this design. Such a corner frequency strongly depends on Vt of the switching transistors. As Vt decreased, both P_OFF and P_OUT and thereby P_IN increased. The calculation result shows that $\overline{I_{\mathit{OUT}}}$ started to decrease at f_CLK = 6 MHz. Since there was a power loss P_OFF = 2.85 μW independent of f_CLK, P_TOT in the low frequency region converged to 2.85 μW.

Figure 14 shows η_TOT across f_CLK. Since $\overline{I_{\mathit{OUT}}}$ of the measured values was lower than the simulation values in the range of f_CLK < 4 MHz, the measured values of η_TOT within the same range were also lower. The efficiency of the measured values was about 23% at the maximum. Compared with the conventional system shown in Figure 1, the power for ROSC was required, and thus the power efficiency was reduced compared with the conventional circuit. Figure 15 shows the relationship between $\overline{I_{\mathit{OUT}}}$ and V_OUT for V_DD of 0.4–1.0 V. ROSC was not able to run at f_CLK of 5 MHz when V_DD = 0.3 V. Because the maximum attainable voltage increased as V_DD, $\overline{I_{\mathit{OUT}}}$ increased as V_DD. P_OUT reached 30 μW at V_DD = 1 V and V_OUT = 3 V, for example. Figure 16a,b show $\overline{I_{\mathit{OUT}}}$ across V_DD and η_SYS across P_EH when V_OUT = 2 V and f_CLK = 5 MHz, respectively.

Figure 17 shows the measured results of f_IN-$\overline{I_{\mathit{OUT}}}$. The actual frequency of the vibration was about 10 Hz –1000 Hz, but it was changed from 10 Hz to 100 kHz for theoretical verification. $\overline{I_{\mathit{OUT}}}$ only varied by 3% over such a wide frequency range. Since the conventional circuit shown in Figure 1 operates on the basis of f_IN, a change in f_IN greatly affects $\overline{I_{\mathit{OUT}}}$ Therefore, it is necessary to adjust the circuit parameters depending on the vibration frequency. On the other hand, the proposed circuit was theoretically expected to be robust against variation in f_IN, as shown by Equations (8) and (14). Figure 17 suggests that the proposed circuit has the advantage that even if the frequency of vibration changes with a different energy transducer, the common circuit design can be used, which contributes to cost reduction.

3.2. Validation with Magnetostrictive Energy Transducer

The fabricated circuit was validated with magnetostrictive energy transducer, which was developed at Ueno lab [5], as shown in Figure 18a. The size of the transducer is about 3.5 cm × 1 cm × 1 cm. To extract f_IN and R_EH, we directly connected the energy transducer with R_L. The acceleration and frequency of the accelerator were controlled by a controller. Figure 18b shows a block diagram of the measurement system. Vibration was applied to the energy transducer to generate an AC voltage across the load resistor R_L.

As shown in Figure 19, the resonant frequency was determined to be 195 Hz. In the subsequent verification, f_IN was fixed at 195 Hz. Figure 20 shows V_DD across vibration acceleration α when R_L = ∞. It can be confirmed that V_DD was proportional to α. Figure 21a,b show, respectively, the output voltage when α = 0.28 G (a) and 0.5 G (b). The data indicate that the effective output resistance of the transducer was about 1 kΩ. The measured waveform validated the assumption that the magnetostrictive energy transducer can be modeled by the AC voltage source and the output impedance, as shown in Figure 3, as long as the load resistance R_L is relatively high. Accordingly, as the output power increased, there could be significant interaction between the mechanical and electrical characteristics, as described in [22]. In such a case, the model of the transducer would need to be modified.

Figure 22 shows f_CLK-$\overline{I_{\mathit{OUT}}}$ in terms of α = 0.28 G and α = 0.5 G. The solid and triangular plots show the results of Equation (8) and the simulation values when R_EH = 1 kΩ, respectively. For both Figure 21a,b, the error rate between the model at f_CLK ≤ 2 MHz and the measurement was approximately 11–16%. The error rate between the simulation result and the measurement was 2–9%. It is confirmed that the fabricated clocked AC-DC CP can output power of 1 μW at 2 V with α = 0.28 G at f_CLK ≥ 1 MHz. Figure 23 and Figure 24 show the input voltage amplitude of CP and $\overline{I_{\mathit{OUT}}}$ when α was changed. Measurement was performed with f_CLK = 5.0 MHz and V_OUT = 2 V. In this experiment, a 1 V CMOS transistor was used. Therefore, V_DD must be limited up to 1 V. As shown in Figure 23, α was controlled to be below 0.7 G. For production, a clamping circuit must be placed between V_REC and GND to limit V_REC. Although V_DD was about 0.4 V when α = 0.2 G, it was confirmed that the proposed circuit operated to obtain power of 2 μW–30 μW in the range of α = 0.2 G to 0.7 G.

4. Comparison with Other Designs

This section compares the proposed circuit with the voltage boosting circuits for vEH that has been reported in past research.

4.1. AC-DC CP

As shown in Figure 2, when the AC-DC CP is used for vEH, C must be increased to compensate for low vibration frequency. An AC-DC CP with N = 9 and C = 10 pF was also fabricated together with the clocked AC-DC CP. Figure 25 shows V_OUT-$\overline{I_{\mathit{OUT}}}$ when the AC-DC CP was operated under the condition of f_IN = 1 kHz and V_DD = 0.5 V. Both the simulation and the measurement results showed that only $\overline{I_{\mathit{OUT}}}$ at an order of nA could be obtained. V_OUT was 0.2 V–0.3 V, even with V_DD = 0.5 V, due to the reverse leakage current being larger than the forward current. In order to obtain P_OUT = 4 μW with AC-DC CP, it is necessary to set C = 3 nF (see Figure 3). Therefore, the total capacitance of 3 × 9 = 27 nF is required. Since the capacitor has capacitance of 2 fF/μm², an area of 27 nF was estimated to be 14 mm². It is too large to implement the AC-DC CP in an IC. Therefore, the pump capacitors must be composed of discrete elements. On the other hand, the proposed circuit can be integrated in a small area of 0.11 μm², as shown in Figure 10.

A comparison of the power distribution between the AC-DC CP and the proposed circuit was estimated for P_OUT of 4 μW, as shown in Figure 26. P_EH was calculated from Equation (16). P_RE is reactive power and P_LOSS is the power consumed by the CP. Compared with the AC-DC CP, the proposed circuit requires more power for OSC. In addition, the power loss due to the parasitic elements increased due to higher clock frequency. However, all the additional power is converted from P_RE. Therefore, the proposed circuit can have a higher power factor than the AC-DC CP.

Even though P_OUT increases with the proposed clocked AC-DC CP, there should be room to increase more because the impedance at the interface between EH and CP is significantly mismatched in the current design. The input impedance of CP was estimated to be about 4 kΩ, whereas the output impedance of transducer was 500 Ω. Design optimization would be needed in a future work.

4.2. AC-DC-DC CP

Figure 3 shows an AC-DC-DC CP. AC-DC-DC CP smooths the AC voltage output from the energy transducer to DC, and then boosts the input DC voltage to a higher DC voltage by CP. AC-DC conversion can be performed by an NMOS diode, as shown in Figure 4a. Figure 27 shows the simulation results of V_OUT-$\overline{I_{\mathit{OUT}}}$ for the proposed circuit and AC-DC-DC CP with the same parameters as N = 9, C = 10 pF, f_IN = 1 kHz, f_CLK = 1 MHz, V_DD = 0.5 V, and R_EH = 500 Ω. V_REC of the AC-DC-DC CP was 0.25 V due to a threshold voltage of the NMOS diode V_THD of 0.13 V, whereas that of the clocked AC-DC CP was 0.4 V. A reduction in V_REC by 0.15 V resulted in a reduction in the maximum available output voltage by 1.5 V, which can be estimated by ΔV_REC × (N + 1). C_REC of about 500 nF is needed to have a moderate ripple voltage in V_REC of 10 mV at f_IN = 1 kHz. As a result, AC-DC-DC CP requires a decoupling capacitor inside in addition to a filtering capacitor for V_OUT.

Figure 28 shows that $\overline{I_{\mathit{OUT}}}$ of the AC-DC-DC CP with N diodes started to flow at V_DD = 0.5 V, whereas the proposed circuit can operate at V_DD = 0.3 V. In the case of AC-DC-DC CP, when V_DD < 0.5 V, the voltage becomes lower than the threshold voltage of the MOS transistor, and thus it cannot operate. To have P_OUT ≥ 1 μW, the AC-DC-DC CP requires V_DD of 0.6 V, whereas the clocked AC-DC CP requires that of 0.4 V. As a result, a cold start voltage can be reduced with the clocked AC-DC CP in comparison with the AC-DC-DC CP. In the range of V_DD > 1 V, if process technology allows, the conventional circuit exceeds $\overline{I_{\mathit{OUT}}}$ of the proposed circuit. Since the input voltage of the proposed circuit is AC, CP and OSC operate only in a part of one half cycle, i.e., from θ_S to π – θ_S. On the other hand, the conventional DC-DC CP continues to be driven by a clock with a constant voltage amplitude. Therefore, when the V_DD of the conventional circuit becomes sufficiently high, higher $\overline{I_{\mathit{OUT}}}$ is obtained.

Figure 29 shows simulated η_TOT. The clocked AC-DC CP had the highest η_TOT of 22% at V_DD of 0.5 V, while the AC-DC-DC CP had η_TOT of 18% at V_DD of 0.8 V. The clocked AC-DC CP had a lower operation voltage than the AC-DC-DC CP did in terms of η_TOT as well as $\overline{I_{\mathit{OUT}}}$. Previous studies [9,10] have reported AC-DC conversion with active diodes that can reduce the voltage drop due to the diode threshold voltage, as shown in Figure 4b. The comparator compared the magnitude of V_REC with that of V_DD. When V_REC became lower than V_DD, PMOS was turned on with the low gate voltage and C_REC was charged. Figure 28 and Figure 29 respectively show $\overline{I_{\mathit{OUT}}}$ and η_TOT of the AC-DC-DC CP, which were estimated by assuming V_THD = 0 V when the active diode was used. The input power of the operational amplifier was assumed to be 1 μW. In the range of V_DD ≥ 0.5 V, AC-DC-DC CP with active diodes provided higher $\overline{I_{\mathit{OUT}}}$ than the proposed circuit. Because the input power of the operational amplifier was required, η_TOT became lower in the circuits with active diodes. In order to operate the operational amplifier, it is necessary to provide a power source. If V_REC is used as the power source for the operational amplifier, a passive diode must be connected in parallel with the active diode for cold start. Thus, the proposed AC-DC CP can have a lower cold start voltage than AC-DC-DC CPs with a lower number of discrete components.

4.3. Comparison with Previous Researche

Table 2. Comparison on the characteristics.

	ET *	Boosting Method	Discrete Element (Values) *	Circuit Area	Maximum fIN	Power Efficiency				CMOS
						VDD	VOUT	POUT	REH
[8]	EM	AC-DC CP	3C + 4D (N.A.)	Discrete	N.A.	25% (ηTOT)				-
						N.A.	2 V	30 μW	N.A.
[9]	EM	AC-DC-DC CP	1C (10 nF)	0.58 mm2 + 4.84 mm2	10 kHz (Est.)	37% (ηSYS)				0.35 μm
						1.2 V	2 V	33 μW	2k Ω
[10]	EM	AC-DC-DC CP	1C (1 μF)	N.A.	30kHz	13% (ηTOT)				90 nm
						0.5 V	1.8 V	3.2 μW	180 Ω
[11]	EM	Rectifier + switching regulator	1L (N.A.)	1.6 × 1.6 mm2	N.A.	67% (ηSYS)				0.18 μm
						0.6 V	1 V	1 mW	120 Ω
This work	MS	Clocked AC-DC CP	None	0.11 mm2	100 kHz or higher	23% (ηTOT), 6% (ηSYS)				65 nm
						0.5 V	2 V	4.2 μW	500 Ω

* ET: energy transducer, EM: electromagnetic, MS: magnetostrictive, C: chip capacitor, D: chip diode, L: chip inductor.

shows a comparison of the proposed circuit with existing voltage boosting circuits for vibration energy harvesting in the literature.

Existence of external elements, integrated circuit area, input/output condition, power efficiency, and technology used are shown. The maximum f_IN is defined by the highest frequency at which the output power is reduced by 10% from the nominal value. The proposed clocked AC-DC charge pump allows ET to operate at a frequency at least as high as 100 kHz. Due to the limitation of the measurement tool, we performed the experiment at 100 kHz or lower. Note that each paper used either η_TOT or η_SYS defined by Equations (15) and (17), respectively, for the definition of power efficiency. Compared with the previously reported circuits, the proposed circuit is only the circuit capable of obtaining an output power of an order of μW at 2 V without discrete elements. It has the smallest integrated circuit area. The authors have no appropriate way to compare power efficiency in different conditions at this point. Although the power efficiency is lower than those of the other circuits, the proposed one can be the best option when the highest priority is to generate a microwatt output power with the lowest cost and the smallest form factor. η_SYS of this work is higher than that of [10]. This could simply be because P_EH of this work was smaller due to 2 × larger R_EH. Technology is not a significant contributor to better performance. The threshold voltage of switching transistors is critical to have a low operating voltage.

5. Future Work

In this study, only a continuous wave at a resonant frequency of the transducer was considered. Under a realistic environment, both acceleration and operating frequency vary in time. Modeling of the proposed circuit and measurement will be required to design a clocked AC-DC CP for actual use. In addition, the output voltage was not regulated internally in this work. For actual use, a control circuit must be designed to stabilize V_OUT in the circuit system as shown in [23]. Furthermore, optimum design methodology needs to be established to design an optimum clocked AC-DC CP under a given condition, taking power matching at the interface between EH and CP into account. A maximum power point tracking was not considered for the clocked AC-DC CP either. It should be considered in the future.

6. Conclusions

A fully integrated clocked AC-DC charge pump circuit system was proposed, designed, and verified for vibration energy harvesting. The frequency of the clock to drive an AC-DC charge pump was upconverted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. Even with an energy transducer with R_EH of 500 Ω and an open circuit voltage amplitude of 0.5 V, one can obtain 4.2 μW power at 2 V with a minimal area overhead of 0.11 mm² without using large discrete capacitors when the input frequency of 1 kHz is increased to 4.8 MHz by the on-chip oscillator. As a result, it is possible to integrate the voltage multipliers in IoT chips for vEH. In addition, the proposed circuit has negligibly small dependency of P_OUT on f_IN. A universal design can be applied to various energy transducers with different resonant frequencies. The fabricated clocked AC-DC CP was measured with a magnetostrictive transducer. P_OUT of 2 μW–30 μW was obtained with α of 0.2 G to 0.7 G at V_OUT of 2 V. Compared with the previously reported circuits, the proposed circuit is only the circuit capable of obtaining an output power of a microwatt order at 2 V without discrete elements.