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Open AccessArticle

A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter

1
Hanwha Defense, Seongnam 13488, Korea
2
LG Electronics, Seoul 07336, Korea
3
Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea
4
Department of Electrical Engineering, Kunsan National University, Gunsan, Jeollabuk-do 54150, Korea
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(12), 2195; https://doi.org/10.3390/electronics9122195
Received: 19 October 2020 / Revised: 11 December 2020 / Accepted: 16 December 2020 / Published: 19 December 2020
(This article belongs to the Special Issue Power Electronics in Industry Applications)
This paper proposes a novel pulse width modulation (PWM) for a three-level neutral point clamped (NPC) voltage source inverter (VSI). When the conventional PWM method is used in three-level NPC VSI, dead time is required to prevent a short circuit caused by the operation of complementary devices on the upper and lower arms. However, current distortion is increased because of the dead time and it can also cause a voltage unbalance in the dc-link. To solve this problem, we propose a zero dead-time width modulation (ZDPWM) which does not require dead time used in complementary operation. The proposed technique applies the offset voltage to the space vector pulse width modulation (SVPWM) reference voltage for the same modulation index (MI) as the conventional SVPWM, but any complementary switching operation needs dead time. In addition, the proposed method is divided into four operation sections using the reference voltage and phase current to operate switching devices which flow the current depending on the section. This ZDPWM method is simply implemented by carrier and reference voltage that reduce the current distortion, because complementary operation that needs dead time is not implemented. However, the operation section is delayed due to the sampling delay that occurs during the experiment. Therefore, in this paper, we conduct a modeling of sampling delay to improve the delay of operation section. To verify the principle and feasibility of the proposed ZDPWM method, a simulation and experiment are implemented. View Full-Text
Keywords: three-level NPC VSI; zero dead-time PWM; sampling delay; current distortion three-level NPC VSI; zero dead-time PWM; sampling delay; current distortion
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MDPI and ACS Style

Kang, J.-W.; Hyun, S.-W.; Kan, Y.; Lee, H.; Lee, J.-H. A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter. Electronics 2020, 9, 2195. https://doi.org/10.3390/electronics9122195

AMA Style

Kang J-W, Hyun S-W, Kan Y, Lee H, Lee J-H. A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter. Electronics. 2020; 9(12):2195. https://doi.org/10.3390/electronics9122195

Chicago/Turabian Style

Kang, Jin-Wook; Hyun, Seung-Wook; Kan, Yong; Lee, Hoon; Lee, Jung-Hyo. 2020. "A Novel Zero Dead-Time PWM Method to Improve the Current Distortion of a Three-Level NPC Inverter" Electronics 9, no. 12: 2195. https://doi.org/10.3390/electronics9122195

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