# Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Literature Review

#### 2.1. Current Conveyors

_{i}

_{2}) and a common-source transistor (M

_{i}

_{1}) in the form of a negative feedback loop. The voltage V

_{i}at the input of M

_{i}

_{2}increases when the current I

_{i}is greater than the rest. This enlarges the common voltage Vc and reduces the gate-source voltage (V

_{GS}) of all voltage followers except M

_{i}

_{2}, switching off the corresponding devices as a result. The voltage Vc will eventually be proportional to the highest input, and the output current Io can be generated through Vc coupled to the gate of the output transistor (Mo). A problem of Lazzaro’s circuit is the presence of the interconnection parasitics, which slows down the operation. Another shortcoming comes from the reduced precision when increasing the number of identical cells for a lowered mismatch. Matching also trades with the device sizes and, consequently, the silicon area.

_{x}decreases such that its output exhibits a logical “1”. The inhibitory feedback decreases V

_{c}of other cells, increasing V

_{x}such that a logical “0” appears in their output. The excitatory feedback has an opposite impact on the winning signal. Node V

_{x}of the winning cell is consequently reduced by increasing the input current. Since the input current is compared with the average of all inputs, the inhibitory and excitatory feedback will provide a hysteretic mechanism that prevents the selection of a potential winner unless it is stronger than the selection [20]. With a wide input current range, the above-described mechanism is well-suited for high-speed, high-precision applications.

_{Ai}), which includes a negative shunt feedback (via M

_{Ci}), enabling the sink of large currents by keeping constant the voltage of the current sensing device. All the FVF cells are coupled to a low-impedance common Vc. The implementation is essentially a maximum current selector since its output current Io follows the maximum between I

_{1}and In. Its main advantage is the modest V

_{GS}+2Vov supply voltage requirement, in which Vov is the transistors’ overdrive voltage.

_{oA}as a voltage-controlled current source, with node U common for all M

_{i}

_{A}devices. Within each cell, M

_{i}

_{C}converts the input current I

_{i}into a proportional drain voltage. The source-to-gate voltages of M

_{iB}compete at node U, and the maximum voltage corresponding to the smallest input current is considered the winner [25]. The architecture is simple, low-power, and modular.

_{8}and M

_{9}constitute the excitatory and inhibitory circuits, respectively. The additional feedback enhances the resolution without introducing any extra stage.

_{wi}in each cell is to establish an effective feedback mechanism. The minimum input current generates the largest voltage at Ci, and the relevant M

_{ui}sinks current from Ib so as to copy the lowest input current to the output. High-speed operation can be reached with high accuracy levels at the expense of more power consumption and area. The minimum voltage supply is also increased because of cascade current mirrors.

#### 2.2. Binary Tree WTA Circuits

#### 2.3. Time-Domain WTA/LTA Circuits

## 3. Comparison and Discussions

## 4. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**The commonly used approaches used for integrating WTA/LTA circuits: (

**a**) current conveyor, (

**b**) binary tree, and (

**c**) time domain.

**Figure 2.**Lazzaro’s circuit as described in [1].

**Figure 3.**The WTA circuit addressed in [9].

**Figure 4.**The WTA circuit presented in [13].

**Figure 6.**Current-mode FVF-based WTA circuit presented in [21].

**Figure 7.**The LTA circuit reported in [25].

**Figure 8.**The WTA cell presented in [27].

**Figure 11.**A WTA maximum (MAX)network topology [17].

**Figure 12.**The WTA network addressed in [26].

**Figure 14.**The neuro-WTA cell shown together with the current source and inverter common for all cells presented in [19].

**Figure 15.**General scheme of the WTA/LTA block used in [35].

**Figure 16.**Scheme of the time-domain WTA presented in [47]: (

**a**) system-level implementation and (

**b**) transistor-level implementation of VCDL block.

[20] | [27] | [38] | [33] | [12] | [48] | [49] | [10] | [16] | [22] | [18] | [28] | [30] | [39] | [43] | [47] | ||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

Technology [µm] | 0.35 | 0.35 | 0.18 | 0.35 | 0.35 | 2.00 | 0.18 | 0.045 | 2.40 | 0.80 | 0.60 | 0.35 | 0.18 | 0.50 | 0.18 | 0.04 | 0.13 |

Supply Voltage [V] | 3.3 | 3.3 | 1.0 | 2.5 | 3.3 | 5.0 | 0.3 | 1.0 | 5.0 | 6.0 | 3.0 | 3.3 | 0.8 | 3.3 | 1.8 | 0.9 | 0.5 |

No. Inputs | 8 | 8 | 8 | 3 | 5 | 2 | 3 | 2 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 16 | 3 |

Precision [%] | 96.4 | 99.95 | 99 | 99.6 | 99.8 | - | - | - | 99.0 | - | - | - | 99.5 | - | 99.0 | - | 99.6 |

Operating Frequency [MHz] | 29 | 83 | 3.5 | 10 | - | - | 0.04 | 0.04 | 13.8 | 2.8 | 20 | 1 | 0.383 | 5 | 50 | 250 | 1 |

Power per Input [µW] | 22.5 | 87.5 | 10 | - | 22 | 400 | - | 0.062 | 200 | 120 | 284 | 70 | 0.36 | 106 | 15.75 | 72 | 0.25 |

Area per cell [µm ^{2}] | 569 | 569 | - | - | 110 | 32,500 | 217 | 150 | 11,200 | - | - | - | - | 60,000 | - | - | 280 |

FoM [µW/MHz] | 0.77 | 1.05 | 2.85 | - | - | - | - | 1.55 | 14.5 | 43.5 | 14.3 | 71.5 | 0.93 | 21.30 | 0.31 | 0.29 | 0.25 |

Architecture | CC | CC | CC | CC | CC | CC | CC | CC | BT | BT | BT | BT | BT | BT | BT | BT-TD | TD |

Meas./Sim. | Meas. | Sim. | Sim. | Sim. | Meas | Meas | Meas | Meas | Meas | Sim. | Sim. | Meas | Meas | Sim | Sim | Meas. |

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**MDPI and ACS Style**

Rahiminejad, E.; Aminzadeh, H.
Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison. *Chips* **2023**, *2*, 262-278.
https://doi.org/10.3390/chips2040016

**AMA Style**

Rahiminejad E, Aminzadeh H.
Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison. *Chips*. 2023; 2(4):262-278.
https://doi.org/10.3390/chips2040016

**Chicago/Turabian Style**

Rahiminejad, Ehsan, and Hamed Aminzadeh.
2023. "Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison" *Chips* 2, no. 4: 262-278.
https://doi.org/10.3390/chips2040016