Total Harmonic Distortion Analysis of a Seven-Level Inverter for Fuel Cell Applications ^†

Abstract

This paper focuses on the total harmonic distortion (THD) analysis of a multi-level inverter (MLI) for fuel cell applications. Furthermore, a 50 kW 625 V proton exchange membrane fuel cell (PEMFC) stack was employed for this analysis. The various modes of operation of the suggested inverter are presented accordingly, along with its switching combinations. Also, a sinusoidal pulse-width modulation (SPWM) controller was employed to drive the power electronic switches in the suggested topology. The suggested inverter can produce sinusoidal voltage with only fundamental frequency switching. Moreover, the number of components and voltage stress of the suggested topology are compared with the conventional topologies presented. In addition, the THD was analyzed with and without the LC filter. Finally, the validity of the system was verified through MATLAB/Simulink software R2022b.

1. Introduction

Advanced power electronic inverters are necessary to meet the high-power demands of electric vehicles (EVs) and hybrid electric vehicles [1,2]. The production of large electric drive trains for these vehicles would lead to increased fuel efficiency, lower emissions, and probably better performance of the vehicles [2,3].

Owing to their high VA ratings, multilevel inverters (MLIs) are uniquely appropriate for EV applications [3,4]. They can easily produce the desired voltage from multiple levels of DC voltage to provide suitable power for EV or HEV drives [5]. The produced output can be obtained using a staircase approach, depending on the incremental levels that lead to the required voltage waveform. Furthermore, if the number of levels increased in output waveform, this would help reduce the total harmonic distortion as well as stress across the power electronic components [6,7].

Furthermore, a suitable power electronic switch is required for high-power applications to meet industry requirements [8,9]. An insulated gate bipolar transistor (IGBT) has a high power rating and high-voltage stress features for use in high-frequency applications [10]. Thus, a metal–oxide semiconductor field-effect transistor (MOSFET) is a suitable component for high-frequency operation.

Nevertheless, its power rating is poor relative to an IGBT. Several different multilevel topologies use low-rating switches for high-power applications to solve this problem [11,12]. The benefits of multilevel topology are lower switching frequency, low dv/dt, and low-input current distortion. Hence, it is usually used in high-power applications [13].

In addition, it has been demonstrated that the inverter can choose a fundamental frequency switching pattern to create a nearly sinusoidal output while simultaneously maintaining the dc voltage level of the capacitors.

After rapid research, many structures and modifications have been developed in multi-level inverters. Among all topologies, the major structures are cascaded multi-level configurations, the neutral point (diode clamped), and the flying capacitor (capacitor clamped) [14]. A cascaded multi-level inverter can be used for increasing the number of levels owing to its modularization, ease of execution, and lower expense. Nevertheless, the cost of the system is increased due to its incremental levels and reduced inverter efficiency. In addition, the lower number of levels leads to considerably high values of the LC filter to mitigate the harmonics [15]. In [16], a single-phase seven-level transformer-less inverter was discussed; it seems a greater number of power electronic devices were utilized for each voltage response, leading to high power loss. An MLI technique was suggested in [17,18], which considered a single power switch and diode coupled with a traditional H-bridge in order to control each additional source of dc inputs. As a result, the component count increased and power-sharing between sources was unequal. Indeed, in [19], a modular MLI with a reduction in power electronic components and usage of excessive dc sources was suggested, but complexity in the controller made the execution slow to generate multilevel voltage responses.

The main objectives of the suggested topology are as follows:

• To produce sinusoidal voltage using only fundamental frequency switching.
• To reduce the power components of the suggested topology.
• To minimize the total harmonic distortion (THD) of the suggested topology.

2. Suggested Topology

The fuel cell-based system is represented in the block diagram depicted in Figure 1. The fuel cell acts as an input for the corresponding system to operate the load. In this article, an effective inverter topology is suggested to meet the load demand. The suggested topology is used to generate the seven-level output.

The suggested topology displayed in Figure 2 consists of three capacitors, C₁, C₂, and C₃, connected in series, which are parallel to the dc source. The shared voltage among the capacitors is transferred to an H-bridge through four MOSFETs along with four diodes. In addition, the H-bridge is formed by two legs, with two MOSFETs for each leg, in order to produce a seven-level response with effective gating signals.

Modes of Operation

This topology is operated in seven modes to obtain the seven-level response; i.e., $\pm \frac{1}{3}{V}_{dc}, \pm \frac{2}{3}{V}_{dc}, {\pm V}_{dc},$ and 0 is as follows:

• In mode 1 operation, the capacitor discharges the energy to the load via S₁, S₅, S₈, and D₂ during the positive half cycle. The voltage response across the load is $+\frac{1}{3}{V}_{dc}$. The current direction is displayed in Figure 3.

• In mode 2 operation, the voltage across capacitors C₁ and C₂ is transmitted to the load through switches S₁, S₅, S₈, S₄, and D₄, and the voltage response is $+\frac{2}{3}{V}_{dc}$. The current direction is displayed in Figure 4.

• In mode 3, the three capacitors’ (C₁, C₂, and C₃) voltages are fed to the load via S₁, S₂, S₅, and S₈. The voltage response across the load is $+V_{dc}$, and the corresponding current direction is displayed in Figure 5.

• In mode 4, during the negative half cycle capacitor C₃ discharges the voltage to the load through switches D₁, S₇, S₆, and S₂. The voltage response across the load is ${-\frac{1}{3}V}_{dc}$, and its current direction is shown in Figure 6.

• In mode 5, capacitors C₂ and C₃ provide voltage to the load through switches D₃, S₃, S₇, S₆, and S₂. The corresponding voltage across the terminal is ${-\frac{2}{3}V}_{dc},$ and its current direction is displayed in Figure 7.

• In mode 6, all capacitors (C₁, C₂, and C₃) produce voltage across the load as $-V_{dc}.$ The current direction is displayed in Figure 8. During this mode of operation, the corresponding switches S₁, S₇, S₆, and S₂ are turned on.

• In mode 7, the voltage generated across the load is zero. Switches S₅ and S₇ are turned on during this mode of operation. The corresponding current flow direction is displayed in Figure 9. The detailed switching combinations of seven-level response is shown in the

  Table 1. Switching combinations of the seven-level response.

  Voltage Response	S1	S2	S3	S4	S5	S6	S7	S8
  1/3 Vdc	ON	OFF	OFF	OFF	ON	OFF	OFF	ON
  2/3 Vdc	ON	OFF	OFF	ON	ON	OFF	OFF	ON
  Vdc	ON	ON	OFF	OFF	ON	OFF	OFF	ON
  −1/3 Vdc	OFF	ON	OFF	OFF	OFF	ON	ON	OFF
  −2/3 Vdc	OFF	ON	ON	OFF	OFF	ON	ON	OFF
  Vdc	ON	ON	OFF	OFF	OFF	ON	ON	OFF
  0	OFF	OFF	OFF	OFF	ON	OFF	ON	OFF

  is as follows.

3. Results and Discussion

In this study, the suggested topology was assessed using conventional seven-level inverter topologies [20,21] displayed in the following tables. The components required to generate a seven-level response of the inverters are shown in

Table 2. Components comparison of seven-level inverters.

Components	Cascaded Multi-Level [15]	Diode-Clamped Multi-Level [14]	Capacitor-Clamped Multi-Level [13]	Suggested
Power switches	12	12	12	8
Input capacitors	3	6	2	3
Diodes	0	10	0	4
Input sources	3	1	1	1
Clamped capacitors	0	0	5	0

. The voltage stress of the suggested topology as compared with conventional topologies is presented in

Table 3. Comparison of seven-level inverters’ voltage stresses.

	Cascaded Multi-Level [15]	Diode-Clamped Multi-Level [14]	Capacitor-Clamped Multi-Level [13]	Suggested
Diodes	-	3 V0/2	-	2 V0/3
Input capacitors	V0/3	V0/3	V0/2	V0/3
Input sources	V0/3	2 V0	2 V0	V0
Power switches	V0/3	V0/3	V0/3	V0

.

The suggested topology based on fuel cells implemented in Simulink software is presented in Figure 10. A 50 kW 625 V proton exchange membrane fuel cell (PEMFC) stack is used to generate a seven-level response for the MLI.

The seven-level AC output generated without the LC filter is depicted in Figure 11, and the corresponding response with the LC filter is displayed in Figure 12. It was observed that a voltage of 830 V obtained from a voltage of 625 V input seemed to boost this feature, and could be used for high voltage applications. The current response across the load was almost sinusoidal for a fundamental frequency of 50 Hz with an amplitude of 5.2 A. Simulation results show that the suggested inverter could generate the desired output voltage.

A SPWM was used in this study to generate a sinusoidal waveform by controlling the duty cycle of the pulse width-modulated signal. The SPWM controller implemented in this study to obtain the gating signals for the power electronic switches is shown in Figure 13 and Figure 14, respectively. It was based on the concept of comparing a reference sinusoidal waveform with a triangular waveform, which is typically a high-frequency triangular wave from. The widths of the pulses in the carrier waveform were adjusted in such a way that they matched the instantaneous value of the reference wave form, and the generated signal given to the power electronic switches of the suggested inverter is shown in Figure 13.

The suggested MLI, without and with the LC filter, had total harmonic distortions of 18.86% and 2.29%, respectively, as shown in Figure 15 and Figure 16. It was observed that the THD level was reduced when the MLI was connected to the LC filter.

4. Conclusions and Future Scope

A reduced-components MLI topology that could produce seven-level output was designed using the SPWM technique, and implemented using MATLAB/Simulink. The suggested MLI has the following advantages as compared with conventional inverters:

• The suggested topology with the minimum active number of components can be easily extended to nine-level or higher output.
• Owing to switching frequency at 50 Hz, switching losses nearly equal zero.
• The seven-level response is generated using one H-bridge.
• The number of capacitors utilized in this suggested topology is lower compared to those used in a conventional cascaded H-bridge multilevel inverter.
• The THD can be still reduced by increasing the number of levels, and using advanced PWM techniques can reduce loss.