A 13-Bit 100 kS/s Two-Step Single-Slope ADC for a 64 × 64 Infrared Image Sensor

Abstract

An Analog-to-Digital Converter (ADC) is an indispensable part of image sensor systems. This paper presents a silicon-based 13-bit 100 kS/s two-step single-slope analog-to-digital converter (TS-SS ADC) for infrared image sensors with a frame rate of 100 Hz. For the charge leakage and offset voltage issues inherent in conventional TS-SS ADC, a four-terminal comparator was employed to resolve the fine ramp voltage offset caused by charge redistribution in storage and parasitic capacitors. In addition, a current-steering digital-to-analog converter (DAC) was adopted to calibrate the voltage reference of the dynamic comparator and mitigate differential nonlinearity (DNL)/integral nonlinearity (INL). To eliminate quantization dead zones, a 1-bit redundancy was incorporated into the fine quantization circuit. Finally, the quantization scheme consisted of 7-bit coarse quantization followed by 7-bit fine quantization. The ADC was implemented using an SMIC 55 nm processSemiconductor Manufacturing International Corporation, Shanghai, China. The post-simulation results show that when the power supply is 3.3 V, the ADC achieves a quantization range of 1.3 V–3 V. Operating at a 100 kS/s sampling rate, the proposed ADC exhibits an effective number of bits (ENOBs) of 11.86, a spurious-free dynamic range (SFDR) of 97.45 dB, and a signal-to-noise-and-distortion ratio (SNDR) of 73.13 dB. The power consumption of the ADC was 22.18 mW.

1. Introduction

The primary function of an image sensor is to convert the captured scene into storable electrical signals. Its operation consists of two main phases: photoelectric conversion and ADC quantization. Based on the intensity of incident light, the optical signal collected on the photosensitive surface is converted into a corresponding voltage signal. This voltage is then processed through correlated double sampling (CDS) to produce a refined analog signal, which is subsequently quantized by the ADC to generate discrete digital output. In infrared image systems, ADC serves as a key component for digitizing photoelectric signals. Its conversion accuracy and efficiency have a direct impact on the data acquisition speed and the quality of image reconstruction. Currently, image sensors primarily adopt three kinds of ADC structures: single-channel ADC, column-parallel ADC and pixel-level ADC [1]. The parallel structure of column-parallel ADC makes its speed superior to single-channel ADC and enables multi-channel parallel analog-to-digital conversion across the pixel array. The off-pixel quantization structure of the column-parallel ADC makes its design complexity lower than the pixel-level ADC. A column-parallel ADC becomes the mainstream structure in modern image sensor applications. Column-parallel ADC contains various structures, and the structures applied to image sensors are successive approximation register (SAR) ADC, cyclic ADC, and single-slope (SS) ADC. The SAR ADC features a simple structure and low power consumption. It completes an N-bit quantization in N clock cycles [2]. However, increasing the resolution by one bit doubles the number of switches and capacitors required, which results in a significant area overhead. The cyclic ADC, similar to the SAR ADC, also requires N clock cycles for N-bit quantization. Without large capacitors, the cyclic ADC occupies less area [3]. However, the high-gain operational amplifiers of cyclic ADC lead to higher power consumption. Compared with cyclic ADC and SAR ADC, the SS ADC benefits from its simple structure, low power consumption, small area, and the ability of the slope generator to generate high-resolution and high-linearity ramp signals. However, it requires 2^N clock cycles to complete N-bit quantization, which significantly limits its conversion speed [4].

To address the limited conversion speed of SS ADC, two-step structures based on a single slope have been proposed. The most common include multiple-ramp single-slope (MRSS) ADC and two-step single-slope (TS-SS) ADC. Reference [5] proposed an MRSS ADC that utilizes a coarse ramp generator to perform high 3-bit quantization and fine ramp generators operating at different voltage to perform low 8-bit quantization. Although this structure significantly improves conversion speed, there are issues with voltage range misalignment and power consumption. Reference [6] introduced a TS-SS ADC that integrates coarse and fine quantization, which utilizes a sample-and-hold capacitor to store coarse quantization results. This structure implements 5-bit quantization with a coarse ramp generator and a 6-bit quantization with fine ramp generator. An additional redundant bit is included. This design addresses the power issue of MRSS ADC but remains sensitive to parasitic capacitance, which may lead to voltage shifting during fine quantization and create quantization dead zones. Reference [7] employed a four-input comparator in TS-SS ADC to separate the high 7-bit coarse quantization and low 8-bit fine quantization. This structure avoids signal mismatch between coarse and fine ramps and prevents degradation of the fine ramp slope. Despite these advantages, the resolution remains a major limitation. Reference [8] applied the Look-Up-Table (LUT) calibration technique to TS-SS ADC. This approach corrects parasitic capacitance errors and improves linearity. After calibration, the ENOB of SS ADC improves from 6-bit to 11.77-bit. Reference [9] applied a multi-column shared capacitor DAC to TS-SS ADC, which significantly reduces the area constraints imposed by column pitch. However, this structure still faces limitations in speed and increased control complexity. Reference [10] proposed a TS-SS ADC with a detachable DAC. A high-linearity coarse ramp signal is generated by the DAC, and this design achieves an INL of −0.89/+1.04 LSB and a DNL of −0.67/+0.91 LSB. Nevertheless, it still suffers from charge injection errors and limited system integration. Reference [11] implemented 14-bit quantization using a two-step ADC based on a 7-bit capacitor array. DAC is employed to adjust the reference voltage, which can enhance resolution. After calibration, the SNDR improved from 73.41 dB to 81.52 dB. However, the increase in resolution came at the cost of higher circuit complexity and reduced stability. Reference [12] integrated a variable gain amplifier (VGA) into a hybrid SAR-SS ADC. In this design, the SS ADC performs 3-bit quantization, and only 8-bit SAR ADC is required to achieve an ENOB of 11-bit. Unfortunately, the introduction of redundant bits leads to an inherent error of 1.5 LSB, and the D-flip-flop scanning scheme accounts for 45% of the total power consumption. Moreover, the dynamic range is limited to 58.3 dB. Reference [13] eliminated the use of the hold capacitor to reduce the load on ramp generators, which minimizes errors caused by mismatch and offset between fine ramps. During the coarse quantization phase, the coarse quantization switch is immediately turned off once the comparator completes the comparison of the 4-bit counter. As a result, the power consumption is only 90 μW, whereas the resolution is 12-bit. However, gain mismatch between the coarse and fine ramps leads to periodic fluctuations in DNL, and the area of the control logic limits the scalability of the coarse quantization resolution. Reference [14] introduced error feedback into noise-shaping ADC. This design uses a second-order switched-capacitor FIR filter and a charge-sharing technique to achieve optimized complex zeros and robust second-order noise shaping. Although it attains an ENOB of 12.83, the design also faces challenges such as increased design complexity and limited system flexibility. Reference [15] proposed a multi-slope column-parallel ADC that enhances conversion speed and introduces compression characteristics through multiple reference slopes. This structure significantly improves the performance-to-power ratio of CMOS image sensors but also presents challenges in control complexity and slope error management. Reference [16] proposed a high-precision, low-area-overhead calibration circuit to address the current ratio mismatch in Dual-Ramp Single Slope (DRSS) ADC. Through structural optimizations, such as the reset scheme, switch isolation, and auto-zero comparator, the design significantly enhances DNL performance. However, the calibration logic falls under foreground calibration, which lacks the ability to dynamically adapt online. As a result, it exhibits limited real-time adaptability to variations caused by temperature drift, aging, or bias drift. Reference [17] employed a pre-comparator to divide pixel signals into small- and large-signal regions. When quantizing large pixel signals, the TS-SS ADC enters an accelerated mode and significantly enhances conversion speed through differential ramping. However, this approach incurs additional circuit area and power consumption, which may constrain large-scale integration in high-resolution arrays.

Compared with MRSS ADC, TS-SS ADC stores the intermediate voltage of coarse quantization by sample capacitors and implements low-bit conversion with a single fine ramp generator. This optimized design preserves the accuracy advantages of multi-level quantization and addresses the issues of area and power consumption. However, charge leakage through the coarse ramp switch during quantization can cause errors on the storage capacitor plate, thus affecting fine quantization. However, the coarse ramp switch will cause charge leakage during quantization. Charge leakage can introduce errors on the storage capacitor plate and consequently affect fine quantization. To address this issue, this paper grounds the bottom plate of the storage capacitor to prevent quantization errors caused by charge leakage. Compared with a traditional two-step ADC that requires an exponentially increasing number of parallel comparators or capacitor arrays in coarse quantization, the proposed TS-SS ADC employs two structurally similar ramp generators for coarse and fine quantization separately, which effectively reduces area and power consumption.

Infrared image sensors are widely employed in applications such as night vision imaging, thermal monitoring, medical diagnostics, and environmental perception. The output signals from these sensors typically exhibit low signal-to-noise ratios, small amplitudes, and significant temperature drift, which impose more stringent requirements on ADC in terms of resolution, linearity, and offset tolerance. Particularly in long-range detection or weak signal imaging scenarios, enhanced ADC resolution contributes to a broader grayscale dynamic range and significantly improves the visibility of subtle targets and the robustness of subsequent image recognition. To address the high-precision sampling demands in infrared imaging, this paper presents a design of ADC based on a Two-Step Signal-Slope structure. The proposed ADC is implemented using the SMIC 55 nm process. It employs a four-terminal comparator instead of the conventional differential comparator to enable the separation of coarse and fine quantization stages. This structure effectively mitigates the issue of fine ramp voltage offset caused by charge redistribution between sample capacitors and parasitic capacitances. In addition, a current-steering DAC is integrated to dynamically calibrate the reference voltage of the dynamic comparator. This calibration approach helps to suppress the offset voltages induced by switch nonlinearity and device mismatches, while simultaneously improving the overall performance by reducing both DNL and INL errors.

2. Circuit Design

The proposed TS-SS ADC targets a 13-bit + 1-bit quantization resolution and features three distinct quantization schemes, as detailed in

Table 1. Comparison of cycle numbers for different quantization schemes.

Coarse Quantization Resolution	Fine Quantization Resolution	Coarse Quantization Cycles	Fine Quantization Cycles	Total Cycles
6-bit	7 + 1-bit	64	256	320
7-bit	6 + 1-bit	128	128	256
8-bit	5 + 1-bit	256	64	320

. When the “7 + 7” quantization scheme is selected, it achieves the minimal cycle count and optimal conversion speed.

The block diagram of the proposed TS-SS ADC is shown in Figure 1. The ADC mainly consists of the following blocks: a sample-and-hold circuit, coarse/fine ramp generators, the DAC, a four-input comparator, and digital logic units. The operational principle is that the sample-and-hold circuit converts analog signal into a sampled V_S and applies it to the negative input of comparator V_IN. The coarse ramp generator produces a coarse ramp voltage V_{RAMP_C}, stores it in C_H, and applies it to the positive input of comparator V_CIP. The comparator compares V_IN and V_CIP. When V_CIP exceeds V_IN, the comparator inverts and the coarse quantization is completed. The coarse quantization result is stored in latch. Then, the fine ramp generator produces a fine ramp voltage V_{RAMP_F} and applies it to the positive input of comparator V_FIP. The comparator compares V_IN and V_FIP and the result is also stored in latch. Finally, the quantization results are output through the digital logic circuit.

2.1. Quantization Scheme

Sampling reset phase: Switches S_C and S_H are turned on. The coarse ramp voltage V_{RAMP_C} is connected to V_CIP through switch S_C and serves as the initial quantization voltage. The reference V_REF is connected to V_FIP through switch S_H. At this time, the comparator output is low, and the input V_IN is as follows:

$${\mathrm{V}}_{\mathrm{I}\mathrm{N}}=-{\mathrm{V}}_{\mathrm{S}}+{\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}\_\mathrm{C}}+{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}={\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}\_\mathrm{C}}-{\mathrm{V}}_{\mathrm{S}}$$

(1)

Coarse quantization phase: The states of switches remain unchanged. The sampled voltage V_S and coarse ramp voltage V_{RAMP_C} are fed into the comparator for comparison. At this time, V_{RAMP_C} jumps in steps of value I, with each step corresponding to a voltage V_{RAMP_C}[i]. The input of the comparator is as follows:

$${\mathrm{V}}_{\mathrm{I}\mathrm{N}}={\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}\left[\mathrm{i}\right]-{\mathrm{V}}_{\mathrm{S}}$$

(2)

When V_IN > 0, the comparator output switches from low to high, and the switch S_C turns off. The latch stores the binary code from the coarse quantization counter. Irrespective of the parasitic effect in the storage capacitor and charge injection from the coarse quantization switch S_C, the voltage across C_H is as follows:

$${\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}=(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}$$

(3)

$$\Delta {\mathrm{V}}_{\mathrm{C}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{F}\mathrm{S}}}{2^{\mathrm{M}}}}$$

(4)

where m is the step of the coarse ramp, M is the coarse quantization resolution, and V_FS is the full-scale voltage.

Fine quantization phase: Switches S_C and S_H turn off. Switch S_F turns on. Each step of the fine ramp corresponds to a voltage of V_{RAMP_F}[i], as follows:

$${\mathrm{V}}_{\mathrm{I}\mathrm{N}}=-{\mathrm{V}}_{\mathrm{S}}+(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}+{\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}}\left[\mathrm{i}\right]-{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}$$

(5)

As step i increases, V_IN increases. When V_IN > 0, the comparator flips. The binary code of the counter is taken as the fine quantization result.

Output results: Due to the inclusion of the redundancy bit, the coarse and fine quantization results cannot be directly added together. Instead, the results need to be processed through addition and subtraction. As shown in Figure 2, the coarse and fine quantization results are transferred from latches to an adder for summation. The first bit of coarse quantization and the seventh bit of fine quantization are added to obtain D_OUT [1:13]. Since fine quantization has been extended from 6-bit to 7-bit, a fixed offset of 27 must be subtracted by a subtractor to obtain the final binary code D_OUT [1:13] corresponding to the analog signal.

Error analysis and improvement: As observed in the coarse quantization phase, parasitic effects in the storage capacitor C_H and the charge injection caused by S_C will change the voltage across C_H, which results in deviation of the coarse quantization result. Assuming W and L are the width and length of switch S_C, m is the coarse quantization result, δ is the proportion of charge injected into the capacitor, and the amount of charge injected into C_H by switch S_C is as follows:

$${\mathrm{Q}}_{{\mathrm{C}}_{\mathrm{H}}}=\delta (\mathrm{W}\mathrm{L}{)}_{{\mathrm{S}}_{\mathrm{C}}}{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\left[{\mathrm{V}}_{\mathrm{D}\mathrm{D}}-(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}\right]$$

(6)

The voltage variation across C_H caused by the charge is as follows:

$$\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}={\displaystyle \frac{\delta \left(\mathrm{W}\mathrm{L}{)}_{{\mathrm{S}}_{\mathrm{C}}}{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\right[\mathrm{V}\mathrm{D}\mathrm{D}-(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}-{\mathrm{V}}_{\mathrm{T}\mathrm{H}}]}{{\mathrm{C}}_{\mathrm{H}}}}$$

(7)

To ensure the performance of the proposed ADC, $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$ must be less than 0.5 LSB.

Combining with Equation (3), the voltage of the storage capacitor C_H increases from $\left(\mathrm{m}+1\right)\Delta \mathrm{V}$ to $(\mathrm{m}+1)\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$. It can be seen that $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$ is related to m. Taking the derivative with respect to m, we obtain the following:

$${\displaystyle \frac{\sigma \Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}}{\sigma \mathrm{m}}}={\displaystyle \frac{\delta \left(\mathrm{W}\mathrm{L}{)}_{{\mathrm{S}}_{\mathrm{C}}}{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\right(-\Delta {\mathrm{V}}_{\mathrm{C}})}{{\mathrm{C}}_{\mathrm{H}}}}$$

(8)

According to Equation (8), $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$ and m have a linear relationship. To mitigate the impact caused by the charge injection of $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$, a current-steering DAC is designed to dynamically compensate for the variation of $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$. After considering the error introduced by S_C, the input of the comparator during the fine quantization phase can be corrected as follows:

$${\mathrm{V}}_{\mathrm{I}\mathrm{N}}=(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}+\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}(\mathrm{m})-{\mathrm{V}}_{\mathrm{S}}-{\displaystyle \frac{3}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}+{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}+\mathrm{i}\Delta {\mathrm{V}}_{\mathrm{F}}-{\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}(\mathrm{m})$$

(9)

To ensure that the input of the comparator during the fine quantization phase matches the ideal condition,

$${\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}\left(\mathrm{m}\right)={\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}+\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$$

(10)

This paper employs three DACs to achieve the elimination of $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$. The specific structure is shown in Figure 3. The top DAC and the bottom DAC receive a 6-bit binary code to generate V_H and V_L, respectively, which serve as the voltage inputs of 7-bit DACs. The coarse quantization binary code D_COUT [1:7] is input into the 7-bit DAC, and the calibrated V_DAC is finally obtained.

Assuming N is the number of DAC bits, that is, the number of coarse quantization bits, and D is the decimal value corresponding to the DAC input binary code, then the DAC output expression is as follows:

$${\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}={\mathrm{V}}_{\mathrm{L}}+{\displaystyle \frac{\mathrm{D}}{2^{\mathrm{N}}}}({\mathrm{V}}_{\mathrm{H}}-{\mathrm{V}}_{\mathrm{L}})$$

(11)

The output expression of the top DAC is as follows:

$${\mathrm{V}}_{\mathrm{H}}=\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{T}\mathrm{O}\mathrm{P}}}{2^6}}\left[{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}+{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}-\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)\right]$$

(12)

Then:

$${\mathrm{V}}_{\mathrm{H}}=\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{T}\mathrm{O}\mathrm{P}}}{2^6}}\Delta {\mathrm{V}}_{\mathrm{C}}$$

(13)

$${\mathrm{V}}_{\mathrm{L}}=\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}}{2^6}}\Delta {\mathrm{V}}_{\mathrm{C}}$$

(14)

Therefore, the DAC output expression can also be written as follows:

$$\begin{array}{ll}{\mathrm{V}}_{\mathrm{D}\mathrm{A}\mathrm{C}}& =\left[\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}}{2^6}}\Delta {\mathrm{V}}_{\mathrm{C}}\right]\\ & +{\displaystyle \frac{{\mathrm{D}}_{\mathrm{C}\mathrm{o}\mathrm{u}\mathrm{t}}}{2^7}}\left[\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{T}\mathrm{O}\mathrm{P}}}{2^6}}\Delta {\mathrm{V}}_{\mathrm{C}}\right.\\ & \left.-\left({\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}-{\displaystyle \frac{1}{2}}\Delta {\mathrm{V}}_{\mathrm{C}}\right)-{\displaystyle \frac{{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}}{2^6}}\Delta {\mathrm{V}}_{\mathrm{C}}\right]\\ & ={\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}+\Delta {\mathrm{V}}_{\mathrm{C}}\left[{\displaystyle \frac{{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}}{2^6}}-{\displaystyle \frac{1}{2}}+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{C}\mathrm{o}\mathrm{u}\mathrm{t}}}{2^{13}}}\left({\mathrm{D}}_{\mathrm{T}\mathrm{O}\mathrm{P}}-{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}\right)\right]\end{array}$$

(15)

Combining with Equation (10), it only requires the following:

$$\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}=\Delta {\mathrm{V}}_{\mathrm{C}}[{\displaystyle \frac{{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}}}{2^6}}-{\displaystyle \frac{1}{2}}+{\displaystyle \frac{{\mathrm{D}}_{\mathrm{C}\mathrm{o}\mathrm{u}\mathrm{t}}}{2^{13}}}({\mathrm{D}}_{\mathrm{T}\mathrm{O}\mathrm{P}}-{\mathrm{D}}_{\mathrm{B}\mathrm{O}\mathrm{T}\mathrm{T}\mathrm{O}\mathrm{M}})]$$

(16)

When D_TOP and D_BOTTOM are in the default state of 100,000, V_DAC = V_REF. During circuit operation, the offset $\Delta {\mathrm{V}}_{{\mathrm{C}}_{\mathrm{H}}}$ can be eliminated by adjusting the code values of D_TOP and D_BOTTOM.

2.2. Sample-and-Hold Circuit

The structure of the sample-and-hold circuit is shown in Figure 4. This structure mainly consists of a gate-boosted switch, a sampling capacitor, an operational amplifier, and other switches. The operation is divided into two main phases: the sampling phase and the hold phase.

Sampling phase: Switches S1 and S2 are turned on, while S3 is turned off. The circuit is equivalent to a first-order RC circuit. The voltage across the sampling capacitor is V_IN, and the charge stored on C_S is as follows:

$${\mathrm{Q}}_1={\mathrm{V}}_{\mathrm{I}\mathrm{N}}{\mathrm{C}}_{\mathrm{S}}$$

(17)

Hold phase: Switches S1 and S2 are turned off, and S3 is turned on. The left plate of the sampling capacitor C_S is connected to the output of the operational amplifier, and node X is the positive input of the amplifier. According to charge conservation, we obtain the following:

$${\mathrm{C}}_{\mathrm{S}}({\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}-{\mathrm{V}}_{\mathrm{x}})={\mathrm{C}}_{\mathrm{S}}{\mathrm{V}}_{\mathrm{I}\mathrm{N}}$$

(18)

The output voltage of the hold phase is as follows:

$${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}=\mathrm{A}(-{\mathrm{V}}_{\mathrm{x}})=\mathrm{A}({\mathrm{V}}_{\mathrm{I}\mathrm{N}}-{\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}})$$

(19)

2.3. Coarse Ramp Generator

The coarse ramp generator is shown in Figure 5. It mainly consists of top and bottom clamp amplifiers, a resistor array, a decoder, and an output buffer. The two clamp amplifiers are used to define the top and bottom voltages of the ramp generator, corresponding to VH_3 and VL_1.3. The resistor array divides the voltage, whereas the output buffer enhances the driving capability. The decoder outputs different logic states, resulting in different voltage outputs from the resistor array.

The top and bottom clamp amplifiers and their respective output transistors form a three-pole system. To ensure that the output ramp signal remains free of oscillation, the stability of both the top and bottom feedback loops must be maintained. Taking the top loop as an example, the system adopts a nested Miller compensation scheme. The unity-gain bandwidth and the second and third pole frequencies are, respectively:

$$\mathrm{G}\mathrm{B}\mathrm{W}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}1}}{2\pi {\mathrm{C}}_1}}$$

(20)

$${\mathrm{f}}_{\mathrm{n}\mathrm{d}2}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}2}}{2\pi {\mathrm{C}}_2}}$$

(21)

$${\mathrm{f}}_{\mathrm{n}\mathrm{d}3}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}3}}{2\pi {\mathrm{C}}_{\mathrm{L}}}}$$

(22)

To ensure sufficient phase margin of the loop, the second and third pole frequencies should be placed as far away from the GBW (Gain Bandwidth) as possible. The second pole is set at four times the GBW, whereas the third pole is set at eight times the GBW, as follows:

$${\mathrm{f}}_{\mathrm{n}\mathrm{d}3}=2{\mathrm{f}}_{\mathrm{n}\mathrm{d}2}=8 \mathrm{G}\mathrm{B}\mathrm{W}$$

(23)

Since the dominant pole located at the GBW already contributes 90° of phase shift, the phase margin (PM) can be expressed as follows:

$$\mathrm{P}\mathrm{M}=180^{\circ }-\left(90^{\circ }+{\tan }^{-1}\left({\displaystyle \frac{\mathrm{G}\mathrm{B}\mathrm{W}}{{\mathrm{f}}_{\mathrm{n}\mathrm{d}2}}}\right)+{\tan }^{-1}\left({\displaystyle \frac{\mathrm{G}\mathrm{B}\mathrm{W}}{{\mathrm{f}}_{\mathrm{n}\mathrm{d}3}}}\right)\right)$$

(24)

Combining Equations (23) and (24), the phase margin is approximately 69°, which meets the stability requirements.

2.4. Fine Ramp Generator

The structure of the fine ramp generator is shown in Figure 6. Considering the redundancy bit, the quantization resolution of the fine ramp generator is also 7-bit. Its structure is similar to the coarse ramp generator and includes top and bottom clamp amplifiers, a resistor array, a decoder, and an output buffer.

The voltage quantization range of the fine ramp is 2ΔV_C. With V_REF = 2.15 V, the quantization interval was determined to range from 2.130078125 V to 2.156640625 V. The small quantization voltage implies that the current flowing through transistors M1 and M2 is small and results in low transconductance in the top and bottom clamp amplifiers, which does not meet the stability of the upper and lower feedback loops. Therefore, compared to the coarse ramp generator, an additional current source was added inside each clamping amplifier in the fine ramp generator and was connected to the external path to improve stability.

2.5. Comparator

The proposed TS-SS ADC performs two comparison operations in each quantization cycle, corresponding to the coarse and fine quantization phases. The structure of the four-input comparator is shown in Figure 7, which consists of a preamplifier, a dynamic comparator, and an output buffer. The two-stage preamplifier amplifies the input and reduces the impact of latch offset. The dynamic comparator carries out the comparison operation. The output buffer enhances driving capability and isolates load interference to ensure reliable output.

To reduce the impact of comparator offset and suppress kickback noise, a two-stage cascaded preamplifier structure was adopted. The first-stage preamplifier is shown in Figure 8.

The preamplifier splits the differential input pair into two paths. During the first comparison, only the coarse ramp voltage V_{RAMP_C} and the input voltage V_IN are processed by the first-stage preamplifier. The output voltage of the first-stage preamplifier is as follows:

$${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{g}}_{\mathrm{m}}({\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}\_\mathrm{C}}-{\mathrm{V}}_{\mathrm{I}\mathrm{N}})$$

(25)

During the second comparison, only the fine ramp voltage V_{RAMP_F} and the reference voltage V_REF are fed into the first-stage preamplifier. The output voltage of the first-stage preamplifier is as follows:

$${\mathrm{V}}_{\mathrm{O}\mathrm{U}\mathrm{T}}={\mathrm{g}}_{\mathrm{m}}\left[(\mathrm{m}+1)\Delta {\mathrm{V}}_{\mathrm{C}}-{\mathrm{V}}_{\mathrm{I}\mathrm{N}}+{\mathrm{V}}_{\mathrm{R}\mathrm{A}\mathrm{M}\mathrm{P}\_\mathrm{F}}-{\mathrm{V}}_{\mathrm{R}\mathrm{E}\mathrm{F}}\right]$$

(26)

where m is the coarse quantization result and ΔV_C is the voltage corresponding to each step of coarse quantization.

As shown in Figure 8, the folded input structure achieves a wide input common-mode range. A constant bias provides the tail current to ensure stable operation with different inputs. The cross-coupled structure forms positive feedback to increase transconductance. The gain of the first-stage preamplifier is as follows:

$${\mathrm{A}}_{\mathrm{v}1}={\displaystyle \frac{{\mathrm{g}}_{\mathrm{m}3}}{{\mathrm{g}}_{\mathrm{m}13}-{\mathrm{g}}_{\mathrm{m}14}}}=\sqrt{{\displaystyle \frac{(\mathrm{W}/\mathrm{L}{)}_3}{(\mathrm{W}/\mathrm{L}{)}_{13}-(\mathrm{W}/\mathrm{L}{)}_{14}}}}$$

(27)

The second-stage preamplifier consists of a differential operational amplifier with cross-coupled PMOS transistors as the load. The total gain of the preamplifiers is the product of the gains of the two stage preamplifiers.

The dynamic comparator is shown in Figure 9. Controlled by the clock signal CLK, the operation of the dynamic comparator is divided into a reset and comparison phase. When CLK is low, the comparator is in the reset state. M6 and M9 are turned on, pulling VOUTP and VOUTN up to VDDA. When M1 is off, there is no current path from the power supply to ground and this results in no power consumption. When CLK is high, the comparator is in the comparison state. M6 and M9 are turned off, and the currents in the M2 and M3 branches are determined by the input voltages VIP and VIN. When VIP is greater than VIN, the current in branch M2 exceeds that in branch M3. As a result, the source voltage of M4 drops faster than that of M5 and creates a voltage difference ΔV. This voltage difference is continuously amplified by the positive feedback formed by the cross-coupled inverters. When the VOUTN is eventually pulled to GNDA and VOUTP is pulled to VDDA, the comparison completes. When VIN is greater than VIP, the current in branch M3 exceeds that in M2. A voltage difference of -ΔV is formed between the source of M4 and M5. This voltage difference is continuously amplified by positive feedback. Finally, the VOUTN is pulled to GNDA and VOUTP is pulled to VDDA.

3. Post-Simulation Results

The proposed design is implemented using the SMIC 55 nm process. The layout of the TS-SS ADC is shown in Figure 10, with an overall area of 0.942 mm².

To eliminate the influence of non-ideal factors, an ideal DAC was connected to the output of the TS-SS ADC during simulation. The ideal DAC restores the quantized binary code of ADC to analog signals. Under the typical–typical (TT) process corner, with a full-scale input amplitude of 1.7 V, Fast Fourier Transforms (FFTs) are performed on the output of the proposed TS-SS ADC. The output spectrum is shown in Figure 11 and is based on 4096 sampling points. The results show that the proposed TS-SS ADC achieves an ENOB of 11.86 bits, an SNDR of 73.13 dB, and an SFDR of 97.45 dB with different input frequencies.

As shown in Figure 12, under the TT process corner and with an input frequency of 25 kHz, the performance at different input amplitudes was evaluated. The input amplitude started at 0 dBFS and decreased in steps of 10 dBFS. The results show that as the input amplitude decreases, the signal power Psignal also decreases, which leads to a reduction in both SNDR and SFDR. Since ENOB is proportional to SNDR, when SDNR decreases, ENOB decreases accordingly.

As shown in Figure 13, under the TT process corner and with a full-scale input amplitude of 1.7 V, the performance of the proposed TS-SS ADC at different input frequencies was evaluated. The results indicate that as the input signal frequency increases, the ENOB, SNDR, and SFDR show a general downward trend, and the decline is relatively small. The primary reason for this degradation is the limited bandwidth of operational amplifiers in the sample-and-hold circuit, ramp generators, and the comparator. As the input frequency increases, the gain of amplifiers decreases, which degrades signal settling accuracy and ultimately reduces SFDR. High-frequency signals exhibit rapid variations and sampling errors, and hold clamping errors are induced in the sample-and-hold circuit. These errors will cause deviation in the sampled value and a reduction in both SNDR and ENOB. The reason for small performance degradation is that the TS-SS ADC provides sufficient bandwidth to ensure adequate charge and discharge time even at higher input frequencies. Furthermore, a dynamic comparator with an adequate margin was adopted, which prevents erroneous comparisons even under faster input frequencies.

As shown in Figure 14, the performance under different process corners was evaluated, with an input amplitude of 1.7 V and a frequency of 25 kHz. The results indicate that under the FF process corner, the proposed TS-SS ADC exhibits lower ENOB, SNDR, and SFDR. This degradation is attributed to the reduced threshold voltage and increased carrier mobility of MOS transistors in the FF corner, which results in faster switching and a higher current, thereby intensifying kickback noise. Kickback noise interferes with the analog voltage held on the sampling capacitor, which may introduce errors and reduce SNDR and ENOB. Furthermore, kickback noise may cause nonlinear charge injection, which leads to increased higher-order harmonics and reduced SFDR.

The comparison results with others are shown in

Table 2. Performance comparison.

	[18]	[19]	[20]	[21]	[9]	[22]	This Work
Process (nm)	110	55	130	90	110	110	55
Supply voltage (V)	3.3/1.5	3.3	3.3/1.2	2.8/1.5	3.3/1.2	3.3/1.5	3.3
Structure	TS-SS	TS-SS	TS-SS	TS-SS	SAR-SS	SS	TS-SS
Transition time (μs)	2	0.512	10	39.7	-	34.2	10
Quantization range (V)	2	1.7	1.2	1	2	1	1.7–3
Resolution (bit)	10	13	12	12	12	10	13
ENOB (bit)	-	11.33	11.25	-	11.17	8.8	11.86
FoM (J/step)	-	9.35 f	296 f	-	-	4.3 p	59.7 p

. The proposed design achieves higher resolution, which enhances the system’s dynamic range and noise immunity. In addition, this design offers a wider quantization range and faster conversion speed, which can better meet the requirements of the front-end readout circuit for full well capacity and support high bandwidth, high dynamic range, and low latency signal processing. However, the use of a four-terminal comparator in this paper results in relatively high power consumption, which in turn leads to a Figure of Merit (FoM) significantly larger than other designs.

4. Conclusions

To ensure high performance of infrared image sensors, it is critical to develop high resolution and low power ADCs. Among various column-parallel ADC structures, the SS ADC has been widely adopted due to its simple structure, low power consumption, and small area. However, the conversion speed of the SS ADC is fundamentally limited by the exponential growth of clock cycles (2^N), which makes them unsuitable for high-frame-rate applications. The TS-SS ADC improves conversion speed by dividing the quantization process into coarse and fine phases. This structure reduces the scale of the capacitor array and switching energy to reduce both power consumption and area overhead. The TS-SS ADC demonstrates strong advantages in large-scale pixel arrays.

In this paper, a column-parallel TS-SS ADC was proposed for infrared image sensors with a frame rate of 100 Hz. This ADC was realized using the SMIC 55 nm process with a supply voltage of 3.3 V. The post-simulation results show that with a full-scale amplitude of 1.7 V, the proposed TS-SS ADC achieves an ENOB of 11.86-bit, an SNDR of 73.13 dB, and an SFDR of 97.45 dB at the Nyquist frequency. Although the proposed TS-SS ADC exhibits relatively high power consumption, it remains suitable for infrared imaging sensor systems that demand both high speed and high precision. Moreover, it provides a feasible solution for the future design of high-performance column-level ADCs.