A Low Power Low Inrush Current LDO with Different Techniques for PSR and Stability Improvement

Abstract

One of the most popular power management regulators is the low drop-out voltage regulator (LDO). LDOs have different specifications such as the power supply rejection (PSR) over different frequencies, stability over different load ranges, inrush current spike flows through the input supply, and power consumption. In this work, we present a low power low inrush current LDO design with different techniques for PSR and stability improvement across different frequencies. The LDO presented in this work is a low-power and small area LDO but achieves a high PSR over a wide range of frequencies. The LDO is designed in 65 nm CMOS technology and achieves a PSR better than 80 dB up to 30 MHz for an output load current of 25 mA using an output load capacitor of 4 µF. The design can be used in capless/capped LDOs with wide load current ranges as high as 200 mA and load capacitor range from 1 nF to 12 µF with inrush current improvement by more than 2×. The presented LDO consumes a zero-load quiescent current of 10 µA and its area of 180 µm × 180 µm.

1. Introduction

In the recent decade, the demand for regulator circuits that provide a regulated output voltage with low power consumption has highly increased. Different types of regulators are used for voltage regulation such as charge pumps (CP), switching regulators (SR), and low drop-out regulators (LDO). LDOs have the advantage of regulating the output with ripple-free output over the other regulator types due to having a non-switching mechanism. Also, the LDOs have the advantage of operating at a low drop-out voltage between the input supply and the output voltage.

Basically, system-on-chips (SOCs) use LDOs to provide a clean supply voltage to different analog–mixed signal blocks. Some blocks need a clean supply at low frequency ranges such as amplifiers and bandgaps. While other high-speed blocks need a clean supply at high frequencies such as oscillators and analog-to-digital converters (ADCs). Thus, a high PSR at the LDOs output over different frequencies is required to support low-frequency blocks such as amplifiers and bandgaps, and high-frequency blocks such as oscillators and ADCs.

In addition to PSR specification importance, the LDO loop stability under wide ranges of load currents and load capacitors is required to make the design suitable for different applications. Also, small area consumption is highly needed for SoC integration.

Another critical design consideration for high-performance regulators is to have a low quiescent current consumption so that it can achieve higher efficiency and suit different low-power applications. Previous works had to consume large power to improve either the PSR or the loop stability. Thus, innovative techniques with low power, widely stable, and high PSR are highly needed.

Figure 1 shows the conventional LDO transistor level diagram including the main pass transistor (MPT), (RFB1) and (RFB2) which are used as feedback resistor divider, the error amplifier, and a feedback capacitor (CFB) connected parallel to the upper resistor thus creating a high-frequency zero, which improves both the PSR and the stability of the LDO.

Basically, the LDO output has a high PSR at DC due to the high DC loop gain. However, at high frequencies and at heavy load currents, the PSR starts to degrade because the pass device’s (MPT) r_out starts to decrease, and hence, the LDO loop gain starts decreasing after the loop bandwidth which degrades the high-frequency PSR [1].

Recently, different techniques were proposed in the literature to improve the high-frequency PSR. A filter was used in the high-frequency PSR path to filter the high-frequency noise [2]. But this technique requires a large passive element with small PSR improvement. One of the other popular techniques is to use different types of feedforward ripples cancellation techniques by creating a direct path between the input supply noise and the pass device gate to couple the noise on it, which provides noise cancellation at the LDO output by subtracting the noise on the source and on the gate. One of those techniques was presented in [3]. The new technique improves the PSR at high frequencies up to 10 MHz but with limited small load current, complex loops, large area, and power consumption. Other techniques were presented after that with higher PSR values but with different limitations. Other technique was presented in [4,5]. They have small areas but with high power consumption and low load current capability. The works in [6,7] consume lower power but with large area consumption. An adaptive loop technique in [8] improved the power consumption with high load current capability but at the cost of a large area and large dropout voltage. Another adaptive design was presented in [9] with a smaller external load capacitance value but with higher power consumption. Recent work in [10] shows better PSR values with small dropout voltages but with the cost of complex design and high-power consumption. Another feedforward compensation technique is recently presented in [11]. It improves the PSR across a wide frequency range but with large power and area consumption. More recent work was presented in [12] that improves the PSR for smaller dropout voltage and external capacitor applications but at the cost of max load current capability limitations, quiescent current consumption, and large area consumption. Other works that focus on improving the PSR for cap-less LDOs have been conducted recently. The work completed in [13,14,15,16,17] improves the PSR with good area consumption and dropout voltage but at the cost of large power consumption and low load current capability. The work completed in [18] increases the current capability with a small area but with very large power consumption. The extended work of [18] is completed in [19] improving the no-load current consumption but with limited maximum load current and higher area. More recent works completed in [20,21] show moderate area and power consumption but with low load current and capacitance.

Our recently published works in [22,23] improve the high-frequency PSR and loop stability with a much smaller area and power consumption.

The newly proposed LDO design provides high PSR at high frequency while consuming a small area and low power. The proposed LDO improves the stability for both wide load currents and capacitor ranges while decreasing the inrush current through the pass device. The PSR improvement techniques are extracted and built on our previous works in [22,23] with different enhancements.

Section II will present the proposed design concept, analyses, and implementation followed by Section III which shows the post-layout simulation results followed up by Section IV which is the paper’s conclusion.

2. Design Concept and Implementation

The following equations present the loop analyses of the LDO design shown in Figure 1. The LDO output V_out shown in (3) is a function of two terms. The first term is due to the main feedback regulation loop as a function of V_ref as shown in (1), and the second term is due to the feedforward path through MPT as a function of Vin as shown in (2).

$$\begin{gathered} {\mathrm{V}}_{\mathrm{out}}/{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}} = \left[\left[{\mathrm{g}}_{\mathrm{m},\mathrm{N}\mathrm{d}1} \times {\mathrm{Z}}_{\mathrm{E}\mathrm{A}} \times {\mathrm{g}}_{\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}} \times {\mathrm{Z}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right]/\left[1 + \mathsf{\beta } \times {\mathrm{g}}_{\mathrm{m},\mathrm{N}\mathrm{d}1} \times {\mathrm{Z}}_{\mathrm{E}\mathrm{A}} \times {\mathrm{g}}_{\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}} \times {\mathrm{Z}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right]\right] = {\mathrm{A}}_{\mathrm{v}\mathrm{L}}/[1 + \mathsf{\beta } \times {\mathrm{A}}_{\mathrm{v}\mathrm{L}}] \\ =\frac{[\mathrm{g}\mathrm{m},\mathrm{N}\mathrm{d}1\times [\mathrm{r}\mathrm{o},\mathrm{E}\mathrm{A}/(1+\mathrm{S}\times \mathrm{r}\mathrm{o},\mathrm{E}\mathrm{A} \mathrm{\ast } \mathrm{C}\mathrm{o},\mathrm{E}\mathrm{A})]\times \mathrm{g}\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T} \mathrm{\ast } \mathrm{Z}\mathrm{o}\mathrm{u}\mathrm{t}]}{[1+[\mathrm{R}\mathrm{F}\mathrm{B}2/(\mathrm{R}\mathrm{F}\mathrm{B}1+\mathrm{R}\mathrm{F}\mathrm{B}2)]\times \mathrm{g}\mathrm{m},\mathrm{N}\mathrm{d}1\times [\mathrm{r}\mathrm{o},\mathrm{E}\mathrm{A}/(1+\mathrm{S}\times \mathrm{r}\mathrm{o},\mathrm{E}\mathrm{A}\times \mathrm{C}\mathrm{o},\mathrm{E}\mathrm{A}]\times \mathrm{g}\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}\times \mathrm{Z}\mathrm{o}\mathrm{u}\mathrm{t}]} \end{gathered}$$

(1)

$$\begin{gathered} {\mathrm{V}}_{\mathrm{out}}/{\mathrm{V}}_{\mathrm{d}\mathrm{d}} = \left[\left[{\mathrm{g}}_{\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}} \times {\mathrm{Z}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right]/\left[1 + \mathsf{\beta } \times {\mathrm{g}}_{\mathrm{m},\mathrm{N}\mathrm{d}1} \times {\mathrm{Z}}_{\mathrm{E}\mathrm{A}} \times {\mathrm{g}}_{\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}} \times {\mathrm{Z}}_{\mathrm{o}\mathrm{u}\mathrm{t}}\right]\right] = {\mathrm{A}}_{\mathrm{V}\mathrm{P}\mathrm{T}}/[1 + \mathsf{\beta } \times {\mathrm{A}}_{\mathrm{v}\mathrm{L}}] \\ \hspace{1em}\hspace{1em} =\frac{[\mathrm{g}\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T}\mathrm{\ast }\mathrm{Z}\mathrm{o}\mathrm{u}\mathrm{t}]}{[1+[\mathrm{g}\mathrm{m},\mathrm{N}\mathrm{d}1 \mathrm{\ast } \mathrm{r}\mathrm{o},\mathrm{E}\mathrm{A} \mathrm{\ast } \mathrm{g}\mathrm{m},\mathrm{M}\mathrm{P}\mathrm{T} \mathrm{\ast } \mathrm{Z}\mathrm{o}\mathrm{u}\mathrm{t} \mathrm{\ast } \mathrm{R}\mathrm{F}\mathrm{B}2]/[(\mathrm{R}\mathrm{F}\mathrm{B}1+\mathrm{R}\mathrm{F}\mathrm{B}2) \mathrm{\ast } (1+(\mathrm{s}/\mathsf{\omega }\mathrm{E}\mathrm{A}\left)\right)\left]\right]} \end{gathered}$$

(2)

V_out ≈ V_ref [A_VL/(1 + β × A_VL] + V_dd [A_VPT/(1 + β × A_VL]

(3)

A_VL = g_m,Nd1 × Z_EA × g_m,MPT × Z_out

(4)

A_VPT = g_m,MPT × Z_out

(5)

Z_out = r_out,MPT ⫽ R_L ⫽ (R_FB1 + R_FB2)

(6)

Z_EA = r_o,EA  ⫽ (1/SC_o,EA) = r_o,EA/(1 + S × r_o,EA × C_o,EA)

(7)

β = R_FB2/(R_FB1 + R_FB2)

(8)

where V_ref is the reference voltage generated from the bandgap, A_VL is the LDO’s loop gain, A_VPT is the pass transistor stage’s gain, Z_out is the overall output impedance of the LDO, Z_EA is the error amplifier’s total output impedance, g_m,MPT is the g_m of the pass device, g_m,Nd1 is the g_m of the error amplifier’s input pair, and C_o,EA is the total capacitance at the error amplifier output. The total capacitance includes drain capacitance at the input pair and load devices, as well as the effective gate capacitance of the pass device.

As shown in (1), at high frequencies (S = ∞) and due to the pole of the error amplifier, the TF goes to zero. Thus, the ripples through the error amplifier and bandgap do not appear at the output. While at a low frequency (S = 0), the PSR of the bandgap is amplified by the feedback ratio and affects the overall LDO output PSR. In (2), it is shown that at a low frequency (S = 0), the supply noise is not very effective because it is divided by the error amplifier gain multiplied by the feedback network factor. While at a high frequency (S = ∞), the supply noise is amplified by the pass device gain affecting the LDO PSR at high frequency. So, the low-frequency LDO PSR is dominated by the bandgap and error amplifier, while high-frequency LDO PSR is dominated by the supply noise through the pass device.

2.1. PSR Enhancement

From the loop analyses, the high-frequency PSR of the LDO is dominated by the pass device path. It can be increased by increasing r_out of the pass device because of the larger high-frequency loop gain and PSR. Also, the PSR can be improved by increasing the supply noise coupling to the pass transistor gate. This is because the more the supply noise coupling to the pass device gate, the higher the noise cancellation due to source–gate cancellation. The supply noise appearing at the source has a positive common gate gain. While the noise coupled to the gate has a negative common source gain. The two gains cancel each other providing a higher high-frequency PSR at the output.

Based on that, a design that combines two techniques of PSR improvement for conventional LDOs is presented. The first compensation technique is based on our work in [22], it works on coupling the noise to the pass device gate through a feedforward load-dependent compensation circuit as described in Section 2.1.1. The second technique of compensation is based on our work in [23], which enhances the r_out of the pass device (r_out,MPT) as described in Section 2.1.2.

2.1.1. Feedforward Compensation PSR Improvement

Figure 2 shows the compensation circuit added to provide a path for the supply noise to the pass device gate to have high-frequency noise coupling. It presents a modified circuit for the design proposed in [23]. Mainly it pushes current through the circuit depending on the load current that flows through the pass device, providing the load-dependent feedforward compensation.

For low loads, r_out,MPT of the pass device is large enough to provide a high PSR, while for a large load current, r_out,MPT of the pass device is small with low loop gain and PSR. As a result, the PSR improvement circuit is mainly needed at high loads. The proposed circuit works depending on the load current passing through the pass device. The gates of the devices MP3 and the pass device MPT are connected to have the same V_sg. The width of MP3 is much smaller. Therefore, MP3 will act as a current mirror for the load current. At zero load current, MP3 is off, disabling the proposed circuit and leading to a low quiescent current. At large loads, the circuit works by providing a path from the supply to the gate of the pass device through the device MP1 and the capacitor CP. This improves the PSR at large load currents.

The proposed feedforward compensation adds the device MP1 in parallel to MpL1, which is the error amplifier load device. This decreases r_o,EA, and hence the DC loop gain. Also, this affects the dc operating point of the main feedback loop. To avoid this issue, a capacitor CP is added to isolate the added feedforward circuit at DC as it behaves as an open circuit. While at a high frequency where the feedforward path is needed to improve the high-frequency PSR, CP becomes effective in connecting the path without affecting the DC operating point or the DC loop gain.

Also, the capacitor CC is added between MN1, the source of the device, which is a low impedance node, and the LDO output to generate a high frequency zero ω_z,cc. This zero improves the PSR at the MHz frequency range and improves the stability across different load currents. This is because g_m,MN1 also depend on the mirrored current by MP3. So, the zero location now depends on the LDO load current. The higher load current will lead to higher g_m,MN1, and hence better high-frequency PSR at ω_z,cc, where:

ω_z,cc ⍺ g_m,N1

(9)

The modification made to our work in [22] is removing three devices in the feedforward circuit that were used for biasing MP1, making use of the bandgap circuit that already generates Vref and Vnbias. The bias Vpbias for MP1 can be externally generated without these three devices. This decreases the circuit area and removes the power consumption through the removed branch at a large load current of 15 µA instead of 18 µA at 200 mA.

The LDO loop gain analyses with the feedforward loop are derived based on the LDO shown in Figure 2. As the load current increases, the feedforward loop gain A_vff increases due to higher g_m,MP1 as shown in (11). This helps in amplifying the supply noise on the gate of the pass device and improving the noise cancellation with a higher PSR at the high-frequency path. The LDO output shown in (3) becomes a function of the feedforward path gain through CP as Equation (10) shows.

V_Out ≈ V_ref ((A_VL)/(1 + β × A_VL)) + V_dd ((A_VPT (1 − A_Vff/Z_Cp))/(1 + β × A_VL))

(10)

A_Vff = g_m,P1 × (r_out,P1 ⫽ (g_m,N1 × r_out,N1 × r_out,N2))

(11)

Z_CP = 1/(S × C_P)

(12)

The output function of the LDO shown in (10) guarantees that the proposed loop improves PSR and the overall gain due to A_Vff term at high frequencies where Z_CP becomes effective. A_Vff is the feedforward loop gain, and Z_CP is the impedance of the capacitor CP.

2.1.2. Loop Gain Adjustment for PSR Improvement

The LDO’s loop gain increases with r_out,MPT as shown in (4)–(6). Increasing the length of the pass device MPT increases r_out,MPT and the high-frequency PSR. But this affects the DC loop operating point since it increases the voltage drop on the pass device which limits the DC load current that the LDO can support due to lower W/L of the pass device. A technique that increases ${\mathrm{r}}_{\mathrm{o}\mathrm{u}\mathrm{t},\mathrm{M}\mathrm{P}\mathrm{T}}$ at high frequency and hence the high-frequency PSR is shown in Figure 3.

Adding another series device (HPT) with the main pass device MPT increases the overall pass device length, which increases r_out,MPT and improves the high-frequency PSR. The gate of the device HPT is connected to the error amplifier output through the capacitor CHF, which acts as a short circuit at high frequencies to provide a larger length to the pass device due to two cascode devices, MPT and HPT. This improves the high-frequency loop gain and PSR. CHF is an open circuit at DC isolating the added device HPT from the main loop by pulling the gate of HPT to the ground through an off-transistor MRHF that acts as a large resistor. This makes HPT act as a short circuit at DC. Thus, the main device MPT will only work by providing sufficient dropout for the large load current. The analyses of the proposed circuit show that Z_out keeps the same at DC but increases at high frequency due to the cascode to be:

Z_out.HF = g_m,MPT × r_out,MPT × r_out,HPT ⫽ R_L ⫽ (R_FB1 + R_FB2)

(13)

The modification completed on our work in [23] is to replace a very large resistor RHF with a small off-transistor MRHF to act as a large resistor to pull down HPT’s gate to ground at DC but with much smaller area consumption.

2.2. Inrush Current Improvement

A common issue for capped LDO is the inrush current that can cause electromigration and IR-drop “EMIR” issues. At large load capacitor values, V_out is charged by “dV_out” within time “dT_ch” according to (14) where:

C_Load × dV_out = I_Load × dT_ch

(14)

For large C_Load, the slow charging time of V_out makes V_fb, which is the positive input of the error amplifier rise slower than V_ref, which is the negative input making the amplifier output “pass transistor gate” low. This increases V_sg on the pass transistor for an interval until V_fb comes up closer to V_ref and the loop works normally. Having a large W/L pass device due to large load currents with such very large V_sg during start-up provides a large inrush current.

An effective solution is to split the main pass device MPT into two parallel devices as shown in Figure 4, which shows the final proposed LDO design. The first is an always enabled small one (MPTS) “small W/L”, and the second is a larger one (MPTL) that is enabled after the RC filter (RF and CF) delay is larger than the inrush current interval. This limits the inrush current due to enabling the smaller pass device at start-up then enabling MPTL after the RC delay makes the loop operate normally with the whole pass device size to support the whole load current. The added RC pole does not affect the stability as it is at a much higher frequency.

2.3. Techniques for Stability Compensation

The newly proposed LDO is stable for a wide range of load currents up to 200 mA and a capacitor range from 1 nF to 12 µF. The device HPT improves the stability as it increases Z_out at high frequencies as shown in (13) by decreasing the dominant pole at the LDO output. The newly proposed LDO shows higher phase margin values compared to the work completed in [22] which includes a similar idea of the feedforward loop, with smaller compensation devices CP and CC, which decreases the area.

At different load currents, the poles ω_pout and ω_pEA will change their locations as both are functions of load currents. The zero ω_z,cc will change its location depending on the output load current according to (9) and follows the non-dominant pole change. This provides compensation to keep the system stable for a load current range from 0 to 200 mA.

3. Simulation Results

The layout of the newly proposed LDO is shown in Figure 5. The silicon area consumption is 180 µm × 180 µm. The RCC post-layout view of the LDO is verified with different load capacitors and different load currents with a bandgap that generates the reference and the bias voltages V_ref, V_nbias, and V_pbias. Electric series inductance “ESL” and electric series resistance “ESR” are added at different load capacitors based on the capacitor value. At 3 V supply, 4 µF load capacitor, and 25 mA load current, transient results are presented in Figure 6. The supply ramps to 3 V while V_ref ramps to 1.2 V. The LDO output ramps and settles as expected at 1.8 V.

3.1. PSR Simulations

The high-frequency improvement in PSR is presented in Figure 7 after each stage of compensation. PSR at the DC of the LDO is not affected by the two proposed high-frequency PSR compensation techniques—the same for the DC operating point and the loop DC gain.

Figure 7 shows the PSR improvement at 100 kHz, 1 MHz, 10 MHz, and 30 MHz of each stage of compensation. The numbers are shown in

Table 1. Comparison between PSR at different frequencies.

Frequency	Conventional LDO	After Adding 1st Compensation	After Adding 2nd Compensation
100 kHz	−65 dB	−76 dB	−78 dB
1 MHz	−40 dB	−78 dB	−82 dB
10 MHz	−32 dB	−72 dB	−83 dB
30 MHz	−30 dB	−70 dB	−83 dB

.

3.2. Stability Measurements

Figure 8 presents the phase margin using different load capacitor values from 1 nF to 12 µF with their corresponding ESR and ESL models with load current ranging from 0 to 200 mA, all across process, voltage, and temperature conveniently called “PVT”. Where VDD is in the range of 2 V to 3 V, fast NMOS and PMOS and slow NMOS and PMOS for process corners, a low temperature of −40 °C and 125 °C for maximum temperature, it shows a worst phase margin of 51 degrees.

3.3. Inrush Current Improvement

Ramping the LDO supply from 0 to 3 V in 30 µs shows inrush current improvement by more than 2× from 120 mA to 58 mA using the proposed design as shown in Figure 9.

Table 2. Comparison between the proposed LDO and the previously published LDOs.

	[3]	[4]	[6]	[5]	[7]	[22]	[23]	This Work
Year	2010	2014	2015	2018	2020	2021	2021	2023
Technology (nm)	130	65	180	65	180	65	65	65
Active Area (mm2)	0.049	0.036	0.21	0.048	0.12	0.036	0.08	0.0324
Input Voltage (V)	>1.15	1.15–1.3	1.3	1.2	5	>2	2.7–3.3	>2
Output Voltage (V)	1	1	1.2	1	4.5	1.8	1.8	1.8
Maximum iLoad (mA)	25	25	25	100	250	200	100	200
Output Capacitor (µF)	4	4–4.7	4.7	4.7	1–12	0.001–12	1–12	0.001–12
Quiescent current (µA)	40	150–350	10	40	5.6–35.6	10–18	5	10–15
PSRR (Power Supply Rejection Ratio) (dB)	@4 µF,	@4 µF,	@4.7 µF,	@4.7 µF,	@2.2 µF,	@4 µF,	@4 µF,	@4 µF,
	@25 mA	@25 mA	@25 mA	@100 mA	@20 mA	@25 mA	@25 mA	@25 mA
	−60	−65	−71	−89	−77	−80	−77	−78
	@100 k	@100 k	@100 k	@100 k	@100 k	@100 k	@100 k	@100 k
	−67	−61	−69	−70	−72	−83	−85@	−82
	@1 M	@1 M	@1 M	@1 M	@1 M	@1 M	1 M	@1 M
	−56	−47	−63	−62	−62	−82	−80@	−83
	@10 M	@10 M	@10 M	@10 M	@10 M	@10 M	10 M	@10 M
FOM@100 KHz	22.8	18.76	22.55	29.94	30.18	31.43	30.8	31.77
FOM@1 Mz	23.3	18.45	22.425	28.9	29.89	31.69	31.23	31.99
FOM@10 MHz	22.52	17.36	22.03	28.37	29.24	31.53	30.97	32

compares between this work and previous works, using a figure of merit (FOM) for an overall comparison as shown in (15). The newly proposed LDO has the best FOM across different high frequencies.

FOM = 10 × log((|PSR| × I_Load@psr))/(I_q × C_L@psr) × Area))

(15)

PSR is in dB, i_Load is in mA, I_q in µA, C_L in µF, and the area is in mm².

4. Conclusions

In this work, we presented an innovative LDO design that includes two compensation techniques to be utilized in LDOs that improve its high-frequency PSR and loop stability without adding a complex loop that degrades the power and the area consumption. The two techniques improve the design PSR by providing a load-dependent feedforward noise path to the pass device gate and adjusting the loop gain at different frequencies. In addition, it guarantees loop stability over a wide load current range from 0 to 200 mA and a wide load capacitor range from 1 nF to 12 µF. The design provides a big improvement in the LDO output PSR by up to −50 dB at 10 MHz and −53 dB at 30 MHz. Also, it shows a technique that improves the LDO inrush current during startup by more than 2X with much smaller power and area compared to previous works in the literature.