Multilevel Inverter Fault Diagnosis Using Differentiable Architecture Search for Edge Deployment

Abstract

With the increasing penetration of renewable energy systems, multilevel inverters have been widely adopted to meet the growing demand for high-power and high-quality energy conversion. Among various multilevel topologies, cascaded H-bridge multilevel inverters (CHMIs) are particularly attractive due to their modular structure and improved output voltage quality. However, the increased number of power semiconductor devices and switching states significantly complicates fault diagnosis under practical operating conditions. Currently, most existing neural networks for fault diagnosis are manually designed based on domain expertise. This may limit their adaptability to task-specific fault patterns as well as edge-side inference performance. To reduce the dependence on manually designed diagnostic networks, an edge-oriented fault diagnosis framework based on differentiable architecture search (DARTS) is proposed to automatically design task-specific diagnostic networks. A simplified special cell search strategy is adopted to improve search efficiency and facilitate practical deployment. The searched architectures are lightweight and suitable for deployment on edge platforms. The experiments show that the proposed method achieves an average diagnostic accuracy of 99.44% on the test set under the RL load of $(7\mathrm{\Omega },6\mathrm{mH})$. Furthermore, the searched model contains only 0.2417 M trainable parameters, and edge deployment experiments on the Jetson Orin Nano platform show low-latency inference capability.

1. Introduction

As critical components for DC-AC power conversion, inverters serve as the technological cornerstone, enabling precise control and the efficient energy conversion in modern power systems. The cascaded H-bridge multilevel inverter (CHMI), recognized as a high-performance multilevel converter, offers several advantages including good harmonic characteristics, reduced dv/dt, enhanced modularity and high efficiency [1,2]. Consequently, the CHMI has been widely adopted in critical domains, including renewable energy generation systems, electric drive applications, and charging stations [3,4,5]. Compared to two-level inverters, the CHMI has more power semiconductor devices, posing a challenge to its reliable operation. The research effort presented in this work aims to apply automated machine learning techniques to learn circuit behavior and fault characteristics, thereby improving and accelerating inverter fault diagnosis.

Within inverter systems, insulated gate bipolar transistors (IGBTs) are widely employed due to their favorable electrical characteristics [4]. However, silicon-based semiconductor materials have inherent physical limitations, and achieving nanosecond-level switching precision requires complex control strategies. These factors make IGBT modules particularly susceptible to various failure mechanisms [5,6]. Although the modular structure of the CHMI facilitates extension to higher output voltage levels, the probability of inverter failure increases significantly as the number of inverter levels rises [7]. Two common types of IGBT failures are short-circuit faults (SCFs) and open-circuit faults (OCFs). SCFs can induce severe current distortion and transient thermal effects within an extremely short time (<10 $\mathsf{\mu }\mathrm{s}$) and have been effectively addressed through mature hardware protection mechanisms [8,9]. In practical applications, protection circuits are typically integrated into IGBT driver modules to convert SCFs into OCFs [10,11]. In contrast, OCFs manifest as distorted currents and voltages, which can severely affect system operation and may further damage the remaining devices. In CHMI systems, the integration of multiple power modules introduces additional challenges for accurate and rapid OCF diagnosis compared with conventional two-level inverters. Therefore, developing robust fault diagnosis strategies specifically targeting OCFs is essential for reliable localization and identification [12].

Previous diagnosis strategies for inverter OCFs can be broadly categorized into model-based methods and data-driven methods [13]. Model-based fault diagnosis methods have been extensively studied over the past decades and constitute a well-established research paradigm. Model-based methods are centered around constructing precise mathematical models and formulating explicit numerical expressions for complex systems [14]. For instance, a mixed logical dynamic (MLD) model is proposed for diagnosing IGBT OCFs in a single-phase three-level neutral-point-clamped (NPC) inverter, where fault conditions are inferred through logical constraints embedded in the system model [15]. Another representative line of research employs sliding mode observers to monitor circuit operating states, in which OCF occurrence is detected when the estimated circulating current exhibits a significant deviation from the measured current [16]. Model-based fault diagnosis methods are characterized by high diagnostic speed and clear physical interpretability. However, their performance is usually sensitive to model-parameter accuracy and threshold selection. As power electronic systems become more complex, constructing accurate models and implementing reliable diagnostic logic become increasingly difficult, which may limit the applicability of traditional model-based methods [17].

Driven by the rapid development of industrial digitalization and the exponential growth of hardware computing power, data-driven fault diagnosis methods have attracted significant research attention. These approaches analyze the relationship between measured voltage and current signals and inverter operating states. By establishing correlations between operational data and fault conditions through systematic data analysis, data-driven methods enable effective fault detection and localization. In power converter fault diagnosis, shallow machine-learning methods based on feature engineering are often combined with signal processing techniques. Moradzadeh et al. [18] reviewed the application of data-driven methods in fault diagnosis of power electronics systems and evaluated some data mining techniques. Wang et al. [19] performed CHMI fault diagnosis using only phase-voltage signals. In their approach, the Fast Fourier Transform (FFT) was employed for feature extraction, followed by Relative Principal Component Analysis (RPCA) to reduce the dimensionality of the feature space. Gomathy et al. [20] applied Discrete Wavelet Transform (DWT) and Principal Component Analysis (PCA) to extract fault-related features from current signals. However, these methods are typically designed for specific converter topologies and heavily rely on manually engineered feature extraction procedures. Moreover, their diagnostic performance strongly depends on the selection of fault-sensitive signals, feature extraction strategies, dimensionality reduction methods, and classifier parameters. Feature engineering, which includes data preprocessing, feature extraction, and feature selection, remains a classic procedure that has achieved remarkable results [21]. Deep learning methods integrate these stages into a unified framework that can be jointly optimized to maximize classification performance, thereby demonstrating powerful feature learning capabilities. Kiranyaz et al. [22] proposed a real-time diagnostic framework for OCFs in power-switching devices using one-dimensional convolutional neural networks (1D-CNNs). Xing et al. [23] achieved high efficiency and robustness using a deep residual filter network. However, the feature extraction capability of CNNs may be limited when using 1D feature representations. To better exploit the representation ability of CNNs, Wang et al. [24] proposed a method that transformed three-phase current signals into input feature maps, achieving improved fault diagnosis accuracy compared to prior studies. Wen et al. [25] attempted to use a special method to convert raw signal data into two-dimensional (2D) images and achieved high diagnostic accuracy using 2D-CNNs. Deng et al. [26] proposed a diagnostic strategy based on sliding-time window to construct concise feature samples for modular multilevel converters (MMCs) in both time and frequency domains. Nevertheless, most existing deep learning-based methods still rely on manually designed network architectures, which heavily depend on expert experience and tedious trial-and-error tuning. This inevitably limits their adaptability to diverse fault patterns and practical deployment constraints.

For CHMI OCF diagnosis, the above limitation becomes more critical when highly similar fault modes are considered. In such cases, different fault modes may exhibit nearly identical global voltage waveforms, while the discriminative information is mainly reflected in weak and localized voltage signal distortions. Consequently, handcrafted time-domain, frequency-domain, or statistical features may be insufficient to stably capture these fine-grained local differences. To enhance feature discriminability, Liu et al. [27] proposed a PCA-based principal component rearrangement (PCR) method. However, such PCA/PCR-based methods still rely on domain expertise for feature selection, component retention, and parameter tuning, which may limit their adaptability to diverse operating conditions and highly similar fault patterns. Some active diagnosis strategies improve the separability of similar fault modes by adjusting modulation schemes or operating states after fault detection [28]. Although such methods enhance fault distinguishability, they introduce additional control complexity and degrade waveform quality, e.g., increasing total harmonic distortion (THD). Therefore, a diagnostic method that automatically extracts discriminative local fault features, reducing reliance on manual feature engineering design and expert intervention, while preserving the original modulation scheme is highly desirable.

Although deep learning methods have significantly improved diagnostic accuracy, their practical deployment in resource-constrained industrial environments remains challenging. In many existing studies, the proposed models are mainly evaluated through PC-based simulations or laboratory validations, which often lead to computationally intensive network architectures that are difficult to deploy in practical applications. Specialized AI hardware platforms, such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), typically feature a relatively closed and less mature software ecosystem and also require specialized hardware design expertise [29]. In contrast, edge computing platforms, such as the NVIDIA Jetson Orin Nano, provide a flexible and developer-friendly software ecosystem. It is compatible with mainstream deep learning frameworks and inference acceleration libraries [30]. This allows researchers to focus on algorithm development while benefiting from low deployment cost, simplified implementation, and shortened development cycles [31,32]. Furthermore, the NVIDIA Jetson platform provides a mature workflow for model compression and optimization, facilitating the efficient deployment of lightweight fault diagnosis models. However, most existing deep-learning-based fault diagnosis models still rely on manually designed network architectures, where key structural choices, such as convolutional operations, network depth, channel width, and downsampling strategy, are usually determined by expert experience and iterative hyperparameter tuning. Such a manual design process may lead to suboptimal architectures for specific diagnostic tasks, especially when the discriminative fault information is weak and locally distributed. For CHMI fault diagnosis, inappropriate architecture design may either weaken fine-grained voltage distortions or introduce unnecessary computational overhead, which is unfavorable for edge deployment. This practical limitation motivates the use of neural architecture search (NAS). Liu et al. [33] proposed a differentiable architecture search (DARTS), which relaxes the discrete architecture selection problem into a continuous optimization problem and enables gradient-based architecture optimization. Compared with reinforcement-learning-based and evolutionary-based NAS methods [34,35], DARTS substantially reduces computational costs while maintaining competitive search performance. For fault diagnosis tasks, this capability is particularly valuable, as it enables the automatic discovery of network architectures adapted to task-specific fault patterns without extensive manual intervention.

In this paper, a data-driven OCF diagnosis method for CHMI based on differentiable architecture search is proposed. The proposed framework automatically derives task-specific lightweight neural architectures for accurate inverter fault diagnosis while facilitating efficient deployment on edge platforms. The main contributions of this paper are summarized as follows:

(1)

An edge-oriented intelligent fault diagnosis method for CHMI is proposed. The method leverages DARTS to automatically derive task-specific diagnostic models, thereby reducing reliance on manual network design and handcrafted feature engineering.

(2)

A differentiable special cell search strategy is proposed to improve search efficiency and enable lightweight architecture design suitable for practical deployment.

(3)

A practical model deployment and inference optimization scheme is established by integrating the searched model with TensorRT, enabling efficient inference on resource-constrained edge devices.

The remainder of this paper is organized as follows. Section 2 analyzes the CHMI fault mechanism and clarifies the challenges of diagnosing similar fault modes. Section 3 presents the proposed fault diagnosis method. Section 4 provides experimental validation and performance evaluation under different operating conditions, including edge deployment experiments. Finally, Section 5 provides a discussion of the experimental results and limitations of the proposed method, while Section 6 concludes this paper and discusses future research directions.

2. Fault Mechanism Analysis and Problem Description

This section analyzes the basic circuit topology of CHMI, followed by an investigation of its fault mechanisms and the associated diagnostic challenges posed by highly similar fault modes. These observations motivate the edge-oriented fault diagnosis method proposed in this paper.

2.1. Basic Circuit Topology of CHMI

The basic topology of the CHMI is illustrated in Figure 1, which is composed of m identical H-bridge submodules. Here, ${\mathrm{H}}_m{\mathrm{S}}_n$ denotes the nth switch of the mth H-bridge submodule, and the voltage of each DC source is denoted as $V_{dc}$. The output AC voltage and current are represented by $u\left(t\right)$ and $i\left(t\right)$, respectively. Each H-bridge submodule consists of four IGBTs, each equipped with an anti-parallel diode. In inverter systems supplying inductive loads, the inductive current cannot undergo abrupt transitions due to its inherent characteristic. When an IGBT experiences an OCF, its controlled conduction channel is interrupted. Owing to load inductance, the current commutates to an available freewheeling paths formed by anti-parallel diode or other conducting devices, which is determined by the instantaneous current direction and switching state.

2.2. Open-Circuit Fault Mechanism Analysis of CHMI

This section considers a single-phase cascaded H-bridge five-level inverter with two submodules (m = 2) as an example to analyze the switching characteristics and OCF mechanisms. The single-phase CHMI system comprises eight IGBTs, denoted as ${\mathrm{H}}_1{\mathrm{S}}_1$ to ${\mathrm{H}}_2{\mathrm{S}}_4$, arranged in two H-bridge submodules. The inverter output voltage signal $u\left(t\right)$ is selected as the signal for fault diagnosis, which helps mitigate the influence of noise and load variations on the diagnostic process [36,37]. The inverter is modulated using the phase-disposition (PD) strategy of level-shifted pulse width modulation (LS-PWM), in which all carrier signals are in phase and vertically shifted to cover the entire modulation range [38]. The shifted carriers are compared with the modulating sinusoidal signal, resulting in the generation of IGBT gating signals. The fault modes are classified into nine classes, including one normal operating condition and eight single IGBT OCF cases. These fault modes produce distinct distortion patterns in the output voltage waveform, which form the basis for subsequent fault diagnosis.

The control signals of ${\mathrm{H}}_1{\mathrm{S}}_1$∼${\mathrm{H}}_2{\mathrm{S}}_4$ are defined as $s_1$∼$s_8$. To prevent the shoot-through phenomenon in bridge legs and subsequent DC-link short-circuit hazards, gate signals must be applied to the two IGBTs on the same leg, ensuring only one switch conducts at any instant. According to the duality principle, the analysis of the control signal states can be simplified. The single-switch OCFs of IGBTs at different positions in submodule 1, along with the corresponding output voltages under different current directions, are listed in

Table 1. Output voltage of submodule 1 under OCF at different fault locations.

Current Direction	Control Signal	Fault Location
		${\mathbf{H}}_{\mathbf{1}}{\mathbf{S}}_{\mathbf{1}}$	${\mathbf{H}}_{\mathbf{1}}{\mathbf{S}}_{\mathbf{2}}$	${\mathbf{H}}_{\mathbf{1}}{\mathbf{S}}_{\mathbf{3}}$	${\mathbf{H}}_{\mathbf{1}}{\mathbf{S}}_{\mathbf{4}}$
$i\left(t\right)>0$	$[1,0,1,0]$	0	$V_{dc}$	0	$V_{dc}$
$i\left(t\right)>0$	$[0,1,1,0]$	0	0	0	0
$i\left(t\right)<0$	$[1,0,1,0]$	$V_{dc}$	$V_{dc}$	$V_{dc}$	$V_{dc}$
$i\left(t\right)<0$	$[0,1,1,0]$	0	0	0	0

. Consider the case where the output current is positive ($i\left(t\right)>0$) and the control signal is $[0,1,1,0]$ as an example. Under normal operation (Figure 2a), the current flows through ${\mathrm{H}}_1{\mathrm{S}}_2$ and ${\mathrm{H}}_1{\mathrm{S}}_3$, resulting in a zero output voltage state. When an OCF occurs in ${\mathrm{H}}_1{\mathrm{S}}_3$, the current path would theoretically shift to ${\mathrm{H}}_1{\mathrm{S}}_2$ and the anti-parallel diode of ${\mathrm{H}}_1{\mathrm{S}}_4$ (Figure 2b), producing $-V_{dc}$ output if the diode conducts. However, reverse current conduction requires sufficient reverse voltage to forward-bias the diode [28]. Due to the carrier constraints inherent in LS-PWM, the absence of such voltage interrupts the current path in this operating mode, thereby forcing the output to remain in the zero voltage state.

As shown in Table 1, when ${\mathrm{H}}_1{\mathrm{S}}_1$ is faulty, the output voltage sequence becomes $(0,0,V_{dc},0)$. Similarly, when ${\mathrm{H}}_1{\mathrm{S}}_3$ is faulty, the same voltage sequence is obtained. Likewise, faults in ${\mathrm{H}}_1{\mathrm{S}}_2$ and ${\mathrm{H}}_1{\mathrm{S}}_4$ produce an identical output voltage pattern. The above analysis indicates that the two diagonally located IGBTs in the first H-bridge submodule generate nearly identical output voltage waveforms under individual OCF. These fault cases exhibit nearly indistinguishable output voltage waveforms, with the only difference being minor voltage spikes [39]. Accordingly, the diagonally located switch pairs, namely ${\mathrm{H}}_1{\mathrm{S}}_1$–${\mathrm{H}}_1{\mathrm{S}}_3$ and ${\mathrm{H}}_1{\mathrm{S}}_2$–${\mathrm{H}}_1{\mathrm{S}}_4$, constitute two pairs of similar faults. Such similarity among fault cases significantly increases the difficulty of accurate fault diagnosis.

2.3. Problem Description for CHMI

In CHMI, OCFs occurring at different switch locations may produce highly similar output voltage waveforms. In particular, when diagonally located IGBTs develop OCFs, the resulting output voltage waveforms are nearly identical. The only observable differences appear as minute voltage spikes caused by the non-ideal switching behavior of the IGBTs and the inductive discharge of the load [40]. Since the magnitude of these voltage spikes is significantly smaller than the amplitude of the output voltage, distinguishing such similar fault cases is particularly challenging.

Conventional fault diagnosis methods often struggle to distinguish fault modes with high visual and statistical similarity, resulting in limited diagnostic accuracy. Deep learning methods offer a promising alternative by automatically learning discriminative features directly from raw sensor data [41]. However, in existing studies, most efforts rely on expert-designed neural architectures, with hyperparameter optimization techniques employed to improve diagnostic performance [42,43,44]. Such approaches rely heavily on manual architecture design, which may limit the achievable diagnostic performance. An appropriate neural architecture serves as the essential foundation for effective hyperparameter optimization.

3. Proposed CHMI Fault Diagnosis Method

This section proposes an edge-oriented fault diagnosis method for CHMI based on differentiable architecture search (DARTS), which automatically derives task-specific neural architectures for accurate fault diagnosis.

3.1. Differentiable Architecture Search with Special Cell Strategy

Neural architecture search (NAS) aims to automatically discover optimal neural architectures within a predefined search space, reducing reliance on manual architecture design. This capability is particularly beneficial for CHMI fault diagnosis, where subtle waveform differences require task-specific feature extraction structures. The architecture search process typically consists of three main components: search space definition, candidate architecture training, and performance evaluation. During the search process, multiple candidate architectures are iteratively trained and evaluated, and the architecture with the best validation performance is selected as the optimal neural architecture. Differentiable architecture search (DARTS) is a representative NAS algorithm that relaxes the discrete architecture search space into a continuous one, enabling efficient gradient-based optimization [33].

Following the standard DARTS formulation, each cell is represented as a directed acyclic graph (DAG) composed of an ordered set of nodes. The cell contains several intermediate nodes and one output node, where each node corresponds to a latent feature representation. The output node aggregates the feature maps from all intermediate nodes to generate the cell output. The information propagated from node i to node j is modeled as a weighted combination of candidate operations in the search space. Accordingly, The output of node j is obtained by aggregating all incoming feature flows from its preceding nodes, which can be expressed as:

$$x_j=\sum _{i<j}{f}_{i,j}\left(x_i\right)$$

(1)

where $x_i$ denotes the output of the node i intermediate node and $f_{i,j}\left(x_i\right)$ represents the mapping from node i to node j. To enable differentiable architecture search, the categorical selection of candidate operations is relaxed into a continuous mixture using softmax-weights, which is formulated as:

$$f_{i,j}\left(x_i\right)=\sum _{o\in \mathcal{O}}{\displaystyle \frac{exp\left({\alpha }_{i,j}^o\right)}{{\sum }_{o^{\prime }\in \mathcal{O}}exp\left({\alpha }_{i,j}^{o^{\prime }}\right)}}o\left(x_i\right)$$

(2)

where ${\alpha }_{i,j}^o$ denotes the architecture parameter associated with operation $o\in \mathcal{O}$ on edge $(i,j)$, and $\mathcal{O}$ denotes the set of all candidate operations in the search space. This continuous relaxation renders the architecture parameters differentiable, thereby enabling efficient optimization via gradient-based methods.

Based on the above formulation, the architecture search is formulated as a bilevel optimization problem following the DARTS framework. Specifically, the network weights $\omega$ and architecture parameters $\alpha$ are optimized on the training and validation sets, respectively, to obtain an architecture with good generalization ability:

$$\begin{array}{c}\hfill \underset{\alpha }{min}{\mathcal{L}}_{val}({\omega }^{*}\left(\alpha \right),\alpha )\\ \hfill \mathrm{s}.\mathrm{t}.{\omega }^{*}\left(\alpha \right)=arg\underset{\omega }{min}{\mathcal{L}}_{train}(\omega ,\alpha )\end{array}$$

(3)

where ${\omega }^{*}\left(\alpha \right)$ denotes the optimal network weights obtained under architecture parameters $\alpha$, while ${\mathcal{L}}_{train}$ and ${\mathcal{L}}_{val}$ represent the loss functions evaluated on the training and validation sets, respectively. This bilevel formulation enables joint optimization of network weights and architecture parameters via alternating gradient-based updates. In this work, the cross-entropy loss is adopted as the optimization objective.

To reduce the computational cost of solving the bilevel optimization problem in (3), a efficient first-order approximation is adopted to estimate the gradient of the validation loss with respect to the architecture parameters:

$${\nabla }_{\alpha }{\mathcal{L}}_{val}({\omega }^{*}\left(\alpha \right),\alpha )\approx {\nabla }_{\alpha }{\mathcal{L}}_{val}(\omega -\xi {\nabla }_{\omega }{\mathcal{L}}_{train}(\omega ,\alpha ),\alpha )$$

(4)

where $\xi$ denotes the learning rate for one step of inner optimization.

Standard DARTS may suffer from unstable architecture selection due to strong coupling introduced by full-channel continuous relaxation, where parameter-free operations tend to dominate the search process [45]. To alleviate this issue, PC-DARTS introduces partial channel connections, in which only a subset of feature channels participates in the mixed operation:

$$f_{i,j}^{\mathrm{PC}}(x_i;S_{i,j})=\sum _{o\in \mathcal{O}}{\displaystyle \frac{exp\left({\alpha }_{i,j}^o\right)}{{\sum }_{o^{\prime }\in \mathcal{O}}exp\left({\alpha }_{i,j}^{o^{\prime }}\right)}}o(S_{i,j}\ast x_i)+(1-S_{i,j})\ast x_i$$

(5)

where $S_{i,j}\ast x_i$ denotes the selected channel features and $(1-S_{i,j})\ast x_i$ represents the remaining channels that bypass the mixed operation. The partial channel connection strategy reduces the memory overhead by a factor of K, enabling more efficient architecture search. However, stochastic channel sampling may introduce instability during the selection of optimal edge operations. To mitigate this issue, edge normalization is introduced to balance the contributions of different edges and stabilize the architecture optimization process. The normalized aggregation is formulated as:

$$x_j^{\mathrm{PC}}=\sum _{i<j}{\displaystyle \frac{exp\left({\beta }_{i,j}\right)}{{\sum }_{i^{\prime }<j}exp\left({\beta }_{i^{\prime },j}\right)}}{f}_{i,j}^{\mathrm{PC}}(x_i;S_{i,j})$$

(6)

where ${\beta }_{i,j}$ denotes the learnable normalization weight associated with edge $(i,j)$. The softmax-normalized edge weights mitigate the instability caused by stochastic channel sampling.

In this work, PC-DARTS is adopted as the underlying architecture search method. Based on this method, a simplified search strategy, termed PC-DARTS-SC (PC-DARTS with a special cell search strategy), is proposed for CHMI fault diagnosis. Unlike standard PC-DARTS, which typically incorporates both normal cells and reduction cells, the proposed strategy restricts the search space to architectures composed exclusively of special cells. This design is motivated by the relatively small input size and the need to preserve subtle waveform variations in inverter voltage signals, which are critical for distinguishing similar fault modes. The architecture search is conducted over a task-specific module referred to as the special cell. The special cell serves as the basic building block of the searched architecture, and all cells share the same architecture. By stacking multiple such special cells, the network progressively extracts hierarchical fault-related features from inverter voltage signals. This design avoids downsampling operations that may corrupt subtle waveform information.

3.2. Signal Reshaping Strategy and Search Space Design

As analyzed in Section 2, diagonally located IGBT OCFs within an H-bridge produce highly similar output voltage waveforms, where the waveform discrepancies mainly manifested as minor voltage spikes. This makes accurate fault diagnosis challenging. To better adapt the searched architecture to the voltage of the inverter, a signal reshaping strategy is proposed. As illustrated in Figure 3, each measured voltage cycle signal is reshaped into a 2D feature map, which facilitates convolutional feature extraction for effective fault diagnosis. Here, $L\left[i\right]$ denotes the value of the i-th voltage sampling point, while $S_d$ and $H_d$ represent the width and height of the constructed matrix, respectively.

For inverter output voltage signals, the discriminative information associated with similar OCF modes is mainly concentrated around the load current zero-crossing instants. These subtle waveform discrepancies span different temporal scales. To capture such localized yet multi-scale waveform variations, the search space $\mathcal{O}$ is designed to include operations with different receptive fields. Specifically, the search space includes the following candidate operations: $3\times 3$, $5\times 5$, and $7\times 7$ depthwise separable convolutions; $3\times 3$, $5\times 5$, and $7\times 7$ dilated separable convolutions; $3\times 3$ max pooling; $3\times 3$ average pooling; identity; and zero. All operations are applied with a stride of one, and appropriate padding is used to preserve the spatial resolution of the feature maps. The inclusion of larger kernel sizes and dilated convolutions enables multi-scale feature extraction. This design allows the searched architecture to capture subtle voltage variations distributed over different temporal scales, which is critical for distinguishing similar faults.

3.3. Network Construction Based on Stacked Special Cells

After the architecture search, the super-network is discretized into a final sub-network by selecting the two candidate operations with the highest architecture parameters ${\alpha }_{i,j}$ for each intermediate node. The derived cells are stacked with a predefined depth to form the feature extraction backbone. Specifically, a four-layer special cell stack is employed to balance diagnostic performance and computational efficiency. As illustrated in Figure 4, the stacked special cells form the feature extraction backbone, followed by a lightweight classifier consisting of a global average pooling (GAP) layer and a fully connected layer with Softmax activation. Compared with conventional fully connected classifiers, the GAP layer reduces model complexity and mitigates overfitting [9,46], which is beneficial for fault diagnosis with limited training data.

4. Experimental Verification and Analysis

This section presents the experimental platform used to evaluate the effectiveness and practical applicability of the proposed fault diagnosis method. The overall workflow of the proposed method is illustrated in Figure 5, which includes offline architecture search and model training, followed by online fault diagnosis on an edge computing device. In the offline stage, the proposed PC-DARTS-SC architecture search strategy is used to automatically derive a task-specific network architecture. The searched architecture is then retrained to obtain the fault diagnosis model, which is subsequently exported to ONNX format for cross-platform deployment. In the online stage, voltage signals are sequentially acquired and processed on a Jetson Orin Nano edge computing device. TensorRT-based inference acceleration is employed to achieve low-latency fault diagnosis for CHMI.

4.1. Experimental Setup and Data Description

Experiments are conducted on a single-phase cascaded H-bridge five-level inverter (CHMI). The experimental platform for acquiring inverter output voltage data is shown in Figure 6. The main circuit of the CHMI platform consists of two cascaded H-bridge inverter units, two DC power supplies, and gate-drive control signals generated by a dSPACE MicroLabBox. The IGBTs used in the experiment are IKW30N60H3 devices, and the output voltage is measured using LV25-P voltage sensors. The main parameters of the experimental platform are summarized in

Table 2. Main parameters of the CHMI experimental platform.

Parameter	Value
DC source voltage	$15\mathrm{V}$
Fundamental frequency	$50\mathrm{Hz}$
Load resistance	$7\mathrm{\Omega }$
Load inductance	$6\mathrm{mH}$/$12\mathrm{mH}$
Sampling frequency	$20\mathrm{kHz}$

. In the experimental setup, single-IGBT OCFs are emulated through a fault-setting circuit by forcing the corresponding IGBT gate-drive signal to zero via a push-button command. This experimental configuration physically reflects the loss of switching functionality induced by an IGBT open-circuit fault, thereby enabling the safe and repeatable collection of inverter output voltage signals under various fault conditions. It is worth noting that this controlled fault-injection approach is used specifically for repeatable laboratory validation.

The inverter output voltage was sampled at 20 kHz. With a fundamental period of $20\mathrm{ms}$, each voltage cycle contained 400 sampling points. For each fault category under each load condition, the output voltage was measured after the inverter reached steady state and then segmented into cycle-level samples. Each sample corresponds to one complete fundamental voltage cycle. No overlapping sliding window was used during sample construction. For each operating condition, 200 labeled cycle-level samples were collected and reshaped into $20\times 20$ matrices to form 2D feature maps. After the cycle-level samples were constructed, the dataset was split into training, validation, and test sets with ratios of 75%, 15%, and 10%, respectively. Each cycle-level sample was assigned to only one subset, and the test set was used only for final performance evaluation. Architecture search and model training were conducted offline, where the training and validation sets were used for architecture search and parameter optimization, and the test set was used for performance evaluation.

In the architecture search process, several hyperparameters were configured to control the search and training process. The resulting architecture contains four special cells for hierarchical feature extraction. The detailed hyperparameter settings are summarized in

Table 3. Hyperparameter settings for architecture search.

Parameter	Value
Optimizer for $\omega$	SGD
Initial learning rate for $\omega$	0.1
Learning rate scheduler	Cosine annealing
Optimizer for $\alpha$	Adam
Learning rate for $\alpha$	$6\times {10}^{-4}$
Weight decay for $\alpha$	$1\times {10}^{-3}$
Channel sampling ratio $(1/K)$	0.25
Search epochs	20

. A cosine annealing learning rate scheduler without restarts was adopted to improve training stability and convergence. The architecture search was conducted for 20 epochs. During the first 6 epochs, only the network weights were optimized, after which the architecture parameters were updated jointly with the network weights.

4.2. Diagnostic Performance of the Proposed Method

To illustrate the fault characteristics of inverter output signals, waveform observations were conducted under inductive load conditions. Figure 7 shows the output voltage waveforms corresponding to two similar fault modes under an RL load of $7\mathrm{\Omega }$ and $6\mathrm{mH}$. The waveforms are presented in a format consistent with oscilloscope measurements. For the pair of similar fault modes defined in Section 2, the overall voltage waveforms remain nearly identical during most of the fundamental period. Waveform discrepancies mainly appear around the load current zero-crossing instants, where the inductive energy stored in the load is released. As shown in Figure 7, these discrepancies are weak and locally distributed, which increases the difficulty of accurate fault diagnosis and motivates the use of cycle-level voltage samples for fine-grained feature extraction.

The waveform discrepancies mainly arise from two types of voltage spikes: relatively large-amplitude spikes induced by load-side inductive discharge and clusters of small-amplitude spikes resulting from the non-ideal switching characteristics of IGBTs. Both phenomena are closely related to the load inductance. Therefore, variations in inductive parameters can significantly influence the manifestation of subtle fault differences. To examine the influence of load inductance variation on the proposed method, two RL load cases are considered to emulate typical motor loads: $(7\mathrm{\Omega },6\mathrm{mH})$ and $(7\mathrm{\Omega },12\mathrm{mH})$, where only the inductance differs. The searched special cell architectures under the two RL load conditions are illustrated in Figure 8.

The searched special cell architectures show a clear preference for operations with a larger receptive field, such as $5\times 5$ and $7\times 7$ separable convolutions. This observation indicates that the inclusion of larger kernel sizes in the search space allows the network to capture subtle waveform variations distributed over different temporal scales. Such multi-scale feature extraction is particularly beneficial for distinguishing highly similar fault modes in CHMI.

4.3. Comparison with Existing Methods

Compared with conventional machine-learning-based fault diagnosis methods using manually designed feature extraction procedures or fixed network architectures, the proposed PC-DARTS-SC framework includes an additional one-time offline architecture search stage. To assess this cost, the architecture search was conducted on a workstation equipped with a single NVIDIA RTX 4060 GPU for 20 epochs. One complete search took 472.95 s, corresponding to 0.0055 GPU-days, and the peak GPU memory allocated during the search was 2.86 GB. After the special cell architecture was obtained, only the final searched diagnostic model was used for retraining, testing, and edge deployment. Thus, the offline search cost does not affect the inference latency of the deployed model. To provide a comprehensive performance evaluation, the proposed fault diagnosis method is compared with several representative data-driven approaches in terms of diagnostic accuracy and testing time. All comparative experiments were conducted under identical operating conditions, where a single-phase CHMI supplies an RL load of $7\mathrm{\Omega }$ and $6\mathrm{mH}$. Due to incomplete implementation details in some reference studies, the compared methods are reconstructed according to their core algorithmic principles. All methods were tested on the same x86 workstation equipped with an Intel CPU and NVIDIA GPU. For statistical reliability, each approach was evaluated under the fixed data split and parameter settings, and the average diagnostic accuracy and testing time are reported. The diagnostic accuracy is reported as mean ± standard deviation (SD) and 95% confidence interval (CI). The comparative results of different methods are summarized in

Table 4. Performance comparison with representative fault diagnosis methods on the test set.

Sample (Groups)	Diagnosis Method	Diagnosis Accuracy (%, Mean ± SD)	95% CI	Testing Time (s)
	PCA-ELM [47]	90.50 ± 3.19	[88.22, 92.78]	0.032
	FFT-PCA-SVM [19]	98.33 ± 0.00	[98.33, 98.33]	0.062
180	FFT-PCA-BPNN [48]	94.12 ± 4.80	[90.73, 97.59]	0.102
	1D-CNN [49]	98.28 ± 2.10	[96.77, 99.78]	0.056
	Proposed method	$99.44\pm 1.05$	[98.69, 100.00]	0.086

.

For FFT-PCA-SVM method, the result remains unchanged across repeated runs under the fixed data split and parameter settings because the method does not involve random network initialization. The proposed method achieves the highest average diagnostic accuracy among the compared methods. However, considering the relatively small test set and the close performance between the proposed method and the 1D-CNN baseline, the numerical improvement in accuracy should be interpreted cautiously. The advantage of the proposed method lies not only in the average diagnostic accuracy but also in its automatically searched lightweight architecture.

Notably, for the fault diagnosis model corresponding to the architecture shown in Figure 8a, the final model obtained after offline architecture search and retraining contains only 0.2417 M trainable parameters, corresponding to approximately 0.97 MB of FP32 parameter storage. This indicates a compact and lightweight architecture, making the model suitable for deployment on resource-constrained edge computing platforms. Moreover, even under CPU-only execution, the model achieves an average inference time of less than 20 ms per sample. Since one fundamental voltage cycle lasts 20 ms, the measured inference latency suggests the feasibility of cycle-level fault diagnosis.

To further evaluate the influence of the NAS search strategy, a focused ablation comparison is conducted between DARTS-SC and the proposed PC-DARTS-SC. Directly adopting reduction cells originally designed for image classification may not be well matched to the small-size reshaped voltage feature maps ($20\times 20$), because premature feature-map downsampling may weaken localized fault-related distortions. Therefore, this ablation focuses on comparing DARTS-SC and PC-DARTS-SC under the same $20\times 20$ input representation and the same special-cell search strategy. For each NAS variant, the architecture selected according to the validation performance during the offline search stage was retrained and then evaluated on the test set. For the proposed PC-DARTS-SC method, the architecture shown in Figure 8a is used as the representative searched architecture under the RL load of $(7\mathrm{\Omega },6\mathrm{mH})$. The corresponding diagnostic accuracy, search cost, and trainable parameter count are reported in

Table 5. Comparison of DARTS-SC and the proposed PC-DARTS-SC under the same input representation and special cell search strategy.

Method	Accuracy (%)	Search Cost (GPU-Days)	Params (M)
DARTS-SC	100.00	0.0082	0.1708
Proposed method (PC-DARTS-SC)	100.00	0.0055	0.2417

.

As shown in Table 5, both DARTS-SC and PC-DARTS-SC achieve 100.00% diagnostic accuracy on the test set. Compared with DARTS-SC, the proposed PC-DARTS-SC reduces the search cost from 0.0082 to 0.0055 GPU-days while maintaining the same diagnostic accuracy. Although the proposed PC-DARTS-SC contains slightly more trainable parameters, its parameter scale remains compact for edge-side deployment. These results indicate that the proposed PC-DARTS-SC provides a more efficient search process under the considered special-cell search strategy.

In practical inverter systems, measured voltage signals may be affected by various disturbances, such as switching noise, quantization noise, measurement noise, and low-frequency oscillation noise [50]. These disturbances may degrade the performance of fault diagnosis algorithms. Since different disturbance sources are strongly related to the hardware layout, sensor characteristics, grounding conditions, and operating environment, it is difficult to construct a unified mathematical model that can accurately represent all practical noise types. In data-driven fault diagnosis studies, zero-mean additive white Gaussian noise (AWGN) is commonly adopted as a controllable perturbation for quantitative noise-sensitivity evaluation [7,51]. Since the experimental data were collected under relatively stable laboratory conditions, and the experimental environment is relatively stable, it is difficult to naturally acquire labeled samples with different and controllable noise level. Therefore, AWGN with different signal-to-noise ratios (SNRs) is artificially added to the original voltage signals to provide a noise-sensitivity evaluation. It should be noted that the AWGN-based test is not intended to fully emulate all practical inverter noise sources. The original voltage signals are experimentally measured from a physical CHMI prototype and thus inevitably contain certain hardware-induced non-ideal effects, such as switching transients and measurement-chain disturbances. The noise level is quantified using the SNR, which is defined as:

$$\mathrm{SNR}=10{log}_{10}\left({\displaystyle \frac{P_s}{P_n}}\right)$$

(7)

where $P_s$ and $P_n$ denote the powers of signal and noise, respectively. The experiments were conducted at SNR levels ranging from 45 dB to 30 dB, covering different levels of additive noise disturbance. The comparative diagnostic results are summarized in

Table 6. Comparison of diagnostic accuracy under different SNR conditions.

Method	45 dB	40 dB	35 dB	30 dB
1D-CNN	98.26%	97.09%	94.44%	92.20%
FFT-PCA-SVM	97.35%	96.52%	89.67%	86.97%
PCA-ELM	90.87%	89.62%	87.13%	84.44%
Proposed method	99.54%	99.23%	98.78%	96.33%

. This evaluation provides insight into the noise sensitivity of the proposed method under controlled additive noise conditions.

4.4. Edge Deployment Performance Evaluation

The above experiments demonstrate that the proposed method achieves high diagnostic accuracy under the investigated RL load conditions. To further evaluate its deployment feasibility under edge-computing constraints, the selected trained model is deployed on a Jetson Orin Nano edge computing platform. For cross-platform compatibility and efficient execution, the selected PyTorch format fault diagnosis model is first converted to the ONNX format and executed using an optimized inference runtime. Subsequently, the converted model is further optimized using TensorRT to accelerate inference. As illustrated in Figure 9, TensorRT performs a series of edge-oriented optimizations, including mixed-precision inference (FP16), layer and tensor fusion, dynamic tensor memory management, and kernel auto-tuning. These strategies are mainly intended to improve inference efficiency on embedded hardware. When FP16 acceleration is enabled, some operations may be executed in half precision, which may introduce slight numerical differences compared with FP32 inference. Therefore, FP16 optimization should not be interpreted as improving the inherent diagnostic capability of the trained model. It should be noted that the edge deployment experiment is conducted using the PyTorch model corresponding to the searched architecture shown in Figure 8a, which is obtained after offline architecture search and retraining. The average diagnostic accuracy reported in Section 4.3 is calculated over ten independent workstation trials and should not be directly compared with the deployment result of a single exported model. Therefore, the accuracy reported in this section is used to evaluate deployment consistency, rather than to indicate an accuracy improvement caused by inference optimization.

During edge deployment and latency evaluation, the inference batch size is set to one, which is consistent with practical online fault diagnosis scenarios where samples are sequentially processed. All performance evaluations are conducted on the NVIDIA Jetson Orin Nano platform, and the detailed hardware and software configurations are summarized in

Table 7. Hardware and software configuration of the edge deployment platform.

Framework	Version	Component	Specification
Torch	2.5	AI Performance	67 TOPS
TensorRT	10.7	SPECint_rate	118
CUDA	12.6	GPU Frequency	1020 MHz
Torchvision	0.20	CPU Frequency	1.7 GHz
JetPack	6.2	Tensor Cores	32
System	Ubuntu 22.04.5 LTS	Memory	8 GB

. After ONNX conversion and TensorRT optimization, the comparative inference performance across different inference backends is summarized in

Table 8. Inference performance comparison on different inference backends.

Device	Inference Backend	Accuracy (%)	Inference Time (ms/Sample)
Jetson Orin Nano	ONNX Runtime (CPU)	100.0	8.42
Jetson Orin Nano	ONNX Runtime (CUDA)	100.0	4.21
Jetson Orin Nano	TensorRT (FP16)	100.0	3.54

.

The experimental results show that the selected model maintains 100.0% diagnostic accuracy across the tested inference backends, which is consistent with its PyTorch reference result before deployment. This indicates that the edge deployment process does not degrade the inference performance of the selected model in this experiment. In particular, TensorRT-based FP16 inference significantly reduces the per-sample inference latency on the Jetson Orin Nano platform. In particular, TensorRT-based FP16 inference significantly reduces the per-sample inference latency on the Jetson Orin Nano platform. By integrating neural architecture search with edge-oriented inference acceleration, the proposed method demonstrates the potential of automatically designed neural architectures for low-latency edge-side inverter fault diagnosis.

5. Discussion and Limitations

This paper integrates neural architecture search (NAS) with edge deployment for inverter fault diagnosis. Different from conventional fault diagnosis methods that rely on manually designed feature extraction procedures or manual neural network architectures, the proposed PC-DARTS-SC framework automatically searches for a task-adaptive diagnostic architecture based on measured voltage signals. The experimental results show that the searched architecture is effective in distinguishing highly similar single-IGBT OCF modes under the investigated laboratory conditions. In particular, the proposed special cell search strategy avoids premature feature-map downsampling and helps preserve weak and localized voltage distortions in the reconstructed voltage samples. In addition, the deployment results on the Jetson Orin Nano platform indicate that the searched lightweight model can achieve low-latency inference on resource-constrained edge hardware.

Nevertheless, several limitations should be acknowledged. First, the experiments are conducted on a single-phase five-level CHMI prototype, controlled single-IGBT OCF cases, and two investigated RL load conditions. Therefore, the reported results mainly demonstrate the feasibility and effectiveness of the proposed method within the considered experimental domain. Broader generalization to different inverter configurations, hardware platforms, control strategies, and operating conditions has not been fully validated in this study and requires further investigation. Second, although the fault data are experimentally measured from a physical inverter prototype, the faults are emulated under controlled laboratory conditions by disabling the corresponding IGBT gate-drive signals. This setting enables safe, repeatable, and balanced data acquisition, but it cannot fully reproduce naturally developed faults, long-term device aging, sensor drift, load transients, or complex electromagnetic interference in practical applications.

Regarding the data splitting strategy, the adopted cycle-level split avoids direct overlap between samples because each sample corresponds to one complete fundamental voltage cycle and no overlapping sliding window is used. However, this cycle-level random split does not guarantee strict temporal independence between the training and test samples, since adjacent voltage cycles may still originate from the same continuous acquisition sequence and may exhibit temporal correlation. Therefore, the current results should be interpreted as diagnostic performance under the adopted cycle-level non-overlapping split strategy. A stricter time-ordered or cycle-block-based split will be further investigated in future work to assess the influence of temporal dependence on diagnostic performance. In addition, the proposed framework includes an offline architecture search stage, which introduces extra computational cost during model development. However, this search process is performed before deployment, and only the final compact diagnostic model is used for inference. Future work will further investigate cross-condition adaptation, validation on different inverter platforms, more diverse fault types, and field-measured fault data to improve the practical applicability of the proposed method.

6. Conclusions

To address the difficulty of distinguishing highly similar OCF modes in CHMI, this paper proposes an edge-oriented intelligent fault diagnosis framework based on DARTS. The main conclusions of this paper can be summarized as follows: (1) A data-driven CHMI fault diagnosis method is developed to automatically derive task-specific diagnostic architectures from measured voltage signals, reducing the reliance on manual network design. (2) A simplified differentiable special cell search strategy is introduced to preserve fine-grained voltage features and obtain lightweight neural architectures suitable for edge deployment. (3) The experimental results under the investigated RL load conditions demonstrate that the searched architecture achieves high diagnostic accuracy, and the deployment evaluation on a Jetson Orin Nano platform confirms its efficient inference capability.

As artificial intelligence continues to evolve, edge intelligence is expected to play an increasingly important role in bringing intelligent diagnostic capabilities closer to industrial systems. From the perspective of artificial intelligence for power electronic systems, this study suggests that automated architecture design can provide a feasible route for developing compact and task-adaptive diagnostic models for edge deployment. Despite these encouraging results, several challenges remain for practical applications. In particular, the availability and quality of labeled fault data, as well as the robustness of data-driven models under complex industrial environments, still require further investigation. Future work will extend the proposed framework to more complex inverter topologies and operating conditions, while exploring more adaptive deployment strategies for practical industrial scenarios.