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Article

Micro- and Nano-Integration in the Production of GaAs and Ga2O3 Nanowire Arrays by Top-Down Design

by
Elena I. Monaico
1,
Eduard V. Monaico
1,*,
Veaceslav V. Ursaki
1,2 and
Ion M. Tiginyanu
1,2
1
National Center for Materials Study and Testing, Technical University of Moldova, Bv. Stefan cel Mare 168, 2004 Chisinau, Moldova
2
Academy of Sciences of Moldova, Bv. Stefan cel Mare 1, 2001 Chisinau, Moldova
*
Author to whom correspondence should be addressed.
J. Manuf. Mater. Process. 2025, 9(11), 376; https://doi.org/10.3390/jmmp9110376 (registering DOI)
Submission received: 22 October 2025 / Revised: 9 November 2025 / Accepted: 14 November 2025 / Published: 16 November 2025
(This article belongs to the Special Issue Recent Developments in Materials Processing for Modern Applications: Advancements and Challenges)
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Abstract

In this paper, a strategy is proposed based on the microstructuring of GaAs substrates by photolithography combined with nanostructuring by electrochemical etching for the purposes of obtaining GaAs nanowire domains in selected regions of the substrate. The micropatterning is based on previously obtained knowledge about the mechanisms of pore growth in GaAs substrates during anodization. According to previous findings, crystallographically oriented pores, or “crysto pores,” grow along specific crystallographic directions within the GaAs substrates, with preferential propagation along the <111>B direction. Taking advantage of this feature, it is proposed to pattern the (111)B surface by photolithography and to, subsequently, apply anodization in an HNO3 electrolyte. It is shown that the areas of the GaAs substrate under the photoresist mask are protected against porosification due to the growth of pores perpendicular to the surface of the substrates in such a configuration. Pores overlapping under adjusted electrochemical etching conditions results in the formation of GaAs nanowire arrays in the substrate regions not covered by photoresist. Thermal annealing conditions in an argon atmosphere with a low oxygen concentration were developed for the selective oxidation of GaAs nanowires, thus producing a wide-bandgap Ga2O3 nanowire pattern on the GaAs substrate. It is shown that the morphology of nanowires can be controlled by adjusting the electrochemical parameters. Smooth-walled nanowire arrays were obtained under specific conditions, while perforated and wall-modulated nanowires were formed when crystallographic pores intersected at a higher applied anodizing potential.

1. Introduction

Porous semiconductor compounds [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18] and semiconductor nanowire networks [19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47] are two classes of nanomaterials with broad prospects in various practical applications. These materials are related to each other in the sense that nanowires can form in porous materials under certain conditions of electrochemical etching, leading to overlapping of pores, such that the porous skeleton is transformed into nanowires [38,39,40,41,42,43,44,45,46,47]. This technology complements the production of semiconductor nanowires using catalyst-assisted or self-catalyzed vapor–liquid–solid (VLS) processes [19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37]. VLS processes are widely used and include a variety of methods, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE). As for nanowire materials produced by VLS technology, these include InP [19,20], GaP [21], GaAs and GaAsSb [22,23,24,25,26,27,28], GaN [29,30,31], ZnS [30], ZnO [33,34], and other materials [35,36,37]. In terms of geometric parameters, VLS growth typically produces nanowires with a diameter of tens of nanometers and a length of several microns, while nanowires with a diameter of tens to hundreds of nanometers and a length of up to a hundred microns can be obtained by electrochemical etching.
Since these semiconductor nanowires cover a wide spectral range, from near-infrared (NIR) to ultraviolet (UV), in terms of band gap and have useful properties, they have found wide applications in energy, photocatalysis, sensors, electronics, optoelectronics, spintronics, photonics, microwave and terahertz devices, piezoelectric generators, and other emerging fields. Among other semiconductor nanowires, GaAs nanowires are of significant interest for next-generation optoelectronic devices due to their superior electrical and optical properties, including high electron mobility and a direct band gap, which enable efficient light-to-current conversion and photon absorption. The one-dimensional architecture of nanowires further enhances these properties by increasing surface area and facilitating charge carrier transport, making them crucial for applications in areas such as solar cells [22], photodetectors [27,28,44], high-performance vertical transistors [26], field emission [42], and other applications. In particular, GaAs nanowires with low defect density were synthesized by combining MBE with the droplet wetting method, which effectively reduced nonradiative recombination and enabled the creation of high-performance dual-band photodetectors for visible (VIS) to near-infrared wavelengths [28]. When GaAs nanowire arrays are coated with ZnO shells, they show promise for polarized light emission applications [46], while GaAs nanowires coated with ferromagnetic shells are of interest for magnetic data storage [44].
Regarding the preparation of semiconductor nanowires by overlapping pores during electrochemical etching, it was found that two types of pores propagate in semiconductor substrates, namely current-line-oriented “curro pores” and crystallographically oriented “crysto pores” [1]. However, only “crysto pores” growing along definite crystallographic directions were found in GaAs substrates, with preferential propagation along the <111>B direction, regardless of the initial surface orientation, with an angle of approximately 109° between the pores (which tend to have a triangular cross-section).
GaAs nanowire arrays with high aspect ratio and triangular cross-section were prepared with a complex multi-step technology that combines colloidal crystal templating, anisotropic chemical etching, localized anodic etching, and isotropic anodic oxidation [39,40]. A simpler and more cost-effective approach has been proposed for the preparation of triangular GaAs nanowires by the electrochemical etching of GaAs(100)-oriented substrates in an aqueous KOH solution [41]. A disadvantage of this method is related to the difficulty of controlling the technological process and the formation of only GaAs nanowire bundles, while their orientation was largely random, in certain regions of the surface. To overcome these issues, it has been proposed to carry out anodization of GaAs(111) wafers in acidic HNO3 electrolytes, achieving a single-stage formation of triangular-shaped GaAs nanowires that are well oriented and perpendicular to the substrate surface [43]. The size of the resulting nanowires in the cross-section perpendicular to the nanowire axis is determined by the width of the space charge region (SCR) created inside the nanopore wall at the interface with the electrolyte during anodization [48], which means that it can be controlled by changing the concentration of charge carriers in the GaAs wafer. The higher the carrier concentration, the narrower the SCR and the thinner the nanowires obtained.
In this work, we report on the fabrication of GaAs and Ga2O3 nanowire arrays in defined areas of a GaAs wafer, where the nanowires are oriented perpendicular to the wafer surface (while other areas of the wafer surface remain intact), by combining photolithographic patterning with the electrochemical etching of GaAs(111) wafers in acidic HNO3 electrolytes and thermal oxidation.

2. Materials and Methods

N-type GaAs single crystals doped with Si, resulting in a free electron concentration of 2 × 1018 cm−3 (with a (111) crystallographic orientation and a thickness of 500 µm), were purchased from Mateck GmbH, Jülich, Germany, and they were used for nanostructuring. In this work, the (111)B orientation refers to the Ga-terminated face of the GaAs crystal, whereas the (111)A orientation refers to the As-terminated face. The GaAs substrates were cleaned by immersing them for 3 min in a diluted HCl solution (HCl:H2O = 1:3, v/v) to remove the surface oxide, and they were then subjected to acetone sonication and rinsed with deionized water.
Semiconductor substrates were etched electrochemically using a potentiostatic three-electrode cell (schematically depicted in Figure 1a). The substrate functioned as the working electrode (WE), while the counter electrode (CE) consisted of a platinum mesh (active surface: 6 cm2). A commercially available Ag/AgCl electrode (BASi MF-2052) was employed as the reference electrode (RE). The process was carried out in an aqueous nitric acid solution (1 M HNO3) at ambient temperature (23 °C).
In addition to direct electrochemical etching, a photolithography-assisted process was employed prior to etching to define stripe patterns with a width of 100 µm and an interspacing of 90 µm. Prior to resist coating, the GaAs substrates were cleaned sequentially in ultrasonic bath, deionized water, and isopropyl alcohol. A positive photoresist layer AZ 1505, ~1 µm (AZ Electronic Materials GmbH, Darmstadt, Germany), was deposited by spin coating at 4500 rpm for 40 s and then, subsequently, soft-baked at 90 °C for 15 min. The photoresist layer was then exposed using a MJB3 Karl Suss mask aligner (SUSS MicroTec, Garching, Germany), and it was then developed to transfer the designed pattern onto the substrate surface.
The thermal treatment enabling the transformation of GaAs nanowires into Ga2O3, using the setup schematically shown in Figure 1b, was performed at 900 °C in an argon flow containing 3% oxygen. The closed-type quartz reactor (50 cm length and 8 cm diameter) was equipped with a resistive heater allowing temperature control up to 1000 °C with ±2 °C accuracy, as well as manual flowmeters for regulating the Ar/O2 gas mixture. After reaching the target temperature, the samples placed in ceramic crucibles were introduced into the reactor, which was sealed with a stainless-steel cap, providing inlet and outlet connections for the gas flow. Continuous gas circulation was ensured, with the entire system operating inside a fume hood. The treatment duration of 1 h was optimized to achieve complete conversion of the semiconductor nanowires into oxides, while the low oxygen content enabled selective oxidation of the nanowires without affecting the GaAs substrate. To prevent detachment of the nanowires, the samples were only removed after cooling the reactor to 150 °C.
The surface and cross-sectional morphologies of the electrochemically etched, as well as annealed, samples were analyzed using a TESCAN Vega TS 5130 MM scanning electron microscope (SEM) (Brno, Czech Republic) equipped with an Oxford energy-dispersive X-ray (EDX) detector operating at 20 kV. The crystalline phases were identified by the X-ray powder diffraction (XRD) technique using a Bruker AXS D8 Discover (Bruker AXS, Karlsruhe, Germany) diffractometer with Cu Kα1 radiation (λ = 0.15406 nm) in a standard 2θ Bragg–Brentano configuration, operating at 40 kV and 40 mA. Raman spectra were recorded using a Renishaw InVia Raman system (Renishaw plc, Wotton-under-Edge, UK) in backscattering geometry at room temperature under illumination by the 532 nm line of a CW DPSS laser.

3. Results and Discussion

3.1. GaAs Substrate Patterning, Electrochemical Fabrication, and Morphology Control of GaAs Nanowire Arrays

A photoresist mask in the form of a 100 µm wide strip was deposited on the surface of a (111)B-oriented GaAs substrate to demonstrate the feasibility of forming patterned nanowire arrays in selected areas of the substrate, leaving the areas of the substrate under the photoresist intact. Figure 2a shows the SEM image of the sample after anodization for 20 min in a 1M HNO3 aqueous electrolyte at an applied voltage of 4.0 V and with the removal of the photoresist mask. The electrolyte concentration of 1M and the applied potential of (3.0–4.0) V during anodization were found to be optimal for pore overlap, resulting in the formation of triangular nanowires, as well as for suppressing lateral pore growth [43,44,45,46]. These technological conditions ensure the formation of GaAs nanowires with smooth and uniform sidewalls, as illustrated in Figure 2b, indicating a stable and well-controlled anodization regime performed at 4.0 V in 1M HNO3. A rough estimate of the nanowire density suggests a value of the order of ~108 nanowires/cm2.
The length of the obtained nanowires was about 50 µm. Producing long nanowire arrays is an advantage of the proposed technology, since some optoelectronic applications require long arrays of nanowires, such as for the generation and detection of polarized light [46]. Another advantage is related to the production of nanowires at room temperature, which reduces the technology cost. Although nanowires produced by VLS processes are of good quality, their length is limited, and the technology requires much higher temperatures. Furthermore, the top-down approach combining photolithographic patterning with electrochemical etching ensures a higher degree of control over the spatial arrangement and geometry of the nanowires compared to the VLS and other bottom-up epitaxial growth methods. This method allows for their direct formation in predefined areas of the wafer without the use of catalysts, which eliminates possible metal contamination and maintains the crystallographic integrity of the substrate. In addition, all processing steps can be carried out under moderate conditions using standard equipment compatible with microfabrication technologies.
As previously discussed, the anisotropic electrochemical dissolution characteristics of GaAs and the polar nature of the (111)B surface favor pore propagation along the <111>B direction, which is perpendicular to the (111)B substrate surface. As a result, the produced nanowire arrays are also perpendicular to the substrate surface, and the pores do not extend under the photoresist mask, as can be seen from the cleavage in Figure 2a. The confinement of pore growth strictly to areas unprotected by the photoresist is characteristic only for GaAs substrates with (111)B orientation. As shown in Figure 2c, for the (100)-oriented GaAs substrate, the pores were tilted relative to the substrate surface, which will result in the pores spreading under the photoresist mask. The same is true for a (111)A-oriented GaAs substrate.
The ability to protect the substrate area under the photoresist mask against pore formation is also guaranteed by the particularity of GaAs to form only “crysto pores”, as has been previously demonstrated [1]. In case of formation of “curro pores”, they easily propagate under the photoresist mask, as illustrated in Figure 2d,e for an InP substrate [45]. The part of the surface protected by the photoresist mask (left side) is shielded against electrochemical etching from above. Under anodizing, pores nucleate on the unprotected part of the surface (right side), and they initially grow in the direction perpendicular to the wafer surface. However, at a later stage of the growth process, they are deflected under the photoresist mask due to the current lines, and they propagate in the direction parallel to the wafer surface. These pore arrays are hidden under a thin surface layer, the thickness of which is equal to the width of a space charge region, which is transparent to electrons in the SEM equipment.
Increasing the applied voltage beyond a critical threshold promotes the generation of intersecting lateral pores, as evidenced by the perforated nanowire architectures shown in Figure 2f. At higher voltages, such as 4.8 V, the increased electric field intensity triggers a transition in the etching dynamics, facilitating the nucleation of lateral pores intersecting the primary vertically aligned nanowires. This leads to the formation of perforated or modulated nanowires, as illustrated in Figure 2f. Furthermore, the dimensional attributes of the nanowires, including diameter, length, and spacing, can be precisely modulated by adjusting the anodization time, electrolyte composition, and photomask geometry. This tunability allows for the customization of nanowire arrays with enhanced surface area to meet specific requirements for optoelectronic, catalytic, and sensing applications.
The controlled fabrication of these GaAs nanowire arrays provides a robust foundation for the subsequent thermal oxidation processes, which convert GaAs nanowires into wide-bandgap Ga2O3 structures, as discussed in the following section.

3.2. Selective Oxidation of GaAs Nanowires for Hybrid Semiconductor–Oxide Platforms

Figure 3a presents a SEM image of GaAs nanowires with cross-sectional sizes ranging from, approximately, 100 to 400 nm. These nanostructures were fabricated by electrochemical etching at an applied potential of 4 V in a 1 M HNO3 electrolyte, as described in Section 2. The resulting nanowire arrays exhibited vertical alignment and uniform morphology across the processed surface.
Subsequent thermal annealing (TA) was carried out at 900 °C for 1 h in an argon atmosphere with a low concentration of oxygen (3%). This annealing led to the conversion of GaAs nanowires into gallium oxide (Ga2O3) nanowires, while avoiding oxidation of the GaAs substrate, as shown in Figure 3b. The transformation maintained the overall shape of the nanowire network. A significant charging effect was observed, consistent with the formation of a dielectric oxide phase, during SEM imaging of the oxidized nanostructures.
The chemical transformation was confirmed by energy-dispersive X-ray spectroscopy, with the spectral data shown in Figure 4 and summarized in Table 1. According to these data, the nanowires were completely oxidized to Ga2O3 while maintaining their triangular geometry, and the GaAs substrate retained its original chemical composition. The selectivity of oxidation was confirmed by EDX Spectrum 4 (see Figure 4c), which did not show significant oxidation of the substrate due to the limited oxygen content in the carrier gas. However, with a significant increase in the oxygen concentration, oxidation of the GaAs substrate also occurred.
Further structural characterization using SEM imaging with a backscattered electron detector (BSD) (see Figure 4d,e), taken in both cross-sectional and top views, revealed contrast variations corresponding to compositional differences between the nanowires and the substrate. The use of a BSD detector is particularly effective in distinguishing the regions consisting of materials with different atomic numbers, making this method popular in the study of composite and heterogeneous materials.
Another key parameter that influences the outcome of the oxidation process is the duration of the thermal treatment. It was found that, under certain conditions, only the outer shell of the GaAs nanowires is converted to Ga2O3, while the inner core remains unoxidized. The thickness of the Ga2O3 shell increases with both the oxidation temperature and the duration of thermal treatment. For example, annealing at 900 °C for 30 min leads to partial oxidation, forming a core–shell structure with a GaAs core and a Ga2O3 shell, whereas longer annealing times, such as 1 h, result in complete conversion of the nanowires to Ga2O3. The formation of core–shell structures can provide additional functional benefits for applications requiring coupled semiconductor–oxide architectures.
A more detailed analysis of the XRD pattern shown in Figure 5 confirms the crystallinity of Ga2O3 nanowires with the retention of the predominant (111) orientation after the thermal treatment of GaAs nanowires with the same initial crystallographic orientation. The XRD pattern exhibited characteristic reflections corresponding to a monoclinic Ga2O3 crystal structure within the C2/m space group. These included reflections indexed as (−201), (−401), (002), (−111), (111), (401), (−311), (600), (−510), (−603), (403), (220), and (−804), which is consistent with the standard powder diffraction file (PDF) Card No. 43-1012 for Ga2O3 [49]. The presence of multiple reflections confirms the high degree of crystallinity and phase purity of the oxide nanowires.
Simultaneously, diffraction peaks from the GaAs substrate remained visible in the pattern, as identified by PDF Card No. 00-032-0389 [50]. This coexistence confirms that the thermal oxidation process selectively transforms nanowires while largely preserving the crystallinity and composition of the substrate. This selective oxidation is essential for maintaining the electronic properties of the substrate, allowing for potential device integration.
These data have been corroborated by the results of Raman scattering analysis, as shown in Figure 6, for four samples. The Raman spectrum of the (111)B-oriented GaAs substrate (curve 1) exhibited the TO phonon peak around 269 cm−1 and the LO peak at 292 cm−1. Since the GaAs substrate was heavily doped, with free electron concentration of 2 × 1018 cm−3, the LO phonon–plasmon coupled modes L− and L+ were also observed in the spectrum [51], with the L− band overlapping the TO peak. The L− and L+ signals originated from the substrate bulk, while the LO signal came from the surface depletion region.
The Raman spectrum of the GaAs nanowire array (curve 2) exhibited the same features, indicating that the high crystalline quality of the obtained nanowires was maintained. However, the ratio of the LO peak intensity to the LO phonon–plasmon-coupled modes was increased in the nanowire array because the ratio of the surface to volume was higher in the nanowire array when compared to the pristine substrate.
The Raman spectrum of the GaAs nanowire array subjected to thermal annealing at 900 °C for 1 h (curve 4) contained only the modes related to the monoclinic crystal structure of Ga2O3 in the β-phase, according to the assignment that is presented in Table 2 [52].
As for the spectrum of the GaAs nanowire array subjected to thermal annealing at 900 °C for 30 min (curve 3), it contained Raman modes related to both the zinc blende-type GaAs and monoclinic-type Ga2O3. It was assumed that the Raman modes related to the zinc blende type GaAs originated from the core of the nanowires, while those related to monoclinic type Ga2O3 originated from the shell. However, this assumption requires confirmation by a detailed high-resolution TEM investigation.
Regarding the oxidation mechanisms of GaAs nanowires, it can be assumed that they are similar to those that occur during the growth of Ga2O3 nanowires by oxidation of GaAs substrates and include three processes, such as GaAs decomposition, Ga accumulation, and As evaporation, as well as Ga2O3 formation [53]. The decomposition of the GaAs surface during the first process occurred due to the diffusion of arsenic through the substrate and its evaporation. Gallium accumulation in the second process led to the generation of liquid Ga clusters on the surface of the GaAs substrate. At this stage, arsenic atoms diffused through the generated liquid Ga clusters and were desorbed from the wafer surface. According to thermodynamic studies of Ga on GaAs, the loss of arsenic through liquid Ga is faster than the diffusion of arsenic through the substrate [54,55]. Ga is oxidized to produce Ga2O3 in the third process, where oxygen from the gas flow and Ga clusters chemically interact on the surface of the GaAs substrate.
According to Langmuir evaporation, the GaAs surface becomes unstable when the temperatures is above 600 °C, and the deviation from stoichiometry manifests itself in the evaporation of arsenic, leaving gallium on the GaAs surface [56]. The possible decomposition of GaAs was previously evaluated by studying the Gibbs free energy of reactions at different temperatures [57]. It was found that the reaction temperature in the thermal oxidation process should be kept between 600 °C and 1093 °C for effective oxidation. Based on these evaluations, the reaction temperature was set at 900 °C to ensure the decomposition of the GaAs surface and the efficient production of Ga2O3.
Another important issue is related to the interfacial stress, which occurs during the GaAs oxidation process due to lattice mismatch and differential thermal expansion. This stress has been shown to be useful for the fabrication and transfer via spontaneous delamination of large-area, high-quality β-Ga2O3 nanoscale thin films during thermal oxidation of reusable GaAs substrates [58]. However, in many device applications, the stress at the GaAs/Ga2O3 interface is detrimental and must be reduced. As can be seen from Figure 4, the mechanical stability at the interface between the Ga2O3 nanowires and the substrate is quite good, with no obvious cracks. The interface should be even better in the case of core–shell structures, where the GaAs core is genetically related to the GaAs substrate. Consequently, this technological hybrid route represents a simple and scalable alternative for producing GaAs and Ga2O3 nanowire arrays integrated on the same substrate.
The technology also enables the production of Ga2O3 nanowires and core–shell structures that are much longer than those grown by VLS and other bottom-up epitaxial growth methods. For example, the length of Ga2O3 nanorods grown by the CVD method was limited to 5–15 µm [54], the length of Ga2O3 nanorods grown by MOCVD was limited to approximately 2 µm due to the growth saturation in the axial direction [59], and the length of Ga2O3 nanowires prepared by thermal oxidation of GaAs substrate was about 1–3 µm [53,57].
Thermal processing has proven to be a cost-effective approach that does not require complex equipment and allows for the formation of arrays of wide-bandgap Ga2O3 nanowires with diameters ranging from 50 nm to 500 nm on narrow bandgap semiconductor substrates. The underlying semiconductor substrates with a narrower bandgap (e.g., GaAs) provide significantly higher thermal conductivities (up to 44 W·m−1·K−1 [60,61]) compared to the corresponding oxides, which typically exhibit thermal conductivities of around 10 W·m−1·K−1 [62,63]. This combination of wide-bandgap oxide nanostructures supported on semiconductor platforms with high thermal conductivity is particularly advantageous for applications requiring efficient heat dissipation and stable operation under thermal stress.

4. Conclusions

The results of this work demonstrate possibilities of selective patterning GaAs nanowire arrays in GaAs substrates by combining photolithography with electrochemical etching and their selective transformation into Ga2O3 nanowire arrays by thermal oxidation. Selective patterning is ensured by the peculiarities of pore growth in (111)B-oriented GaAs substrates, in which the pores strictly propagate in the <111>B direction perpendicular to the wafer surface, as well as by the absence of current-line-oriented pores in GaAs substrates. As a result, pore growth is facilitated in areas of the wafer without the photoresist mask, while it is prohibited under the photoresist mask. Vertically aligned nanowires with smooth walls and well-defined morphology were obtained by optimized electrochemical etching, minimizing the development of lateral pores. Based on knowledge that the pore diameter and the thickness of the skeleton in porous structures are determined by the carrier concentration in the substrate material, it can be assumed that the transverse dimensions of nanowires can be tuned within the range from 50 nm to 500 nm depending on the electrochemical etching parameters and the carrier concentration in the substrate material. Perforated and wall-modulated nanowires can also be produced at a higher applied anodization potential when crystallographic pores intersect with each other. Selective oxidation of nanowires, leaving the substrate unoxidized, provides conditions for the fabrication of wide-bandgap (Eg ≈ 4.9 eV) Ga2O3 nanowire arrays on narrower-bandgap (Eg ≈ 1.44 eV) GaAs substrates, which is essential for potential device integration in advanced nanoelectronic and optoelectronic applications.

Author Contributions

Conceptualization, E.V.M. and V.V.U.; methodology, E.I.M., V.V.U. and E.V.M.; validation, V.V.U. and E.V.M.; investigation, E.I.M. and E.V.M.; writing—original draft preparation, V.V.U. and E.V.M.; writing—review and editing, V.V.U., E.V.M. and I.M.T.; visualization, E.I.M. and E.V.M.; supervision, I.M.T.; project administration, E.V.M.; funding acquisition, E.V.M. All authors have read and agreed to the published version of the manuscript.

Funding

This work was funded by Ministry of Education and Research from the Republic of Moldova (institutional subprogram #02.04.02 “Development of technologies and investigation of the properties of layered semiconductor compounds, hybrid nanostructures and laser sources” institutional financing contract no. 2/CC as of 28 January 2025) and #25.80013.5007.08GER project “DEHYCONA—Exploring the feasibility for the DEvelopment of Hybrid COmposite NAnomaterials”.

Data Availability Statement

The data presented in this study are available on request from the corresponding authors.

Conflicts of Interest

The authors declare no conflicts of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

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Figure 1. (a) Schematic representation of the GaAs wafer nanostructuring process by electrochemical etching. (b) Illustration of the thermal treatment process applied to GaAs nanowires for their oxidation.
Figure 1. (a) Schematic representation of the GaAs wafer nanostructuring process by electrochemical etching. (b) Illustration of the thermal treatment process applied to GaAs nanowires for their oxidation.
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Figure 2. (a) Oblique-view SEM image of a cleaved (111)B GaAs wafer anodized for 20 min in a 1 M HNO3 aqueous electrolyte at an applied voltage of 4.0 V with a photolithographic mask (the photoresist mask being removed after anodization). (b) Enlarged image of a GaAs nanowire array produced in the photoresist-free region of the substrate. (c) SEM image of an anodized (100) GaAs substrate illustrating the formation of tilted pores. (d) Top-view SEM image of a porous InP sample anodized with a photoresist mask illustrating the propagation of current-line-oriented pores under the photoresist mask. (e) Cross-sectional SEM view of the porous InP sample showing the bending of “curro” pores under the photoresist mask. (f) Nanowires with modulated walls and internal perforations obtained in a (111)B GaAs substrate at a higher anodizing potential of 4.8 V. The inset shows images of perforated and wall-modulated nanowires (the width of each image is 1 µm).
Figure 2. (a) Oblique-view SEM image of a cleaved (111)B GaAs wafer anodized for 20 min in a 1 M HNO3 aqueous electrolyte at an applied voltage of 4.0 V with a photolithographic mask (the photoresist mask being removed after anodization). (b) Enlarged image of a GaAs nanowire array produced in the photoresist-free region of the substrate. (c) SEM image of an anodized (100) GaAs substrate illustrating the formation of tilted pores. (d) Top-view SEM image of a porous InP sample anodized with a photoresist mask illustrating the propagation of current-line-oriented pores under the photoresist mask. (e) Cross-sectional SEM view of the porous InP sample showing the bending of “curro” pores under the photoresist mask. (f) Nanowires with modulated walls and internal perforations obtained in a (111)B GaAs substrate at a higher anodizing potential of 4.8 V. The inset shows images of perforated and wall-modulated nanowires (the width of each image is 1 µm).
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Figure 3. (a) SEM image of a GaAs nanowire array produced by anodizing a (111)B-oriented GaAs substrate for 20 min in a 1 M HNO3 aqueous electrolyte under an applied voltage of 4.0 V. (b) SEM image of Ga2O3 nanowires obtained by thermal treatment of the GaAs nanowire array at 900 °C for 60 min in an argon flow containing 3% of oxygen.
Figure 3. (a) SEM image of a GaAs nanowire array produced by anodizing a (111)B-oriented GaAs substrate for 20 min in a 1 M HNO3 aqueous electrolyte under an applied voltage of 4.0 V. (b) SEM image of Ga2O3 nanowires obtained by thermal treatment of the GaAs nanowire array at 900 °C for 60 min in an argon flow containing 3% of oxygen.
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Figure 4. (a) Cross-sectional SEM image of a nanowire array produced on a GaAs substrate after anodization and subsequent TA (900 °C, 1 h), indicating the points where chemical composition were investigated. (b,c) Resulting EDX spectra. The (d) cross-sectional and (e) top views acquired in BSD mode.
Figure 4. (a) Cross-sectional SEM image of a nanowire array produced on a GaAs substrate after anodization and subsequent TA (900 °C, 1 h), indicating the points where chemical composition were investigated. (b,c) Resulting EDX spectra. The (d) cross-sectional and (e) top views acquired in BSD mode.
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Figure 5. XRD pattern of a sample subjected to anodization and thermal treatment at 900 °C for 1 h.
Figure 5. XRD pattern of a sample subjected to anodization and thermal treatment at 900 °C for 1 h.
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Figure 6. Raman scattering spectra of the four samples measured at room temperatures: (1) the initial GaAs substrate, (2) GaAs nanowire array, (3) GaAs nanowire array subjected to thermal annealing at 900 °C for 30 min, and (4) GaAs nanowire array subjected to thermal annealing at 900 °C for 1 h.
Figure 6. Raman scattering spectra of the four samples measured at room temperatures: (1) the initial GaAs substrate, (2) GaAs nanowire array, (3) GaAs nanowire array subjected to thermal annealing at 900 °C for 30 min, and (4) GaAs nanowire array subjected to thermal annealing at 900 °C for 1 h.
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Table 1. Results of the EDX analysis of the chemical composition of GaAs nanowires and substrate subjected to electrochemical etching and thermal treatment. Measurements were performed in the regions indicated in Figure 4a.
Table 1. Results of the EDX analysis of the chemical composition of GaAs nanowires and substrate subjected to electrochemical etching and thermal treatment. Measurements were performed in the regions indicated in Figure 4a.
Measured RegionElementWeight %Atomic %
Spectrum 1O K24.7958.95
Ga K75.2141.05
Spectrum 2O K25.1059.35
Ga K74.9040.65
Spectrum 3O K24.6258.79
Ga K73.0240.00
Spectrum 4Ga K49.9851.78
As L50.0248.22
Table 2. Assignment of the Raman peaks observed in Figure 6 to the Raman modes of the monoclinic Ga2O3 crystal structure [52].
Table 2. Assignment of the Raman peaks observed in Figure 6 to the Raman modes of the monoclinic Ga2O3 crystal structure [52].
Peak Position, cm−1146170201321346416475631655767
Mode assignmentBg(2)Ag(2)Ag(3)Ag(4)Ag(5), Bg(3)Ag(6)Ag(7), Bg(4)Ag(8)Ag(9), Bg(5)Ag(10)
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Monaico, E.I.; Monaico, E.V.; Ursaki, V.V.; Tiginyanu, I.M. Micro- and Nano-Integration in the Production of GaAs and Ga2O3 Nanowire Arrays by Top-Down Design. J. Manuf. Mater. Process. 2025, 9, 376. https://doi.org/10.3390/jmmp9110376

AMA Style

Monaico EI, Monaico EV, Ursaki VV, Tiginyanu IM. Micro- and Nano-Integration in the Production of GaAs and Ga2O3 Nanowire Arrays by Top-Down Design. Journal of Manufacturing and Materials Processing. 2025; 9(11):376. https://doi.org/10.3390/jmmp9110376

Chicago/Turabian Style

Monaico, Elena I., Eduard V. Monaico, Veaceslav V. Ursaki, and Ion M. Tiginyanu. 2025. "Micro- and Nano-Integration in the Production of GaAs and Ga2O3 Nanowire Arrays by Top-Down Design" Journal of Manufacturing and Materials Processing 9, no. 11: 376. https://doi.org/10.3390/jmmp9110376

APA Style

Monaico, E. I., Monaico, E. V., Ursaki, V. V., & Tiginyanu, I. M. (2025). Micro- and Nano-Integration in the Production of GaAs and Ga2O3 Nanowire Arrays by Top-Down Design. Journal of Manufacturing and Materials Processing, 9(11), 376. https://doi.org/10.3390/jmmp9110376

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