BOOLE: Iterative Engineering Design and Prototype Demonstration of a Modular AI-Assisted Electronics Learning Platform

Abstract

BOOLE is a four-face educational platform integrating analog, combinational-logic, and sequential-logic activities with optional AI-assisted component identification and datasheet support. The system was developed through requirements translation, circuit simulation, two-layer PCB design, mechanical review, fabrication, assembly, functional verification, and iterative refinement. A Raspberry Pi 5, Camera Module 3 NoIR, and touchscreen support image capture and local interaction, while an Arduino Mega provides deterministic control of the physical learning faces. Segmented power energizes only the selected face and activity, and removable boards improve maintenance and fault isolation. Hardware demonstrations reproduced the intended voltage-divider, diode threshold/polarity, counter, and sequential-logic states. Ten one-versus-rest classifiers were fine-tuned from a pretrained ViT-Base model using 2000 original photographs, with 200 images for each of ten categories. The dataset was partitioned class-wise into mutually exclusive 80/10/10 training, validation, and final-test sets before augmentation, which was applied only to training data. Final-test accuracy ranged from 91.0% to 99.5%, with precision, recall, F1-score, specificity, balanced accuracy, and confusion matrices also evaluated. A 73-student pilot produced 89–96% positive (Yes) responses across six binary survey items, providing preliminary evidence of learner-perceived effectiveness, engagement, usability, and theory-to-practice support. Overall, BOOLE demonstrates a feasible, serviceable architecture for progressive electronics education.

1. Introduction

Laboratory work is essential to electronics and digital-logic education because it exposes learners to physical components, non-ideal behavior, measurement, and troubleshooting. A comparative review distinguished hands-on, simulated, and remote laboratories and showed that each supports different learning objectives [1]. Inductive and learning-by-doing approaches similarly emphasize predicting, manipulating, observing, and reflecting on a physical system [2]. A recent meta-analysis of virtual laboratories in engineering education found positive effects but concluded that they remain complements rather than complete replacements for hands-on work [3]. The practical challenge is therefore not simply to place more components on a trainer. It is to design a coherent product that guides novice users while remaining manufacturable, safe at educational voltages, maintainable across cohorts, portable, and technically extensible.

A 2018 Pew Research Center finding reported that 52% of surveyed U.S. adults selected perceived subject difficulty as the main reason more young people do not pursue STEM degrees [4]. Figure 1 retains that contextual visualization. The statistic describes public perception rather than measured student performance, so it is used only to frame the accessibility problem addressed by the design.

Related Work and Research Gap

Compact logic trainers and take-home kits establish the value of accessible physical hardware. Ajao et al. implemented a low-cost digital-logic module combining basic, combinational, and sequential functions [5], while Khaing et al. developed a portable Arduino-based gate trainer with selectable inputs and immediate LED feedback [6]. Programme-level take-home kits have emphasized alignment with progressive learning outcomes, inclusivity, and safe independent use [7]. Physical logic blocks can make abstract gate behavior more tangible [8], and a remote digital-electronics laboratory showed how structured access to real equipment can complement simulation [9]. These studies establish the pedagogical value of real or remotely operated hardware, but they generally focus on a bounded experiment set or delivery mode rather than the co-design of the complete product architecture.

Recent portable platforms broaden that comparison. Lab in a Box combined Raspberry Pi-based instrumentation with iterative software performance optimization for remote or hybrid electronics work [10]. WinterLab integrated low-cost measurement functions into a portable experimentation board intended to support independent inquiry [11]. The HELP project documented three generations of an at-home electronics kit and used student and staff feedback to guide technical and pedagogical development [12]. Krismadinata et al. developed a vocational digital-electronics kit through an Analysis–Design–Development–Implementation–Evaluation process and pilot evaluation [13]. Collectively, these studies show that portability, integrated instrumentation, guided experiments, and user feedback are recurring priorities. However, they report different levels of circuit breadth, mechanical integration, maintainability, and verification, which limits direct comparison and leaves room for a traceable system-level design account.

Artificial intelligence (AI) adds a second design opportunity and a second source of risk. A systematic review of AI in science, technology, engineering, and mathematics education described the potential of context-sensitive support while stressing the need for transparent evaluation and a clearly bounded role [14]. Electronic-component vision research has demonstrated high detection or sorting accuracy, but much of it targets industrial inspection and recycling under controlled conditions [15,16]. The recent ElectroCom61 resource extends this field with 61 component classes and images collected across varied lighting, backgrounds, distances, and viewpoints, providing a more demanding basis for external benchmarking [17]. Embedded vision also requires an explicit balance among sensing quality, computing capacity, latency, power, flexibility, and maintainability [18]. Educational work has used mobile augmented reality to recognize and explain electronic components [19], while a recent mobile system combined optical character recognition, resistor color decoding, component classification, and datasheet retrieval for educational support [20]. These studies strengthen the case for recognition-assisted learning, but they also show why capture conditions, evaluation splits, network dependence, and the handoff from predicted class to trustworthy documentation must be reported explicitly. YOLOv4-tiny was reviewed in the project literature review as a real-time electronic-component detection approach [16]. The deployed BOOLE AI face uses a transfer-learning classification pipeline comprising ten one-versus-rest binary classifiers fine-tuned from the pretrained zjbrammer/ElectricComponentDetect ViT-Base model, as detailed in Section 2.7.1.

An engineering-design account also requires iteration to be observable rather than merely asserted. Rees Lewis et al. characterize expert iteration as coupled revisions across problem framing, prototypes, and stakeholder evidence [21]. Comparative prototyping research further shows that sequential refinement is common but is not the only useful strategy; parallel concepts can improve early exploration of a complex design space [22,23]. BOOLE therefore used a hybrid logic: controllers, cameras, displays, and PCB toolchains were screened as alternatives early, after which the selected architecture was refined through repeated simulation, schematic, layout, mechanical, fabrication, bring-up, and integration loops. Each loop produced evidence, a documented change when necessary, and reverification of the affected requirement.

BOOLE was conceived to address this combined design problem. The name honors George Boole, whose Boolean algebra provides the formal basis of digital logic; BOOLE is a product name rather than an acronym. The system is a self-contained cube with three removable learning faces—analog electronics, combinational logic, and sequential logic—and a fourth AI/user-interface face. The contribution is not a new circuit topology or classifier. It is a system-level design case organized around three transferable ideas: physical embodiment of curricular progression, bounded AI assistance that remains optional to hands-on activity, and modularity for maintenance and fault containment. These ideas are evaluated against named portable learning platforms in Section 4.4 using explicit design and evidence criteria.

The contributions are threefold. First, the work presents a requirements-to-verification trace for a multidisciplinary educational product. Second, it documents a modular electrical and mechanical architecture that separates replaceable learning PCBs from the AI/user-interface subsystem while coordinating power and I/O. Third, it reports a transparent prototype-demonstration record comprising quantified circuit-level functional checks, the documented component-classification evaluation, integrated operation, and a preliminary learner-perceived-effectiveness study. The research question is: how can a progressive electronics learning platform be embodied as a portable and maintainable prototype without allowing the AI subsystem to displace the physical learning objective?

2. Materials and Methods

2.1. Iterative Design Strategy

The development process followed a staged but explicitly iterative engineering-design workflow, consistent with systematic movement from task clarification and conceptual design to embodiment, detail design, and verification [24]. Figure 2 summarizes the six stages. A stage was not considered complete merely because a document or model existed; evidence from a later stage could reopen an earlier requirement, architecture, or embodiment decision.

Each loop followed an evidence → decision → revision → reverification pattern. Computing and interface evidence changed the initial Raspberry Pi 4 concept to a Raspberry Pi 5 (Raspberry Pi Ltd., Cambridge, UK), while retaining the Arduino Mega (Arduino S.r.l., Monza, Italy) for deterministic I/O; tool and library availability changed the PCB workflow from the candidate KiCad route to OrCAD/Allegro; DRC and three-dimensional review revised routing, footprint, and clearance decisions; board bring-up triggered localized solder rework and repeated module tests; and integration review added enclosure ventilation while confirming segmented power and subsystem boundaries.

2.2. Requirements, Constraints, and Traceability

Needs gathered from the educational context were translated into engineering characteristics using a quality-function-deployment (QFD) logic [25]. The original QFD ranked reliable feedback most strongly, followed by durability and learning support. For the journal-focused redesign, these needs were consolidated into the traceability matrix in

Table 1. Design requirements, constraints, implemented responses, and verification evidence.

ID	Design Requirement	Principal Constraint/Driver	Implemented Response	Verification Evidence
R1	Progressive topic coverage	Novice cognitive load; finite panel area	Separate analog, combinational, and sequential faces with ordered activities	Implemented-circuit inventory; complete face operation
R2	Immediate and interpretable feedback	Minimal external instruments	LEDs, counters, seven-segment displays, adjustable inputs, and selected waveform outputs	Truth-state and analog-behavior checks
R3	Portable, self-contained operation	Classroom transport and desk use	Four-face cube containing PCBs, display, camera, controllers, and wiring	Integrated prototype assembly
R4	Maintainability and modularity	Repeated cohort use; localized faults	Removable PCB panels, headers, labeled signals, replaceable components, and separable AI subsystem	Module-level bring-up and replacement access
R5	Controlled power and low idle consumption	Three learning PCBs share a source	Master face switches plus per-circuit shunt jumpers; only selected circuits are energized	Selective-power functional test
R6	Manufacturable PCB realization	Panel density; footprint availability; two-layer fabrication	OrCAD schematics, Allegro constraint-driven placement/routing, ground plane, vias, DRC, Gerber and drill outputs	DRC closure, 3D fit review, fabrication and assembly
R7	Accessible component information	Marking size; changing part inventory; intermittent network	Camera-based class recognition, part-number extraction, editable result, and local datasheet repository	Class-wise validation and end-to-end UI tests
R8	Safe educational interaction	Novice users and exposed controls	Low-voltage circuits, current-limiting resistors, isolated active modules, enclosure retention, ventilation, and documented operation	Visual inspection and powered functional testing
R9	Scalability	Future mixed-signal and programmable-logic content	Face-level interfaces and replaceable panels; software layers separated by function	Architecture review and defined expansion interfaces

DRC: design rule check. The project was designed with reference to relevant safety and quality principles, but no claim of product certification is made.

. The matrix distinguishes a requirement from the implementation selected to satisfy it and from the evidence used to evaluate it. This distinction prevents descriptive features—for example, the use of a Raspberry Pi—from being presented as requirements in themselves.

Constraints were grouped into technical, economic, temporal, ethical, and operational categories. Technically, components from different families had to coexist at appropriate voltage and signal levels, dense educational content had to fit on the panels, and the camera/display had to operate within a compact enclosure. Economically, components needed to be obtainable through common suppliers, and failures needed to be repairable without replacing the full product. Temporally, the design had to progress from concept to a demonstrable prototype within an academic project cycle. Ethically, the product had to preserve learner agency, avoid presenting AI predictions as guaranteed facts, and protect participant data in the pilot evaluation. Operationally, the user needed to understand which face and circuit were energized and to obtain a result with limited instructor intervention.

2.3. Modular System Architecture

The final architecture uses functional decomposition to prevent a failure in one subsystem from disabling the entire learning sequence. Figure 3 distinguishes the power, data, network, and controller-coordination paths, while

Table 2. Activity-level allocation of physical behavior, controller measurement, software calculation, and learner-facing output.

Face	Activity	Physical Behavior/Path	Controller Measurement	Software Calculation	Learner Display
Face 1	Voltage divider	Resistor network at 5 V with R1 = 10 kΩ and selectable R2	ADC input represents the selected divider state	Maps the selected state to nominal 1.67, 2.50, or 3.33 V	Labeled voltage LED
Face 1	RC charge/discharge	Switched 5 V RC reference topology; selected capacitance is represented in the control input	Reads switch and selection state	Applies the documented 5τ timing rule; for 5 mF and 200 Ω, τ = 1 s	LED persistence; analytical reference in Section 3.2
Face 1	Diode polarity/threshold	Adjustable input and two indicator branches	Reads the selected input/polarity state	Applies the activity threshold/polarity logic	Mutually exclusive half-cycle LEDs
Face 1	Full-wave rectifier	Complete bridge-and-smoothing reference is simulated; the learning PCB uses controller-driven indicators	Reads the selected input/capacitance setting	Represents conduction path and ripple trend	Bridge-path LEDs and smoothing indicator
Face 1	Transistor switch	Adjustable base-control input and output indicator	Reads the control voltage	Applies the switching threshold	Output LED
Face 1	Transistor amplifier	Transistor topology is instructional; the implemented response is controller-assisted	Reads an amplitude-control input	Maps input level to the demonstrator output	Buzzer/output indication
Face 2	AND/OR/NOT/XOR gates	Discrete transistor/logic networks with manual inputs	Direct hardware path; controller mediation is unnecessary	Truth function is realized by the physical logic network	Direct LED truth state
Face 2	MUX/comparator/adder	Logic ICs and manual binary inputs	Direct hardware path; controller mediation is unnecessary	Selection, comparison, and addition are realized by the logic ICs	LED and/or seven-segment result
Face 2	Counter	Counter/decoder hardware with manual clock/control	Controller support configures activity inputs	Counter/decoder hardware generates the binary and BCD response	Four-bit LEDs and BCD display/blanking
Face 3	Clock divider	Two cascaded 74,175 stages configured as toggles	Arduino provides the adjustable base clock/control settings	Hardware stages produce the F/2 and F/4 outputs	Clock-state LEDs
Face 3	D flip-flop and shift register	Physical flip-flop/register ICs with manual control and staged outputs	Stored-state propagation follows the direct hardware path	Decoder support converts the staged binary state for display	Q/state LEDs and seven-segment display
Face 4	Component-to-datasheet support	Camera captures the physical component	Pi receives the image; no learning-face electrical quantity is measured	ViT classification; cloud part-number extraction; local PDF filename matching	Ranked class score, editable part number, and datasheet PDF

maps each activity to the physical behavior, controller measurement, software calculation, and learner-facing output. The Raspberry Pi 5 hosts the on-device component classifiers, camera control, Streamlit interface, and local datasheet index in the 3.3 V logic domain. The Camera Module 3 NoIR connects by CSI; the touchscreen receives HDMI video and returns USB touch data. Printed part-number extraction is the only network-dependent stage and uses the Gemini 2.0 Flash vision-language API. The Arduino Mega supplies deterministic 5 V ADC, PWM, and digital I/O to the learning faces. Each face receives power through a master switch, after which a circuit shunt enables only the selected activity. For reproducible controller coordination, the revised interface specification defines request–acknowledge messages (FACE_SELECT, ACTIVITY_SELECT, READ_STATE, STATE, ACK, and ERROR), a sequence field and checksum, a 500 ms acknowledgement window, one retry, and transition to a de-energized safe state after a failed exchange. The three physical learning faces and the fourth AI/user-interface face are functionally independent: no analog, combinational, or sequential activity requires AI inference or cloud access, and the AI face is used only for optional component identification, part-number assistance, and datasheet support.

The corresponding learner interaction sequence is retained from the original manuscript in Figure 4. It shows how a session progresses from power-up and circuit selection through observation, correction, assessment, and level advancement, while the AI face remains available as an optional support path.

2.4. Component-Selection Iterations and Trade-Offs

2.4.1. Computing Platform

The first concept comparison considered a PIC18F45K22, Arduino Mega, and Raspberry Pi 4. The PIC offered low cost and deterministic control but insufficient memory and software support for the vision workload. The Arduino Mega provided abundant 5 V I/O and a familiar educational ecosystem, but it could not host the classification and graphical interface. The Raspberry Pi 4 therefore became the initial high-level computing candidate. During implementation, the architecture was revised to use both an Arduino Mega and a Raspberry Pi rather than forcing one platform to perform both roles. The final AI face adopted a Raspberry Pi 5, while the Arduino retained deterministic board-level I/O. This partition increased component count, but reduced level-shifting complexity, separated real-time educational control from the Linux application, and preserved a clear replacement boundary.

2.4.2. Camera and Display

Candidates for the camera were assessed on criteria of resolution, autofocus capability, interface, field of view, effort required for integration, and cost. Candidates were ruled out based on lack of resolution capability, lack of autofocus capability, the fact that the small markings on components require the camera to be focused at different distances, lack of native camera-stack integration, and cost. A 16 megapixel third-party autofocus camera gave enough resolution capacity but increased the integration risk due to high driver risk. A USB webcam had more general-purpose ports but lacked native camera-stack integration. The Sony IMX708 Camera Module 3 NoIR (Sony Semiconductor Solutions Corporation, Atsugi, Japan) was chosen due to its autofocus capability, 12 megapixel capability, native CSI interface, and small form-factor. The final design used resolution 1920 × 1080 with Picamera2 with autofocus and automatic white balance.

Candidate displays ranged from small displays at 800 × 480 to a portable monitor at 1920 × 1080. Display candidates considered factors of direct touch interaction, enclosure fitment, compatibility, and cost but not desktop class resolution. A HDMI display is used, which uses HDMI for video input and USB for touch inputs. This decision contrasts with the initially proposed DSI display but reduces the driver uncertainty and allows the easy panel mount interface for the final enclosure. This iteration exemplifies an important principle of the design process; candidates for component selection tables help shape concepts, but the actual candidate used can be allowed to change based on evidence of integration difficulty.

2.4.3. PCB Toolchain

KiCad, Altium Designer, EasyEDA, and Flux were initially compared. KiCad ranked strongly because it is free, cross-platform, and includes schematic, layout, and three-dimensional viewing. The embodiment phase nevertheless migrated to OrCAD Capture 23.1 and Allegro PCB Designer 23.1 after compatible component libraries and industrial design support became available through Multilane Inc. (Houmal, Lebanon). OrCAD-to-Allegro netlist transfer reduced manual connectivity errors; Allegro provided constraint-driven routing, footprint and courtyard control, real-time DRC, copper-plane handling, and three-dimensional mechanical review. The change increased tool cost in a general deployment, but reduced implementation risk within the available collaboration. For replication in a cost-constrained institution, the same schematics and board constraints could be migrated to an open-source toolchain.

2.5. Circuit, Schematic, and PCB Development

2.5.1. Progressive Circuit Selection

Circuit selection was driven by prerequisite order and observable behavior. Face 1 begins with passive voltage division and energy storage before introducing rectification and transistor operation. Face 2 exposes Boolean operations with manually controlled inputs, then combines those concepts in multiplexing, comparison, addition, and counting. Face 3 introduces time and state through clock division, flip-flops, and cascaded register stages. The aim was not to maximize the number of circuits. It was to fit a coherent sequence in which each panel has a visible input, a manipulable parameter or state, and an Immediate output.

2.5.2. Simulation and Schematic Capture

Each circuit was first evaluated in Proteus before schematic capture, PCB layout, fabrication, or assembly. For analog activities, the simulation checked voltage relationships, diode conduction states, rectifier action, transistor switching or amplification, and the expected exponential response of the RC activity. For digital activities, all defined input combinations, truth states, counter sequences, and clocked transitions were checked. These simulation results established the expected state or threshold for each activity before prototyping: for example, the voltage-divider targets were 1.67, 2.50, and 3.33 V; the 5 mF, 200 Ω RC reference gave τ = 1.0 s and 5τ = 5.0 s; and logic activities were required to reproduce their complete truth/state sequences. Only after this review were the validated circuits recaptured in OrCAD as three independent face schematics. Standard library symbols were used where possible; missing symbols and footprints were constructed from supplier datasheets. Each face included a global supply path, per-circuit enable jumpers, signal headers, current-limiting elements, and labeled nets. This simulation-first gate reduced implementation risk and provided a pre-established reference against which the later visual and powered prototype states could be checked.

2.5.3. Layout and Manufacturability Decisions

The three faces were made with a two-layer FR-4 PCB technology. Component arrangement conformed to the print learning layout and not just the shortest-net layout; for example, the control and indicator were lined up according to the silkscreen diagram, whereas connectors stayed at the panel edge to remain accessible. Courtyard clearance and polarity/orientation were checked before routing. In the case where a one-layer routing produced congestion, vias were incorporated, while a copper ground plane was used to create common return paths as well as minimize long ground traces. The top and bottom silkscreen layers carried circuit boundaries, reference designators, connector labels, Arduino pin numbers, and instructional markings.

Iterative Allegro DRC was used to detect the violations related to spacing, trace width, via size, and component placement. A 3D layout was later reviewed to check the components’ height, access of controls, and alignment with the enclosure. Outputs of the Gerber file, drill, and bill-of-materials (BOM) were only created after both the electrical and mechanical reviews were complete. The boards were manufactured, populated manually, visually inspected, and powered individually per each module. Power-up showed solder bridge or poor joints, which were corrected before conducting tests. Assembly feedback was used as the design result since it exposed issues relating to accessibility and serviceability, which were impossible to detect through simulation.

Figure 5, Figure 6 and Figure 7 consolidate the design evidence by learning face. Each figure pairs the user-facing layout, routing view, and a readable representative schematic so that circuit identity, board embodiment, and the physical/software boundary can be checked together.

2.6. Mechanical Enclosure and Serviceability

The enclosure converts three large trainer boards and an AI interface into a single transportable product. A custom 3D-printed frame holds each PCB as a face, provides dedicated positions for the display and camera, protects wiring, and keeps controls accessible. The face-level construction allows one board to be removed for repair or replacement without discarding the remaining system. Mechanical review added an opening at the top of the cube for airflow around the Raspberry Pi, display electronics, and internal wiring. Fasteners and edge supports restrain the panels during handling. The enclosure is therefore not cosmetic packaging; it is the element that realizes portability, alignment, ventilation, and service access. Figure 8 shows the resulting assembled cube and the four face-level interfaces.

2.7. AI and User-Interface Co-Design

Figure 9 separates sensing, classification, text extraction, datasheet retrieval, and touchscreen presentation so that each software function can be revised without changing the learning-face hardware.

2.7.1. Classification Pipeline

The component-recognition subsystem was organized as replaceable software modules for data preparation, component classification, part-number extraction, datasheet retrieval, and user interaction. The classification experiment comprised the ten component categories reported in Section 3.4: seven-segment display, capacitor, diode, graphical LCD (GLCD), integrated circuit (IC), LED, potentiometer, relay, resistor, and transistor. The classifier dataset comprised 2000 original photographs, 200 for each category, so the classes are balanced by construction. Original images were organized by class and partitioned using a fixed random seed of 42 into mutually exclusive training, validation, and final-test sets in an 80/10/10 ratio, giving 160 training, 20 validation, and 20 final-test photographs per category. Partitioning was completed before augmentation to prevent transformed versions of the same source image from appearing in more than one partition. Rotations, horizontal and vertical flips, brightness and gamma adjustments, Gaussian noise, and Gaussian blur were applied only to the training partition, producing three augmented variants per training photograph and 640 training images per class. Validation and final-test images were not augmented.

Partitioning was performed at the image-file level before augmentation, and augmented derivatives were generated only within the training partition. However, the dataset did not include a verified unique identifier linking every photograph to its underlying physical component specimen or acquisition session. Different photographs of the same specimen may therefore have been assigned to different partitions. The current evaluation consequently measures performance on held-out image files but cannot be interpreted as a specimen-independent or acquisition-session-independent evaluation.

Each component category was formulated as a one-versus-rest binary classification task using transfer learning from the pretrained zjbrammer/ElectricComponentDetect Vision Transformer (ViT-Base: 12 encoder layers, 768 hidden units, 12 attention heads, and 16 × 16 pixel patches) [26]. This ViT-Base transfer-learning architecture is the component-classification algorithm deployed on the BOOLE AI face. Each model was trained for five epochs using the Hugging Face Trainer API. Class-weighted cross-entropy loss was used during training to reduce the effect of the imbalance between the target category and the combined negative categories. Epoch-wise evaluation was performed on the validation partition, and the checkpoint with the highest validation balanced accuracy was selected as the final model. The selected checkpoint was then evaluated once on the untouched final-test partition. For each one-versus-rest classifier, the final-test set contained 20 positive images from the target category and 180 negative images from the remaining nine categories. Final performance was evaluated using accuracy, precision, recall, F1-score, specificity, balanced accuracy, and a binary confusion matrix. Per-image predictions, reference labels, and model scores were recorded for error analysis. Because accuracy can be inflated by the larger negative class, F1-score and balanced accuracy were treated as essential complementary measures. At inference the ten classifiers are evaluated independently, and the category with the highest positive score is displayed, with the next two shown as alternatives; the multiclass confusion matrix uses this same decision rule. The deployed Raspberry Pi 5 system was additionally exercised through qualitative deployment demonstrations using physical components presented under informally varied lighting, background, orientation, distance, and appearance conditions. These demonstrations were not used to calculate classifier performance and are not interpreted as an independent external-validation experiment.

2.7.2. Part Number and Datasheet Workflow

After component-class prediction, the captured image is submitted through a Pydantic AI agent to the Gemini 2.0 Flash vision-language API, configured with a temperature of 0.2, to produce a structured part-number response and an associated model-generated confidence value. The displayed classifier confidence is an instance-specific model score used to communicate ranking/uncertainty; it is not treated as a calibrated probability of correctness or as an external accuracy estimate. Cloud-assisted part-number extraction requires an active network connection and transmits the captured component image to a third-party service. Deployments should therefore record the service, model revision, and access date, and should process only non-sensitive component images in accordance with applicable institutional privacy and network policies. The user confirms or corrects the extracted string before searching. Datasheet retrieval then checks a local directory whose PDF filenames contain normalized part numbers; exact and substring matching permit offline retrieval for cached components. The classifier and local PDF lookup remain available without the cloud service, whereas new cloud-based part-number extraction requires the network.

A multi-page Streamlit application exposes the workflow on the touchscreen. The component-analysis page captures an image, shows the top class predictions, displays the extracted part number, permits correction, and provides a datasheet link when a local match is found. Session state prevents unnecessary model reloads. The editable part-number field and local datasheet cache are deliberate human-in-the-loop controls: the learner can compare the physical marking with the extracted string, correct it when necessary, and then open the cached manufacturer document. The AI/user-interface face is intentionally separate from all three learning faces; each physical face remains fully usable if the classifier, cloud service, camera, or network is unavailable.

2.8. Verification Protocol

Evidence provenance and scope. The reported evidence comprises final schematics/layouts and summary tables from the BOOLE project report, embedded prototype photographs and interface screenshots, the component-classification results reported in Section 3.4, and aggregate percentages from the 73-participant pilot. The manuscript distinguishes theoretical references, simulations, powered functional checks, classification results, end-to-end component-information workflow tests, and learner-perception results. Section 3.2 and Section 3.4 summarize the verification evidence and the additional measurements recommended for a broader independent evaluation.

2.8.1. Circuit and PCB Verification

Verification proceeded from simulation to implementation rather than from assembly photographs alone. Before PCB release, every circuit was simulated, and its expected voltage relationship, threshold state, truth state, count sequence, or timing behavior was recorded. After assembly, each face was first inspected without power for polarity, orientation, solder bridges, and connector continuity. A face was then connected to the 5 V source, its master switch enabled, and one circuit at a time activated through its shunt. Controlled inputs were exercised across every defined state, and the visible outputs were compared with the pre-established theoretical or simulated reference. The acceptance rule for the present prototype demonstration was state agreement: all expected LEDs, display codes, polarity states, count states, and sequential states had to match the reference before the module was accepted. Any mismatch triggered localized rework and repetition of that module before integration. Section 3.2 therefore distinguishes the state-based functional verification completed in the present study from the calibrated electrical and timing measurements specified for a future instrumented campaign.

2.8.2. AI and Complete-System Verification

The component-classification pipeline used the same ten predefined categories throughout dataset preparation, model training, and evaluation. Original images were partitioned class-wise into 80% training, 10% validation, and 10% final-test sets before augmentation, and augmentation was restricted to the training partition. The validation partition was used for epoch-wise model selection, with balanced accuracy used to select the best checkpoint. The untouched final-test partition was used only after model selection. For each one-versus-rest classifier, this partition contained 20 positive and 180 negative images. Final evaluation included accuracy, precision, recall, F1-score, specificity, balanced accuracy, and confusion counts. Following the internal classifier evaluation, physical components were processed through the deployed Camera Module 3 NoIR and Raspberry Pi 5 interface to demonstrate the complete operational sequence: image capture, component classification, cloud-assisted part-number extraction, user confirmation or correction, local PDF retrieval, and touchscreen display. Component presentation was varied informally with respect to lighting, background, orientation, distance, and appearance. These trials were intended to demonstrate integrated operation rather than estimate generalization performance: they did not use a prospectively defined sampling protocol, a separately collected external dataset, or predefined stage-specific performance measures. They are therefore reported as qualitative deployment demonstrations and not as independent external validation.

2.8.3. Pilot User Evaluation

A pilot perception study involved 73 undergraduate engineering students after guided laboratory use of BOOLE. The participants were junior- and senior-year students aged 19–21 years. The pilot was approved by the University of Balamand Institutional Review Board (approval No. UOB/IRB/2025/002), and informed consent was obtained from all participants. The survey was voluntary and anonymous and did not collect personal data, identifiers, tracking information, or demographic information from individual respondents. The pilot questionnaire comprised six author-developed binary Yes/No items. Each item was presented as a positively worded statement, with a Yes response indicating affirmative endorsement of that statement. The six items were constructed specifically for this descriptive pilot to address perceived conceptual understanding, engagement, theory-to-practice connection, usability, preference relative to conventional laboratories, and willingness to recommend BOOLE. The questionnaire was designed to provide concise post-use perception feedback. During the guided activity, students selected a face and activity, manipulated the available inputs and controls, observed the corresponding LEDs, displays, or waveform-related feedback, progressed through the guided interaction sequence, and could use the AI face as optional component-identification and datasheet support. Results are reported as the percentage of participants selecting Yes or No for each item and are interpreted only as learner-perceived effectiveness and acceptance, not as objective learning gains. Future evaluation will prospectively collect broader participant demographic and academic-background information, including age, gender, year of study, prior academic achievement, and baseline electronics/logic knowledge, together with standardized documentation of BOOLE exposure duration and learning activities, as detailed in Section 4.5.

3. Results

3.1. Design Iterations and Resulting Architecture

The principal result is not a single component choice but convergence from a broad educational concept to a traceable product architecture.

Table 3. Major iterations, triggers, design changes, and engineering effects.

Iteration	Trigger/Evidence	Implemented Change	Engineering Effect
Compute platform	AI, camera, and touch UI exceeded microcontroller capability	Initial Raspberry Pi 4 concept updated to Raspberry Pi 5; Arduino retained for deterministic 5 V I/O	Separated application computing from circuit control and simplified learning-face interfaces
PCB toolchain	Industrial libraries, review, and fabrication support became available	Candidate KiCad workflow replaced by OrCAD Capture plus Allegro PCB Designer	Reduced netlist/footprint transfer risk and enabled constraint-driven DRC and 3D review
Power architecture	Three dense PCBs created idle-load and fault-isolation concerns	Master switch per face plus shunt enable per circuit	Only the selected module is energized; troubleshooting is localized
Panel embodiment	Board density and novice navigation competed for area	Activity boundaries, signal labels, and control/output alignment added to silkscreen	The PCB itself became an instructional map without obscuring service labels
Enclosure	Integrated electronics required protection and cooling	3D-printed cube with restrained removable panels and top ventilation opening	Improved portability, alignment, access, and thermal airflow
AI workflow	Class labels alone did not support bench decisions	Added structured part-number extraction, user correction, and local PDF lookup	Connected recognition to actionable specifications while keeping uncertainty visible
Board bring-up	Visual and powered checks revealed assembly defects	Localized solder rework followed by repeated module tests	Converted a non-working joint into documented assembly feedback before integration

records the most consequential iterations. The changes show that portability, maintenance, and integration were treated as design variables rather than claims added after fabrication. In particular, the dual-controller architecture resolved the conflict between high-level AI/UI processing and stable 5 V educational I/O; the OrCAD/Allegro transition reduced PCB implementation risk; and segmented power preserved both energy control and fault isolation.

3.2. Simulation-to-Hardware Realization

Figure 10 consolidates representative pre-fabrication evidence at a larger readable scale. Figure 10a gives the complete switched RC reference topology for the three documented capacitance selections; Figure 10b gives the analytical 5 mF, 200 Ω, 5 V charging/discharging reference (tau = RC = 1.0 s; 5τ = 5.0 s); and Figure 10c shows the transistor-based AND-gate simulation with both inputs HIGH. These references were established before PCB prototyping and were used as expected-behavior targets during bring-up. They verify the design logic and thresholds used for functional comparison but are not presented as calibrated measured waveforms.

The fabricated boards preserved the intended grouping and control placement shown in Figure 5, Figure 6 and Figure 7. Following localized assembly rework, all modules reached their intended observable functional states.

Table 4. Functional-verification results from the present prototype study and predefined criteria for future instrumented validation.

Face	Activity Family	Reference/Programmed Criterion	Functional Result	Predefined Criterion for Future Instrumented Validation
1	Voltage divider	Vin = 5 V; R1 = 10 kΩ; Vout = 1.67, 2.50, 3.33 V for R2 = 5, 10, 20 kΩ	3/3 expected indicator states obtained (labels: 1.66, 2.50, 3.33 V)	Confirm with calibrated Vout within ±5% over 10 repeated selections/state
1	RC activity	C = 5 mF; R = 200 Ω; τ = 1.0 s; 5τ = 5.0 s	2/2 modes showed the intended rise/decay trend and LED persistence	Fit measured τ within ±10% and repeat 10 charge/discharge cycles
1	Diode/polarity	Input states 0.7, 1.8, and 2.5 V plus reversed polarity	4/4 programmed indicator states matched the threshold/polarity logic	Confirm forward drop/current and repeat each state 10 times
1	Full-wave activity	Four-diode bridge reference with selectable smoothing capacitance	Bridge-conduction and smoothing-indicator sequence completed	Measure ripple before/after smoothing; target reduction ≥ 50% at fixed load
1	Transistor switch/amplifier	Programmed threshold and amplitude-response states	2/2 activity modes produced the intended LED/buzzer response	Measure switch saturation and amplifier gain over 10 repeated input sweeps
2	Logic gates	AND, OR, XOR: 4 states each; NOT: 2 states (14 total)	14/14 truth-table states produced the required LED output	Repeat the 14-state matrix three times and record propagation delay
2	MUX/comparator/adder	Complete defined selection, comparison, and binary-sum state matrices	Every applied state produced the selected path, relation, or binary output	Repeat each complete matrix three times with zero state errors
2	Counter/display	16 binary states; BCD display valid for 0–9 and blank for 10–15	16/16 counter states and 10/10 valid BCD symbols followed the defined sequence	Run 10 full cycles with zero missed counts and measure maximum clock rate
3	Clock divider	Two hardware ratios: F/2 and F/4	2/2 divider outputs followed the documented sequence	Confirm ratios within ±1% and duty cycle 50% ± 5% over 10 periods
3	D flip-flop/register	Preset/clear state table and staged binary propagation	Defined Q/state and decoded-display sequence completed	Repeat the full sequence 10 times and record setup/hold and propagation timing

separates the evidence obtained in the present study from the measurements reserved for subsequent validation. The “Functional result” column reports the state-based outcomes observed during prototype testing, whereas the final column defines the calibrated electrical, timing, and repeatability criteria to be applied in a future instrumented campaign. Accordingly, the present results establish functional agreement with the theoretical or programmed behavior but do not constitute calibrated measurement of voltage, current, ripple, gain, propagation delay, frequency, duty cycle, or repeatability.

Figure 11, Figure 12, Figure 13 and Figure 14 consolidate the powered-hardware evidence: selective power activation, representative analog states, and representative digital states. The procedure remained: enable one face, insert the selected shunt, apply controlled inputs, compare the visible response with the reference state, and de-energize the circuit before moving on.

Figure 11 documents the two-stage enable sequence used during bring-up. The master control first energized one learning face; the removable shunt then connected only the circuit under test. Repeating the same sequence on the analog and sequential faces demonstrates that selective power was an implemented modular interface rather than a face-specific workaround. It limited fault exposure and allowed each repaired circuit to be retested before the next module was enabled.

For the unloaded divider, Vout = VinR2/(R1 + R2). With Vin = 5 V and R1 = 10 kΩ, the theoretical outputs are 1.67, 2.50, and 3.33 V for R2 = 5, 10, and 20 kΩ, respectively. Figure 12a–c show the corresponding powered indicator states. The one-to-one match across all three selections verifies the functional path from manual selection through controller decision to visible feedback; Table 4 separately defines the calibrated ±5% node-voltage criterion for quantitative confirmation.

Figure 13a,b verify that the lower 0.7 V and 1.8 V input states remain below the programmed combined threshold, while Figure 13c,d shows opposite indicators for the positive and negative 2.5 V half-cycles. Thus all four defined visual states matched the pre-established polarity/threshold logic. This is functional verification of the implemented educational state logic; Table 4 defines the follow-up forward-drop/current measurement and 10-repeat criterion.

The four illuminated counter LEDs in Figure 14a represent binary 1111 (decimal 15). The blank seven-segment display is expected because 1111 lies outside the 0000–1001 BCD range. Figure 14b extends the evidence to state storage, while Figure 14c shows staged register outputs 0000 decoded as 0. These states were documented after localized soldering faults had been corrected and the affected circuits retested; Table 4 defines the repeated-cycle and propagation-timing criteria for quantitative follow-up validation.

3.3. PCB, Enclosure, and Complete-System Integration

Through the fabrication and assembly, it was proved possible to fabricate three densely labeled educational panels through the two-layer technique and then mount the boards in one frame. The use of common rails with the use of per-circuit jumpers allowed us to power up each face sequentially. It means that an error in one of the modules will not require powering up all faces of the cube. Top and bottom labeling of the board helped with connector positioning during assembly. The three-dimensional testing kept accessibility of slide switches, potentiometers, push-buttons, headers, LEDs and seven-segment displays. The final cube worked with each face separately and with the camera/display subsystem working. The enclosure helped keep panel positions in order, protected internal wiring, and made sure that learning controls were accessible. Disconnecting a shunt from the rail disabled power on the corresponding face, while choosing a face disabled power supply on its board level. Additional opening on the top provided passive airflow path for the cube. There was no cross-coupling failure detected during functional integration tests.

Figure 15 consolidates fabrication and assembly evidence from the project report. The first row shows the three fabricated boards before component population; the second row shows the corresponding faces after population and enclosure mounting. This closes the design loop from layout release to physical realization and makes the face-level maintenance boundary visible.

3.4. AI Validation and End-to-End Operation

Table 5. Final performance of the ten one-versus-rest ViT-Base classifiers on the untouched final-test partition.

Component Category	Accuracy (%)	Precision (%)	Recall (%)	F1-Score (%)	Balanced Accuracy (%)
7-segment display	97.5	100.0	75.0	85.7	87.5
Capacitor	96.0	80.0	80.0	80.0	88.9
Diode	95.0	81.3	65.0	72.2	81.7
Graphical LCD (GLCD)	99.5	100.0	95.0	97.4	97.5
Integrated circuit (IC)	98.0	90.0	90.0	90.0	94.4
LED	96.5	78.3	90.0	83.7	93.6
Potentiometer	96.0	73.1	95.0	82.6	95.6
Relay	97.0	85.0	85.0	85.0	91.7
Resistor	98.5	100.0	85.0	91.9	92.5
Transistor	91.0	54.2	65.0	59.1	79.4

reports the final performance of the ten one-versus-rest classifiers on the untouched final-test partitions. Accuracy ranged from 91.0% for the transistor classifier to 99.5% for the GLCD classifier. Accuracy was consistently influenced by the predominance of negative examples in each binary test set, so the class-specific precision, recall, F1-score, and balanced-accuracy results provide a more informative assessment of target-category recognition. The GLCD classifier produced the strongest overall result, with 99.5% accuracy, 97.4% F1-score, and 97.5% balanced accuracy. The transistor classifier produced the weakest target-class result, with 54.2% precision, 65.0% recall, 59.1% F1-score, and 79.4% balanced accuracy. The diode classifier also showed reduced positive-class sensitivity, with 65.0% recall and 72.2% F1-score despite an overall accuracy of 95.0%. These findings demonstrate that accuracy alone does not adequately characterize classifier performance. The lower transistor and diode results identify these categories as priorities for additional data collection, specimen-level separation, and error analysis. The results therefore support internal performance on held-out image files. Because the partitioning procedure did not enforce grouping by physical specimen or acquisition session, they do not establish generalization to previously unseen specimens, acquisition sessions, cameras, users, or operating environments.

The revised component-classification procedure uses one consistent ten-category definition and a class-wise 80/10/10 training, validation, and final-test split performed before augmentation. Each binary final-test set contained 20 positive images from the target category and 180 negative images from the remaining categories, so accuracy should be interpreted together with positive-class F1-score and balanced accuracy.

Table 6. Component-recognition and datasheet-workflow evaluation.

Workflow Stage	Evaluation Basis	Reported Result	Additional Robustness/Benchmark Measure
Component classification	Ten predefined component categories; 2000 original photographs (200 per category); class-wise 80/10/10 training, validation, and final-test split performed before augmentation; augmentation restricted to the training partition.	Ten one-versus-rest ViT-Base classifiers evaluated on untouched final-test data (20 positive and 180 negative images per classifier). Accuracy ranged from 91.0% to 99.5%, precision from 54.2% to 100.0%, recall from 65.0% to 95.0%, F1-score from 59.1% to 97.4%, and balanced accuracy from 79.4% to 97.5%.	Balanced accuracy and binary confusion matrices are included in the present evaluation. Future external testing should use new physical specimens and acquisition sessions with prospectively controlled lighting, background, orientation, distance, camera, and operator conditions.
Part-number extraction	Physical component images from the deployed interface	Structured part-number extraction demonstrated with editable user confirmation.	Evaluate exact-string success across additional marked components and document blur, glare, occlusion, and orientation cases.
Datasheet retrieval	Local part-number matching and PDF display	Local datasheet lookup demonstrated in the deployed workflow.	Report correct-PDF retrieval rate across a broader cached component library.
Human correction	Editable part-number confirmation and re-query path	User correction is available before datasheet retrieval.	Record correction-to-correct-PDF recovery when the extracted part number is inaccurate.
Pi 5 end-to-end workflow	Camera -> class -> part number -> confirmation -> lookup -> display	All six functional stages were demonstrated on the Raspberry Pi 5 interface. Design-level benchmark: approximately 7 s end-to-end under stable Wi-Fi (about 2 s capture/local ViT-Base classification, 4 s cloud part-number extraction, and 1 s local lookup/display).	Confirm the latency budget with timestamped repeated runs and log CPU/RAM utilization and network-failure recovery across representative operating conditions.

distinguishes the completed final-test evaluation and deployed functional demonstrations from additional external-robustness and resource measurements that remain future work.

The Gemini 2.0 Flash part-number step requires network access and image transmission to a third-party service; classifier inference and cached PDF lookup are local. A practical design-level latency benchmark for the deployed Raspberry Pi 5 workflow is approximately 7 s per complete query under stable Wi-Fi: about 2 s for image capture and local ViT-Base classification, 4 s for cloud-assisted part-number extraction, and 1 s for local datasheet lookup and display. This value is used as an implementation benchmark rather than a calibrated timing statistic.

The qualitative deployment demonstrations confirmed operation of the six-stage component-information workflow but were not used to calculate classifier performance. Figure 16 documents the integrated camera/display face and physical presentation sequence. Figure 17 presents five examples produced by the deployed interface—LED, integrated circuit, potentiometer, resistor, and capacitor—under informally varied presentation conditions. Figure 18 documents the LM741 part-number result, the editable confirmation or correction step, and retrieval of the corresponding locally cached PDF. These examples provide evidence of end-to-end functional integration; they do not constitute a controlled assessment of performance on an independent external dataset.

The spread in Figure 17 is informative: correctly labeled examples can receive substantially different model scores because of object appearance, viewpoint, background, lighting, and visual similarity to other classes. The 71.81% capacitor example is intentionally retained rather than showing only best cases, supporting the design decision to expose uncertainty and require user confirmation before part-number and datasheet actions are accepted.

3.5. Pilot Student Perception Results

Table 7. Aggregate student-perception results for the BOOLE pilot.

Survey Statement	Yes (%)	No (%)
BOOLE helped me understand electronics and logic concepts better.	92	8
The hands-on interactive platform made learning more engaging.	92	8
Real-time LEDs and waveform feedback helped link theory to practice.	95	5
The device and interface were user-friendly and easy to use.	89	11
I prefer learning with BOOLE over traditional laboratories.	92	8
I would recommend BOOLE to other students or classes.	96	4

and Figure 19 report the complete distribution across the two response categories used in the pilot survey. Positive (Yes) responses ranged from 89% to 96%; willingness to recommend BOOLE was highest at 96%, while perceived ease of use was lowest at 89%. The corresponding No responses ranged from 4% to 11%. These results are interpreted only as preliminary learner-perceived effectiveness and acceptance, not as an objective learning-gain estimate.

Figure 19 presents the Yes and No response percentages for each of the six individual survey statements, allowing the full distribution across the response categories actually used in the pilot instrument to be viewed directly.

4. Discussion

4.1. Design Value of the Modular Architecture

BOOLE occupies a design space between simulation, portable measurement kits, fixed logic trainers, and AI information tools. Its contribution is the deliberate separation of these functions so that the AI face is supportive rather than prerequisite. The analog, combinational, and sequential faces each retain their own physical input–output path and remain usable with the Raspberry Pi, classifier, camera, network, and cloud service unavailable. The fourth face adds component identification, editable part-number assistance, and local datasheet access only; no learning-face circuit depends on AI to operate. Named-platform comparison in

Table 8. Evidence-grounded comparison of named portable electronics-learning platforms and BOOLE.

Criterion	Programme Take-Home Kits [7]	Lab in a Box [10]	WinterLab [11]	HELP [12]	BOOLE
Primary emphasis	Programme-aligned take-home activities	Portable Raspberry Pi-based electronics trainer	Portable integrated experimentation/measurement board	Portable generator/instrument plus functional board and breadboard	Progressive multi-face trainer plus optional AI support
Physical topology	Kit selected for programme activities	Trainer functions in a portable enclosure	Open experimentation with integrated instruments	Breadboard plus fixed functional blocks	Dedicated analog, combinational, and sequential PCBs
Curricular progression	Explicit programme-level alignment	Activity-level electronics coverage	Inquiry-oriented experimentation	Multi-generation electronics-lab activities	Explicit analog → combinational → sequential face sequence
Integrated instrumentation	Varies by kit	Raspberry Pi-based trainer functions	Integrated measurement functions	Portable signal generator and measurement instrument	LEDs/displays; no calibrated instrument suite
Maintenance boundary	Not reported as a formal design criterion	Not reported as a face-level boundary	Board-level product	Kit evolved across three generations	Replaceable faces, labeled headers, per-circuit shunts
AI component/datasheet aid	Not reported	Not reported	Not reported	Not reported	Optional classifier, editable part number, local PDF cache
Reported evaluation	Design and programme-use rationale	Development and initial testing	Design case and engagement rationale	Student surveys and staff focus groups	Functional prototype evidence and aggregate perception pilot

shows that WinterLab emphasizes portable integrated experimentation [11], HELP combines a portable signal generator/measurement instrument with a functional board and breadboard [12], Lab in a Box uses a Raspberry Pi-based portable trainer [10], and programme-level take-home kits prioritize alignment and safe independent use across activities [7]. BOOLE differs by physically mapping analog, combinational, and sequential progression to replaceable faces and adding optional component-to-datasheet support. This is a design distinction, not evidence of superior learning outcomes.

The architecture also improves fault containment. A damaged analog module can be removed while the digital and AI faces remain serviceable. A failed classifier does not prevent the AND gate or RC activity from operating. Per-circuit shunts reduce the number of active loads during troubleshooting. This is more than convenient maintenance; it is a design response to repeated educational use, where faults must be located quickly and where replacing an entire product for one damaged component is economically and environmentally undesirable.

4.2. Trade-Offs

The main trade-off is guided reliability versus open-ended construction. Hard-mounted circuits reduce wiring mistakes and keep a laboratory session focused on behavior, but they provide less topology freedom than a breadboard. BOOLE partly compensates with test headers, adjustable inputs, frequency and duty controls, and face replacement. A second trade-off is portability versus panel readability. The cube compresses four subsystems into a transportable object, but a very small enclosure would make labels and controls unusable. The final design therefore preserves full-face PCBs rather than shrinking the product to the dimensions of a conventional single-board trainer.

The dual-controller decision trades bill-of-materials cost and internal wiring for clean functional partitioning. A single Raspberry Pi could, in principle, control every activity, but its 3.3 V GPIO, operating-system timing, and software dependencies would become coupled to all learning faces. Retaining an Arduino for selected 5 V I/O keeps those activities deterministic and familiar. The Pi 5 is then free to manage vision, storage, and the graphical interface. Similarly, the OrCAD/Allegro toolchain increased dependence on commercial software, but provided an effective path through available libraries, industrial review, DRC, and fabrication. An open-source migration remains possible because the design intent and face boundaries are documented independently of the tool.

The AI subsystem trades immediacy for uncertainty. A predicted label and extracted marking can shorten lookup time, but a plausible result can still be wrong. The editable part-number field and direct display of the datasheet are therefore important design controls: they require the user to compare the physical marking, extracted string, and manufacturer document. The system should be viewed as a specification-literacy aid, not an authority. A future fully local text-recognition model would also remove the present cloud dependency in the part-number stage.

4.3. Safety, Standards, and Sustainability

The prototype was informed by principles relevant to laboratory equipment, including low-voltage operation, current limitation, visible operating states, retention of internal wiring, ventilation, and documented use. IEC 61010-1 is a relevant safety reference for electrical equipment used for measurement, control, and laboratory purposes [27], and ISO 9241-210 provides human-centered design principles for interactive systems [28]. BOOLE was not subjected to accredited conformity assessment or formal dielectric, temperature, abnormal-operation, mechanical, flammability, or accessibility testing. The defensible claim is therefore “low-voltage, standards-informed prototype,” not a safe, compliant, or certified product.

Sustainability is addressed only as a design intention. Replaceable faces and through-hole service access may extend useful life; segmented power prevents unnecessary energization of inactive learning circuits; and reusable fixed circuits may reduce loose-wire and damaged-component consumption across cohorts. These mechanisms are architecturally plausible but were not quantified through energy logging, repair statistics, life-cycle assessment, material inventory, or comparative cost. The project is pedagogically aligned with equitable access and sustainable engineering awareness [29], but no direct SDG impact or environmental superiority is claimed.

Future work should measure energy use, repair frequency, bill-of-materials mass, recycled content, and end-of-life separability before making comparative environmental claims.

4.4. Comparison with Named Alternative Learning Platforms

Table 8 uses criteria that can be traced to the cited platform descriptions rather than scoring BOOLE against generic categories. “Not reported” means the cited publication did not establish the criterion in a form suitable for this comparison; it does not imply that the platform cannot support it. BOOLE’s distinct proposition is the combination of curricular face progression, face-level service boundaries, selective circuit power, and optional component-to-datasheet assistance. Cost, learning gain, mass, setup time, and supervision time are omitted because harmonized measurements are unavailable.

For implementation transparency and reproducibility,

Table 9. Principal bill of materials and part numbers for BOOLE.

Component	Part Number
Slide switch	GF-123-0054
10 kΩ SMD resistor	CRCW040210R0FRED
Quadruple D-type flip-flop IC	SN74HC175DR
200 Ω SMD resistor	ERJ-2RKF2000X
SMD LED (20 mA)	SML-LX2832 SRCJR
330 Ω SMD resistor	AC0402FR-07330RL
7-segment display	LDS-C512RI
BCD/7-segment IC	CD4511BNSR
Pin header	4-103186-0
2-pin male header	N/A
Push button	HP0315AFKP2-R
1 kΩ potentiometer	PT01-D120D-B102
1-bit flip-flop IC	SN74LVC1G74DCUR
XOR gate IC	SN74LVC1G86DCKR
NOT gate IC	SN74LVC1G14DBVRE4
AND gate IC	SN74LVC1G08DBVRE4
OR gate IC	SN74LVC1G32DCKRE4
Comparator IC	CD74HC85PW
4-bit adder IC	SN74F283D
1 kΩ SMD resistor	CRCW04021K00FREDC
Counter IC	SN74HC193DR
Transistor	2N2222A
Diode	4878-1N4001CTT-ND
Buzzer	2223-CMI-1210-5-95T-ND
68.1 Ω SMD resistor	ERJ-2RKF68R1X

summarizes the principal electronic bill of materials used for the learning boards, including the component designations and manufacturer/supplier part numbers used during schematic capture, sourcing, and assembly.

4.5. Limitations and Next Validation Steps

BOOLE has been demonstrated as a functional engineering prototype through simulation-before-prototyping, powered state verification across the three learning faces, a 2000-original-image component-classification dataset with an untouched 200-image final-test partition, deployed physical-component checks qualitative demonstrations of the deployed component-information workflow, and the 73-participant perception pilot. The remaining validation scope is primarily an expansion of quantitative depth and generalizability rather than a redesign of the demonstrated architecture. Future work will prioritize the weakest AI categories, particularly transistors (F1-score 59.1%) and diodes (F1-score 72.2%), by collecting additional images of visually similar components under varied lighting, orientation, distance, and background conditions. In future evaluations, each physical component specimen and acquisition session will be assigned a unique identifier before partitioning. All photographs and derived images associated with the same specimen or session will be grouped within a single training, validation, or test partition. This grouped-partition design will prevent specimen-level and session-level leakage and permit a more defensible estimate of performance on previously unseen components. The ten one-versus-rest classifiers will then be replaced with a single balanced ten-class model, removing the 1:9 positive-to-negative imbalance of each binary task and making class scores more directly comparable. Improvement will be assessed using per-class and macro F1-scores, balanced accuracy, and a multiclass confusion matrix. In parallel, repeated calibrated electrical and timing measurements will quantify hardware repeatability, while objective pre/post concept and timed datasheet-search tests will extend the educational evaluation. Because the AI/touchscreen face is functionally independent of the analog, combinational, and sequential faces, these improvements can be introduced without redesigning or interrupting the core learning activities. Future work will expand the learner evaluation by collecting age, gender, year of study, prior academic achievement, and baseline electronics/logic knowledge. BOOLE exposure duration and learning activities will also be standardized and documented, complete Likert-scale response distributions will be reported, and objective pre/post assessments will be included to distinguish student perceptions from actual learning gains. The development and construction of the survey instrument will be documented, with content validity and internal consistency evaluated before broader implementation. Any new participant data collection will be conducted under new IRB approval.

5. Conclusions

This article presented BOOLE as an iterative engineering-design and prototype-demonstration case. The prototype integrates three manufacturable, two-layer learning PCBs, a ventilated serviceable cube, segmented power, deterministic 5 V controller I/O, and an independent AI/touchscreen support face. The documented workflow proceeded from requirement definition and component screening through circuit simulation, OrCAD/Allegro embodiment, DRC, three-dimensional review, fabrication, assembly rework, and complete-system functional checks. In particular, circuit behavior was simulated before prototyping, and the powered hardware was accepted only after its defined visual/state outputs matched the theoretical or simulated references, separating engineering verification from simple assembly evidence.

All implemented activity families reached their intended observable functional states after bring-up. Ten one-versus-rest component classifiers based on the ViT-Base transfer-learning approach were trained using a class-wise 80/10/10 training, validation, and final-test split performed before augmentation. On the untouched final-test data, accuracy ranged from 91.0% to 99.5%, F1-score from 59.1% to 97.4%, and balanced accuracy from 79.4% to 97.5%. The variation between accuracy and positive-class F1-score confirms that accuracy alone is insufficient for evaluating the imbalanced one-versus-rest classifiers. The deployed interface also completed the six-stage image-to-part-number-to-datasheet sequence as a functional demonstration, and the results support internal feasibility of the AI workflow but do not yet establish external generalization. The 73-participant pilot produced 89–96% positive (Yes) responses across the six binary acceptance and learner-perceived-effectiveness items. Together, these findings support prototype feasibility, functional integration, and preliminary learner-perceived effectiveness. The simulation-first design process, held-out image evaluation, qualitative deployment demonstrations, and end-to-end workflow provide a clear verification chain from design to implementation.