Microstrip Array Ring FETs with 2D p-Ga₂O₃ Channels Grown by MOCVD

Abstract

Gallium oxide (Ga₂O₃) thin films of various thicknesses were grown on sapphire (0001) substrates by metal organic chemical vapor deposition (MOCVD) using trimethylgallium (TMGa), high purity deionized water, and silane (SiH₄) as gallium, oxygen, and silicon precursors, respectively. N₂ was used as carrier gas. Hall measurements revealed that films grown with a lower VI/III ratio had a dominant p-type conduction with room temperature mobilities up to 7 cm²/Vs and carrier concentrations up to ~10²⁰ cm⁻³ for thinner layers. High resolution transmission electron microscopy suggested that the layers were mainly κ phase. Microstrip field-effect transistors (FETs) were fabricated using 2D p-type Ga₂O₃:Si, channels. They achieved a maximum drain current of 2.19 mA and an on/off ratio as high as ~10⁸. A phenomenological model for the p-type conduction was also presented. As the first demonstration of a p-type Ga₂O₃, this work represents a significant advance which is state of the art, which would allow the fabrication of p-n junction based devices which could be smaller/thinner and bring both cost (more devices/wafer and less growth time) and operating speed (due to miniaturization) advantages. Moreover, the first scaling down to 2D device channels opens the prospect of faster devices and improved heat evacuation.

1. Introduction

Recently, gallium oxide (Ga₂O₃) with an ultra-wide bandgap (UWBG) of ~4.9 eV has emerged as a next generation semiconductor material for high power electronic devices. This is in great part due to its high breakdown electric field (~8 MV/cm), which largely surpasses that of competing materials systems such as SiC or GaN. Furthermore, the emergence of n-type doping capacity and single crystal Ga₂O₃ substrates has allowed the development of various unipolar electronic devices including metal oxide semiconductor field effect transistors (MOSFETs), Schottky diodes, and metal semiconductor field effect transistors (MESFET), which have been demonstrated based on high quality homo-epitaxial growth [1,2,3]. The vast majority of this work has focused on homoepitaxial growth of monoclinic β-Ga₂O₃, which is the most stable of five common polytypes α-, β-, γ-, ε-, and κ). A major drawback of β-Ga₂O₃ until recently, however, has been lack of a method to obtain p-type conduction; this is a key limitation for its adoption in a whole range of semiconductor device applications. Moreover, the relatively low thermal conductivity of Ga₂O₃ and the problem of Ga₂O₃ substrate cost being two orders of magnitude higher than sapphire are both currently hindering the fuller development of Ga₂O₃-based powered electronics. In previous studies, we showed that κ-Ga₂O₃ (an orthorhombic polymorph which is normally considered to be transient) could be stabilized in heteroepitaxial growth on sapphire (0001) substrates by MOCVD [4,5,6,7,8,9,10,11,12]. In this work, we found that high levels of shallow acceptor p-type conduction could be achieved in such layers using silicon impurity doping under Ga rich growth conditions. We then processed 2D layers of such p-type Ga₂O₃:Si into microstrip array ring FETs using conventional photolithography. The operational characteristics of the FETs proved to be consistent with p-type conduction. This is the first demonstration of both shallow acceptors doping of Ga₂O₃ and a p-type Ga₂O₃ channel FET. A phenomenological model that is coherent with a p-type channel is also presented.

2. Materials and Methods

A commercial MOCVD reactor (AIXTRON 200/4 RF) was used to grow Ga₂O₃ on sapphire (0001) substrates at growth temperatures ranging from 730 °C to 1000 °C. Trimethylgallium (TMGa), high purity deionized water and SiH₄ were adopted as the Ga, O and Si precursors, respectively. N₂ was used as the carrier gas. The total pressure was 50 mbar. The VI/III ratio was either 100 (Ga-rich) or 150 (O-rich). The SiH4 flow rate was fixed at 15 sccm [4,5,6,7,8,9,10,11,12].

3. Results

XRD analysis was performed (Figure 1) to analyze the phases of the grown ~150 nm thick Ga₂O₃:Si with different VI/III ratio 100 and 150. The XRD results showed three peaks for each Ga₂O₃:Si layer. The three peaks that were observed were similar to the results of the β-Ga₂O₃ substrate (Figure 1). However, the TEM analysis in Figure 1d showed the result of κ-phase with the space group of Pna2₁ [4,5,10]. This metastable and transient κ-Ga₂O₃ was also identified by Playford et al. [13]. The κ-phase Ga₂O₃:Si was grown in the (002) direction and the six rotated domains were observed in the ~150 nm thick Ga₂O₃:Si.

Electrical properties were measured using Van der Pauw Hall measurements. Ohmic contacts were obtained using a Ga/In eutectic. Figure 2a,b show the results as a function of growth temperature for both VI/III ratios. At a VI/III ratio of 150, Ga₂O₃:Si that was grown at 730 °C shows n-type characteristics and the carrier concentration is ~2.6 × 10¹⁸ cm⁻³. The average resistivity is measured as ~4.3 Ω·cm. As the growth temperature was increased from 730 °C to 1000 °C, the carrier concentration decreased linearly to ~4.4 × 10¹⁷ cm⁻³. Such a tendency is reminiscent of the amphoteric doping of GaAs with Si [14,15]. In the case of GaAs, p-type Si doping behavior was obtained for a relatively low V/III ratio and growth temperature [16,17,18]. Assuming that the Si dopant acts as a shallow acceptor by substituting on the O-site of the Ga₂O₃, the VI/III ratio of 100 growth condition could be expected to a generate higher density of oxygen vacancies (V_O) by virtue of the Ga-rich nature of the growth which lets the Si substitute more readily at the O-sites. This assumption is coherent with Figure 2c which shows the Hall mobility of the Ga₂O₃:Si as a function of growth temperature for VI/III ratios of 150 and 100. For a VI/III ratio of 150, an n-type mobility near 50 cm²/Vs was observed for a growth temperature of 1000 °C. For a VI/III ratio of 100, a p-type mobility of ~3.3 cm²/Vs was observed. This demonstrates Si being an amphoteric dopant in κ-Ga₂O₃. Si impurity doping is generally incorporated to substitute for Ga where it acts as a shallow donor to create heavily doped n-type Ga₂O₃. But as the density of V_O increases under Ga-rich growth conditions, the above results suggest that Si can act as a shallow acceptor by substituting on the O-sites in κ-Ga₂O₃, and thus promote a transformation to predominantly p-type conduction. These p-type results were confirmed via theoretical and experimental measurements by multiple groups [19,20,21].

Ring type FETs were fabricated and evaluated for the characteristics of the FET device of ~150 nm thick p-type Ga₂O₃:Si with VI/III ratio of 100. Figure 3 shows the I-V curves; a negative bias voltage was applied to the drain terminal and the Vds values of all presented experimental and theoretical results correspond to the magnitude of drain-source voltage |Vds|. It was observed that the drain current decreased with increasing gate voltage. However, it was not possible to achieve pinch-off due to the gate electrode burning at gate voltages higher than 50 V. To avoid this issue, the channel thickness was reduced to ~1.2 nm and the ring pattern FETs were patterned with microstrips. Ga₂O₃:Si channel layers were grown at 1000 °C with a VI/III ratio of 100. The channel thickness was estimated to be ~1.2 ± 0.5 nm based on the interferometric growth rate calibration and AFM step-edge profilometry. Hall measurements confirmed the p-type nature of the layers with a resistivity of ~0.007 $\mathsf{\Omega }$·cm, a carrier concentration of ~1.7 × 10²⁰ cm⁻³, and a mobility of ~5.7 cm²/Vs.

Standard photolithography and lift-off were employed to deposit source and drain metal contacts. Before their deposition, 3 μm × 3 μm microstrip patterns were formed by electron cyclotron resonance-reactive ion etching (ECR-RIE) with CF₄ for 5 min. The metal contacts were Ti (20 nm)/Au (150 nm) deposited by e-beam evaporation. SiO₂ of 100 nm thick gate dielectric material was formed by plasma-enhanced chemical vapor deposition (PECVD). After dielectric and passivation film deposition, the gate metal contact was formed with Pt (20 nm)/Ti (20 nm)/Au (150 nm) on the SiO₂ film. The gate length, and the spacing between the source/drain and the inside source circular pad were 15, 20, and 100 μm, respectively. Figure 4a shows schematic illustrations of the device with top- and cross-sectional views illustrating the device scale. Figure 4b shows an optical microscope image of the fabricated devices.

The FETs were then fabricated and tested using a semiconductor parameter analyzer and probe station. Figure 5a shows the DC source-drain current versus source-drain voltage (I_DS–V_DS) output characteristics for the depletion-mode FETs that were measured by increasing the gate-source voltage (V_GS) stepwise from −50 to 100 V. The maximum I_DS was 2.19 mA and it was effectively modulated by V_GS from −50 to 100 V, which is coherent with a p-type channel. Because of the heavy p-doping, the 2D microstrip channel is normally-on, and the channel off-state was observed for a gate bias of 50 V (I_DS = 0.1 pA at V_DS of 40 V). In addition, because of the high sheet resistance, even with a drain voltage as high as 40 V, the voltage drop in the FET channel was still lower than |V_G-V_T|, which was the condition for current saturation in long channel FETs. As such, the I_DS-V_DS characteristics remained linear. Figure 5b displays a similar set of curves that were obtained from the simulation. It can be seen that the theoretical model is consistent with the experimental data in showing an output resistance increase with positive gate voltage and I_DS bunching with little variation of the output resistance for V_GS < 0. This is also consistent with a p-type channel. Figure 5c shows the transfer characteristics at V_DS of 10 to 40 V in a logarithmic scale. The device achieved an on/off ratio of ~10⁸ by minimizing the thickness and width of the channel. Figure 5d shows that IG increases above a V_GS of 50 V because of a gate leakage current. It is expected that the on/off ratio can be further improved through the optimization of the dielectric layer.

A phenomenological model was developed that was based on the device configuration that is displayed in Figure 4. Figure 6 shows the schematic of the model device that consists of a linear array of $\delta$ = 3 $\mathsf{\mu }$m wide micro-strips that were separated from each other by $\delta$ = 3 $\mathsf{\mu }$m. They are covered by a disk-shaped source contact of 200 μm in diameter and separated from a square shaped drain by a 30 $\mathsf{\mu }$m wide circular channel. As such, in each quadrant, the channel length, Li, varies between a minimum value when it is perpendicular to the disk and a maximum value when it is tangential to the disk. The position of the ith microstrip is identified by its distance, di, from the center of the source disk.

At V_G = 0 V, the channel is uniform and the current between source and drain in the i^th micro-strip channel is given by

$$I_i=e{p}_s\delta v_i$$

(1)

where e is the electron charge (C), $p_s$ is the 2D hole concentration (carriers/cm²), $\delta$ the wire width (cm), and $v_i$ is the hole velocity in the ith channel (cm/s). In the absence of saturation velocity (long channel-low mobility),

$$v_i=\frac{\mu V_{DS}}{L_i}$$

(2)

where μ is the hole mobility (cm²/Vs) and $L_i$ is the channel length (cm).

If $d_i= 2i\delta with 0\le i\le N$, Equation (1) becomes for top and bottom right quadrants

$$I_{right}= 2{{\displaystyle \sum }}_{i=0}^N{I}_i=e{p}_S\mu V_{DS}{{\displaystyle \sum }}_{i=0}^{N}1/\left[\sqrt{{\left(N+5\right)}^2- i^2}- \sqrt{N^2- i^2}\right]=2.84e{p}_S\mu V_{DS}$$

(3)

Due to the relatively big gate pad on the left side of the source, the channel lengths are longer for a sizeable portion of the FIN-microstrips, so we estimate the total current should be multiplied by a factor $\eta$ ~ 1.8–1.9 < 2. Finally,

$$I= I_{Right}+I_{Left}= \eta I_{Right}$$

(4)

At $V_G\ne 0$, the channel is made of three portions with different conductances (Figure 6b). By neglecting the contact resistance, we get for each channel,

$$I_i\left(V_G\right)=\frac{V_{DS}}{\frac{1}{G_1^i}+\frac{1}{G_2^i}+\frac{1}{G_3^i}} with G_{1,3}^i=\frac{e{p}_s\left(V_G=0\right)\delta \mu }{L_{1,3}^i} G_2^i=\frac{e{p}_s\left(V_G\ne 0\right)\delta \mu }{L_2^i}$$

(5)

If $P_s\left(V_G\ne 0\right) = P_s\left(V_G=0\right)exp\left(-\frac{e{V}_c}{KT}\right), \mathrm{where} V_c\left(V_G\right)$s the channel potential that is induced by the gate bias, the expression for the current reads

$$I_i\left(V_G\right)= e{p}_s\left(V_G=0\right)\delta \mu V_{DS}/\left(L_1^i+L_2^{i}exp\left(e{V}_C/kT\right)+L_3^i\right)$$

(6)

or after summation over all channels,

$$\left(V_G\right)=\frac{2I\left(V_G=0\right)}{1+exp\left(\frac{e{V}_C}{kT}\right)}$$

(7)

This equation shows that for V_C < 0 (V_G< 0) the drain current decreases, whereas for V_C > 0 (V_G > 0) the drain current increases in agreement with the experimental data. This is coherent with the channel being a p-type. In quantitative terms, it shows that current decreases by several orders of magnitude under a positive V_G compared to a limiting increase by a factor 2 under a negative V_G. This asymmetry in the variation of the I-V characteristics for V_G < 0 and V_G> 0 is also consistent with the experimental data.

From the Poisson equation, one can derive an expression of V_C for intermediate gate bias:

$$V_C\left(y\right)=\frac{V_G{\lambda }_{D}exp\left(-\frac{y-D}{{\lambda }_D}\right)}{D+{\lambda }_D}$$

(8)

where D is the thickness of the SiO₂ barrier, y is the vertical coordinate inside the Ga₂O₃ layer, and ${\lambda }_D$ is the Debye length in the Ga₂O₃ layer that is fitted to reproduce the experimental I-V characteristics. Figure 5b displays the simulation data of I-V curves from V_GS = −40 to 40 V, for which we used a channel mobility $\mu$ = 23 cm²/Vs and hole concentration p_s = 2.35 × 10¹²/cm².

4. Conclusions

In conclusion, $\kappa$-Ga₂O₃:Si layers that were grown on sapphire (0001) substrates by MOCVD showed consistent p-type Hall signal for layers that were grown with lower III/VI ratios during growth. The room temperature mobilities were up to 7 cm²/Vs, resistivities were as low as 0.007 $\mathsf{\Omega }$.cm, and the carrier concentrations were up to ~10²⁰ cm⁻³ for thinner layers. The ring mesa FETs were fabricated based on ~1.2 nm thick p-Ga₂O₃:Si channels that were formed into a number of 3 $\mathsf{\mu }$m wide microstrips. The devices achieved a maximum drain current density of 2.19 mA and an on/off ratio of ~10⁸ and showed characteristics that were consistent with a p-type conduction in the channel. The p-type Ga₂O₃ that was demonstrated in this work represents a significant advance and is state of the art, which may herald the fabrication of a range of p-n junction-based devices. These could be smaller/thinner and bring both cost (more devices/wafer and less growth time) and operating speed (due to miniaturization) advantages than current isotype FETs. Moreover, the demonstration of the first functioning devices based on scaling down to 2D device channels in Ga₂O₃ based FETs opens the prospect of faster devices and improved heat evacuation.