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Fast Frame Synchronization Design and FPGA Implementation in SF-BOTDA

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College of Information Science and Technology, Jinan University, Guangzhou, Guangdong 510632, China
2
College of Qiuzhen, Huzhou University, Huzhou, Zhejiang 313000, China
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ITEAM Research Institute, Universitat Politècnica de València, 46022 Valencia, Spain
*
Author to whom correspondence should be addressed.
Photonics 2020, 7(1), 17; https://doi.org/10.3390/photonics7010017
Received: 26 November 2019 / Revised: 25 January 2020 / Accepted: 6 February 2020 / Published: 8 February 2020
To address the issues of high time consumption of frame synchronization involved in a scanning-free Brillouin optical time-domain analysis (SF-BOTDA) system, a fast frame synchronization algorithm based on incremental updating was proposed. In comparison to the standard frame synchronization algorithm, the proposed one significantly reduced the processing time required for the BOTDA system frame synchronization by about 98%. In addition, to further accelerate the real-time performance of frame synchronization, a field programmable gate array (FPGA) hardware implementation architecture based on parallel processing and pipelining mechanisms was also proposed. Compared with the software implementation, it further raised the processing speed by 13.41 times. The proposed approach could lay a foundation for the BOTDA system in the field with the associated high real-time requirements.
Keywords: Brillouin optical time-domain analysis; frame synchronization; field programmable gate array; incremental updating Brillouin optical time-domain analysis; frame synchronization; field programmable gate array; incremental updating
MDPI and ACS Style

Pan, Q.; Huang, X.; Min, R.; Liu, W. Fast Frame Synchronization Design and FPGA Implementation in SF-BOTDA. Photonics 2020, 7, 17.

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