Modular Multilevel Converter-Based Hybrid Energy Storage System Integrating Supercapacitors and Batteries with Hybrid Synchronous Control Strategy

Abstract

This paper proposes a hybrid synchronization control modular multilevel converter-based hybrid energy storage system (HSC-MMC-HESS) that innovatively integrates battery units within MMC submodules (SMs) while connecting a supercapacitor (SC) to the DC bus. The configuration synergistically combines the high energy density of batteries with the high power density of SCs through distinct energy/power pathways. The operational principles and control architecture are systematically analyzed, incorporating a hybrid synchronization control (HSC) strategy to deliver system inertia, primary frequency regulation, fault-tolerant mode transition capabilities, and isolation control. A hierarchical control framework implements power distribution through filtering mechanisms and state-of-charge (SOC) balancing control for battery management. Hardware-in-the-loop experimental validation confirms the topology’s effectiveness in providing inertial support, enabling flexible operational mode switching and optimizing hybrid energy storage utilization. The demonstrated capabilities indicate strong application potential for medium-voltage distribution networks requiring dynamic grid support.

1. Introduction

The growing integration of renewable energy sources, particularly wind and photovoltaic power, into power systems has substantially reduced the penetration of conventional synchronous generators, leading to diminished system inertia. This inertia reduction, coupled with the inherent intermittency of renewable generation, exacerbates frequency regulation challenges, thereby compromising grid stability and power quality. To mitigate these operational constraints, energy storage systems equipped with frequency regulation capabilities have emerged as critical components for maintaining generation–load balance and enhancing grid stability in renewable-dominated power networks [1,2,3].

Existing single-structure energy storage systems, due to the characteristics of energy storage resources, cannot independently meet the frequency regulation requirements of the system [3]. To improve power system reliability while addressing the requirements for rapid power response and high-capacity energy storage, battery–supercapacitor hybrid energy storage systems have gained significant research and industrial adoption. [4,5,6]. Batteries exhibit high energy density and superior cycle efficiency; however, they suffer from limited response speed. Conversely, supercapacitors demonstrate exceptional power density, rapid charge/discharge capabilities, and extended cycle life, albeit with constrained energy storage capacity. The strategic integration of these complementary technologies in hybrid energy storage systems effectively addresses concurrent requirements for high-power delivery and substantial energy reserves. This synergistic configuration enhances power output characteristics, accelerates system response dynamics, and mitigates component degradation through optimized energy allocation mechanisms.

In 10 kV medium-voltage distribution networks, energy storage devices are typically connected through two topologies. One involves connecting DC-side storage through a medium/low-voltage converter after voltage step down via an isolation transformer, but it faces challenges such as small capacity and coordination issues. There have been some mature studies on energy storage systems based on MMC [7,8,9]. In MMC-based systems, such as the MMC-BESS [10], batteries and capacitors are connected in parallel across submodules for voltage balancing, though the DC bus-side configuration is not considered. Reference [11] presents a hybrid MMC-based energy storage system (MMC-HESS) combining supercapacitors and batteries, where the batteries are directly connected in series on the DC side. This setup meets high power and fast response needs, but the series connection of batteries is limited by the SOC balancing algorithm, preventing it from meeting capacity requirements. Reference [12] introduces another MMC-HESS, with batteries in the upper-arm submodules and supercapacitors in the lower-arm submodules. The asymmetry in energy storage resources requires complex control strategies and reduces system stability and resource utilization. This paper proposes a novel topology that deploys supercapacitors on the DC side and replaces submodule capacitors with batteries, significantly improving system performance across multiple metrics.

Table 1. Performance comparison of different topologies.

Evaluation Metric	Topology 1	Topology 2	Topology 3
Energy Utilization	High	Low	High
Dynamic Response Time	Slow	Medium	Fast
Power Distribution Efficiency	Low	Medium	High
SOC Balancing Complexity	High	Low	Low

presents comparative results, where the topology numbering corresponds to their order of presentation in the text.

The MMC-HESS in the above references all use grid-following (GFL) control, with the phase-locked loop (PLL) measuring the grid voltage frequency as a reference for fast power response, but they lack frequency support capability. In grid-forming (GFM) control, virtual synchronous generator (VSG) control with virtual inertia and frequency regulation has been extensively studied in low-voltage three-phase inverters [13,14] and widely applied in medium- and high-voltage MMC topologies. Reference [15] proposes a VSG control strategy for MMC that can provide reactive power compensation during voltage sag; however, it does not include specific standards for reactive power compensation, nor does it consider the time standard for islanding. Reference [16] implements AC/DC power transfer using MMC with VSG control, similar to MMC-HVDC [17,18], but it lacks energy storage. Reference [19] proposes a transient current suppression strategy for MMC, but it does not consider the switching of the actual operating state of MMC, such as grid connection and disconnection transitions.

To address the power response requirements for primary frequency regulation and resolve virtual synchronous generator control transition challenges during voltage sags and grid mode switching, this paper presents (1) an HSC strategy for MMC-HESS enabling concurrent inertia support, frequency regulation, low-voltage ride-through capability, and seamless grid interconnection/disconnection and (2) a coordinated power distribution strategy with SOC balancing through circulating current control for battery–supercapacitor systems. (3) The proposed architecture was successfully implemented and experimentally validated using a hardware-in-the-loop (HIL) platform, employing PLECS for real-time simulation with an RT-Box and DSP-based controller execution.

2. MMC-HESS Topology Working Principle

2.1. MMC-HESS Topology

The main circuit topology of MMC-HESS [20] is shown in Figure 1. It features a three-phase bridge arm, each phase consisting of two upper and lower bridge arms, connected by the bridge arm impedance, i.e., the bridge arm inductance L₀ and bridge arm resistance R₀. Both the upper and lower bridge arms are cascaded with an equal number of identical submodules (SMs), where each submodule is a parallel structure that includes a battery, a full-bridge converter, and a parallel capacitor to control the rate of change of the DC-side voltage during the switching process of the converter bridge. The communication side terminals are drawn from the connection impedance midpoint of each phase’s upper and lower bridge arms and then connected to the grid through an LC filter and line impedance. The necessity of the LC filter depends on the modulation strategy and the number of submodules per arm and is generally not mandatory. The supercapacitor is formed by connecting multiple capacitor cells in series on the DC side.

The modular design of the MMC-HESS bridge arm structures enables direct integration into the 10 kV distribution network without the need for a step-down transformer. Appropriate modulation strategies for the bridge arm voltage can be adopted to reduce the switching frequency requirements of power electronic devices. Compared to two-level converters operating above 2.5 kHz, the MMC-HESS system only requires a switching frequency range of 300–800 Hz, yielding substantial switching loss reductions.

The distributed battery configuration across submodules simplifies individual battery management system (BMS) control while maintaining SM voltage stability under equivalent energy capacity. Supercapacitors are strategically positioned on the full-bridge MMC’s high-voltage DC bus, providing extended voltage regulation range that maximizes SC energy utilization efficiency through adaptive voltage matching.

2.2. MMC-HESS Mathematical Model

The single-phase equivalent circuit for three-phase symmetrical operation is illustrated in Figure 2, where u_sj denotes the AC voltage on the grid side; u_pj and i_pj represent the voltage and current of the upper bridge arm, respectively; u_nj and i_nj represent the voltage and current of the lower bridge arm, respectively; U_SC represents the terminal voltage of the DC-side supercapacitor.

The MMC’s AC and DC sides can be equivalently expressed as:

$$\left\{\begin{array}{c}{L}_{\mathrm{e}}{\displaystyle \frac{\mathrm{d}{i}_j}{\mathrm{d}t}}+R_{\mathrm{e}}{i}_j=u_{\mathrm{s}j}-e_j\\ L_0{\displaystyle \frac{\mathrm{d}{i}_{\mathrm{cir}j}}{\mathrm{d}t}}+R_0{i}_{\mathrm{cir}j}={\displaystyle \frac{U_{\mathrm{SC}}}{2}}-e_{\mathrm{dc}j}\end{array}\right.$$

(1)

where e_j is the AC equivalent electromotive force, e_dcj is the DC equivalent electromotive force, and i_cirj is the circulating current. L_e and R_e are the AC equivalent inductance and resistance, respectively.

The equivalent expression is given by:

$$\begin{array}{cc}\left\{\begin{array}{c}{e}_j\triangleq {\displaystyle \frac{u_{\mathrm{n}j}-u_{\mathrm{p}j}}{2}}\\ e_{\mathrm{dc}j}\triangleq {\displaystyle \frac{u_{\mathrm{n}j}+u_{\mathrm{p}j}}{2}}\\ i_{\mathrm{cir}j}\triangleq {\displaystyle \frac{i_{\mathrm{n}j}+i_{\mathrm{p}j}}{2}}\end{array}\right.& \left\{\begin{array}{c}{L}_{\mathrm{e}}=\left(L_{\mathrm{s}}+{\displaystyle \frac{L_0}{2}}\right)\\ R_{\mathrm{e}}=\left(R_{\mathrm{s}}+{\displaystyle \frac{R_0}{2}}\right)\end{array}\right.\end{array}$$

(2)

By neglecting the high-frequency components of the circulating current i_cirj and DC electromotive force e_dcj, and considering only the DC component and the fundamental frequency component [21], the total power absorbed by the single-phase battery P_Bj and the power difference across the upper and lower bridge arms P_Δpnj are expressed as:

$$\begin{array}{c}{P}_{\mathrm{B}j}=2U_{\mathrm{DC}j}{I}_{\mathrm{DC}j}+2U_{\mathrm{AC}j}{I}_{\mathrm{AC}j}\cos \left({\phi }_{j3}-{\phi }_{j1}\right)+\\ U_j{I}_j\cos \left({\phi }_{j4}-{\phi }_{j2}\right)\end{array}$$

(3)

$$\begin{array}{c}{P}_{\Delta \mathrm{pn}j}=-U_{\mathrm{AC}j}{I}_j\cos \left({\phi }_{j3}-{\phi }_{j2}\right)-\\ 2U_j{I}_{\mathrm{AC}j}\cos \left({\phi }_{j4}-{\phi }_{j1}\right)\end{array}$$

(4)

From Equation (3), the DC component of the circulating current I_DCj is introduced into the phase power balance in this topology.

According to Equation (4), the fundamental frequency component of the circulating current I_ACj is introduced to balance the power between the upper and lower bridge arms [22,23].

Additionally, the nearest-level modulation (NLM) algorithm [24] is used to implement the SOC balancing control between the batteries within the submodules.

2.3. Power Flow Characteristics

The MMC-HESS has four power sources: the grid-side input power P_g, the battery output power P_bat, the supercapacitor output power P_SC, and the converter losses P_SC. According to the power conservation law, these four powers satisfy:

$$P_{bat}+P_{SC}+P_g=P_{SW}$$

(5)

Thus, by controlling the AC-side power P_g and the DC-side power P_SC, the power distribution and control between the battery and supercapacitor can be achieved. The reference value for the DC-side power P_SCref can be distributed by using a filter [25].

3. Hybrid Synchronous Control Strategy

3.1. AC-Side Control Strategy

3.1.1. HSC Power Control Considering Both Grid-Connected and Off-Grid Modes

The HSC power control strategy is based on VSG and PLL control. The frequency control loop incorporates frequency components from both of these control strategies [26].

The VSG active power–frequency control model, which considers virtual inertia, damping characteristics, and primary frequency regulation, is given by the following equation:

$$\begin{array}{l}{P}_{\mathrm{ref}}-P_{\mathrm{e}}=J’{\omega }_0{\displaystyle \frac{\mathrm{d}\omega }{\mathrm{d}t}}+\left(D’{\omega }_0+K_{\omega }\right)\left(\omega -{\omega }_0\right)=\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}J{\displaystyle \frac{\mathrm{d}\omega }{\mathrm{d}t}}+D_{\mathrm{p}}\left(\omega -{\omega }_0\right)\end{array}$$

(6)

where J’ is the virtual inertia of the VSG-controlled converter. D’ is the damping factor of the frequency regulator. K_ω is the droop coefficient for primary frequency regulation. P_ref and P_e are the reference active power and the actual output power, respectively. ω₀ is the rated electrical angular frequency (100π rad/s). ω is the actual electrical angular frequency. J and D_p are the inertia and damping coefficients of the simplified oscillation equation.

According to Equation (6), the angular frequency of VSG is:

$${\omega }_{\mathrm{VSG}}={\omega }_0+{\displaystyle \frac{1}{Js+D_{\mathrm{p}}}}\left(P_{\mathrm{ref}}-P_{\mathrm{e}}\right)$$

(7)

During severe faults, when active power cannot meet the reference value, the oscillation equation will become unstable, and the VSG will lose synchronization with the grid. To solve the synchronization problem, a PLL component is introduced into Equation (7). In practical control, the integral term in PLL causes static errors; so, only the proportional term is kept. This simplifies to:

$${\omega }_{\mathrm{HSC}}={\omega }_0+{\displaystyle \frac{1}{Js+D_{\mathrm{p}}}}\left(P_{\mathrm{ref}}-P_{\mathrm{e}}\right)+K_{\mathrm{p}}{U}_{\mathrm{o}q}$$

(8)

where U_oq is the q-axis component of the output voltage at the grid connection point. K_p is the proportional coefficient of PLL.

Additionally, the MMC islanding mode eliminates PLL components due to absent grid synchronization requirements. During pre-synchronization, analogous phase-locking mechanisms ensure grid–machine voltage alignment through q-axis voltage matching at the converter’s grid terminal. Thus, U_oq is replaced with the q-axis component of the grid-side voltage U_pccgq.

The adjusted frequency of HSC is:

$${\omega }_{\mathrm{HSC}}={\omega }_0+{\displaystyle \frac{P_{\mathrm{ref}}-P_{\mathrm{e}}}{Js+D_{\mathrm{p}}}}+S_{\mathrm{oncmd}}{K}_{\mathrm{p}}{U}_{\mathrm{pccg}q}$$

(9)

where S_oncmd represents the grid connection control signal, which is 1 during grid-connected operation and pre-synchronization, and 0 during off-grid operation.

The VSG’s reactive voltage loop usually uses droop control. During pre-synchronization, in addition to achieving phase synchronization (9), voltage amplitude matching is required. The adjusted voltage reference is:

$$E_{\mathrm{ref}}=E_0+{\displaystyle \frac{Q_{\mathrm{ref}}-Q_{\mathrm{e}}}{K_Q}}+{\displaystyle \frac{S_{\mathrm{pres}}\left(U_{\mathrm{pccg}}-U_{\mathrm{o}}\right)}{s}}$$

(10)

where K_Q is the reactive power–voltage droop coefficient; E_ref and E₀ are the voltage reference value and the rated value, respectively; Q_ref and Q_e are the reactive power reference value and the actual output value, respectively; U_pccg and U_o are the grid-side voltage amplitude and the machine-side voltage amplitude of the grid connection switch, respectively; S_pres represents the pre-synchronization signal, where it is 1 during pre-synchronization and 0 at other times.

In summary, the HSC power control loop for both grid-connected and islanding control is shown in Figure 3, including the active power–frequency loop and reactive power–voltage loop.

In Figure 3, the active power–frequency loop generates the VSG frequency component based on the reference active power P_ref and actual active power P_e. The PLL frequency component is derived from the q-axis component of the grid-side voltage U_pccgq and the grid connection control signal S_oncmd. Both frequency components are then combined with the nominal frequency ω₀ to form the output frequency ω_HSC. After integration, the reference phase angle θ_HSC is obtained. The reactive power–voltage loop generates the reactive voltage droop component based on the reference reactive power Q_ref and actual reactive power Q_e. It also generates the pre-synchronization component using the grid-side voltage magnitude U_pccg, machine-side voltage magnitude U_o, and the pre-synchronization signal S_pres. Both voltage components are combined with the rated voltage E₀ to form the output voltage reference E_ref.

3.1.2. Low-Voltage Ride-Through Switching Strategy

Figure 4 specifies the reactive current compensation thresholds and islanding timing criteria: system operation switches to islanding mode when voltages persist below the defined threshold curve, while maintaining grid connection with reactive current injection above the curve.

According to Equation (10), the HSC reactive voltage loop cannot meet the reactive current curve and has a slow response. Therefore, during voltage sag, the q-axis current reference value output by the q-axis voltage loop should be switched to the reactive current curve shown in Figure 4. However, after switching the i_qref, the d-axis voltage loop will no longer track the reference without static error. Therefore, the d-axis current reference value needs to be switched simultaneously; the switched current reference value is:

$$\left\{\begin{array}{l}{i}_{q\mathrm{ref},0}=\left\{\begin{array}{l}1.5\left(0.9-U_{\mathrm{pccg}}\right),0.2\le U_{\mathrm{pccg}}\le 0.9\\ 1.05,U_{\mathrm{pccg}}<0.2\end{array}\right.\\ i_{d\mathrm{ref},0}=\min \left(\frac{P_{\mathrm{ref}}}{U_{\mathrm{pccg}}},\sqrt{{1.2}^2-{i_{q\mathrm{ref}}}^2}\right)\end{array}\right.$$

(11)

The fault islanding time is:

$$t\left(U_{\mathrm{pccg}}\right)=\left\{\begin{array}{l}\infty ,U_{\mathrm{pccg}}>0.9\\ 2-1.375\frac{\left(0.9-U_{\mathrm{pccg}}\right)}{0.7},0.2\le U_{\mathrm{pccg}}\le 0.9\\ 0.001,U_{\mathrm{pccg}}<0.2\end{array}\right.$$

(12)

After fault recovery or islanding operation, the fault current-limiting mode is exited. To reduce the impact current after switching modes during grid connection, the fault current-limiting mode will continue until ω_HSC stabilizes. The voltage loop PI controller will be improved to a compensatable PI controller, as shown in the control block diagram in Figure 5.

In Figure 5, the output value i_dqref,1 of the PI controller is:

$$i_{dq\mathrm{ref},1}=\left\{\begin{array}{l}\left(K_{\mathrm{p}}+\frac{K_{\mathrm{i}}}{s}\right)\Delta u,S_{\mathrm{mode}}=1\\ K_{\mathrm{p}}\Delta u+\frac{K_{\mathrm{i}}}{K_{\mathrm{p}}s+K_{\mathrm{i}}}{i}_{dq\mathrm{ref},0},S_{\mathrm{mode}}=0\end{array}\right.$$

(13)

where S_mode is the mode switching signal, which is 0 after a voltage sag during grid connection and 1 during islanding operation or normal grid connection. i_dqref,0 is the current reference during fault current limiting.

The voltage loop employs PI control in grid-connected/islanded modes. During grid-connected voltage sags, current reference transitions to fault-limited output—PI output becomes superposition of fault-limited value and proportional term. When switching from grid-fault to islanded/normal grid operation, the integrator initializes with a fault-limited value, expediting transient recovery.

The dual-loop control block diagram considering low-voltage ride-through is shown in Figure 6.

In the voltage control loop, which includes the PI compensating controller and LC filtering capacitor decoupling term, as shown in Figure 6, the current reference values i_odref and i_oqref are obtained based on the dq-coordinate voltage reference E_ref, 0, and the actual values u_od, u_oq. In the current control loop, which includes the traditional PI controller and LC filtering inductance decoupling term, the dq-coordinate reference values for the AC equivalent electromotive force e_dref, e_qref are calculated from the current reference values i_odref, i_oqref and their actual values i_od, i_oq.

3.1.3. Islanding Detection and Grid Connection/Island Operation Control

The grid connection and island operation control strategies, as well as the islanding detection strategy, are shown in Figure 7. In Figure 7, the following symbols are used: S_plan, S_oncmd, S_swcmd, S_state, and S_pres represent the grid connection plan (this signal is actively set and should be set to 1 when grid connection is required), grid connection control, grid switch, islanding grid state, and pre-synchronization signal, respectively. U_pccg, u_pccgα, and u_pccgβ represent the magnitude, α-axis component, and β-axis component of the grid-side voltage of the grid switch. ε_U,1, ε_U,2 are the grid switch closing judgment threshold and islanding detection threshold.

As shown in Figure 7a, the system can directly operate in islanding mode during planned disconnection, or it can disconnect and operate in islanding mode under fault conditions where the grid-connected state operates below the voltage curve shown in Figure 6, by setting S_oncmd = 0.

As shown in Figure 7b, when S_oncmd = 0, the grid switch directly opens. When S_oncmd = 1, the grid switch closes based on the squared difference of voltage phasors on both sides of the switch. Islanding and grid connection states are also detected based on the squared difference of the voltage phasors.

As shown in Figure 7c, the pre-synchronization signal introduced into the reactive power–voltage loop is derived from the grid connection control signal S_oncmd and the islanding grid state S_state.

3.1.4. Overall AC-Side Control Model

The AC-side control model, shown in Figure 8, includes the HSC power loop, the voltage–current double inner loop, low-voltage ride-through control, and islanding detection and grid connection/islanding control modules. The AC-side control strategy, based on the grid connection plan S_plan, the PCC point grid-side voltage u_pccg, the machine-side voltage u₀, the current i₀, and the AC-side power commands P_ref and Q_ref, generates the system’s grid switch control signal S_swcmd and the AC equivalent electromotive force reference values e_jref.

3.2. Supercapacitor Power Distribution Strategy

According to Equation (9), ignoring the response time of the voltage–current double loop, the relationship between the output power and the voltage frequency variation at the grid connection point is given by:

$$\Delta P_{\mathrm{e}}=-\left(Js+D_{\mathrm{p}}\right)\Delta {\omega }_{\mathrm{HSC}}$$

(14)

To mitigate battery power and slow down aging, the high-frequency components of the power are allocated to the supercapacitor. At the same time, considering the health management of the supercapacitor, the low-frequency response components of the supercapacitor are appropriately increased. Based on Equation (14), the reference value for DC-side SC power is given by:

$$P_{\mathrm{SCref}}={\displaystyle \frac{K_{\mathrm{H}}\frac{J}{D_{\mathrm{p}}}s+K_{\mathrm{L}}}{K_{\mathrm{H}}\frac{J}{D_{\mathrm{p}}}s+1}}{P}_{\mathrm{e}}$$

(15)

where K_H and K_L are the high-frequency and low-frequency compensation coefficients for the supercapacitor, respectively. P_SCref is the discharge power reference value.

The voltage state coefficient αSC is used as the coefficient configuration basis, defined as:

$${\alpha }_{\mathrm{SC}}={\displaystyle \frac{U_{\mathrm{SC}}-U_{\mathrm{SC}\min }}{U_{\mathrm{SC}\max }-U_{\mathrm{SC}\min }}}$$

(16)

where U_SCmax and U_SCmin are the upper and lower boundaries for the supercapacitor’s operating voltage. α is defined to range from 0.05 to 0.95 for the working interval, with 0.25 to 0.75 being defined as the healthy interval.

Based on the inertia and damping coefficients of the active ring, as well as the battery power suppression time constant T_B, the coefficient K_H is configured as:

$$K_H=\left\{\begin{array}{c}0, {\displaystyle \frac{d{P}_e}{dt}}<0\cap {\alpha }_{SC}\ge 0.95\\ 0, {\displaystyle \frac{d{P}_e}{dt}}>0\cap {\alpha }_{SC}\le 0.05\\ T_B{\displaystyle \frac{D_p}{J}}, else \end{array}\right.$$

(17)

For the pre-set supercapacitor ratio K_L0, to reduce the supercapacitor’s operation time in non-healthy intervals, the coefficient K_L is configured as:

$$K_L=\left\{\begin{array}{c}{\displaystyle \frac{{\alpha }_{SC}-0.75}{0.2}}{K}_{L0}, P_e>0\cap {\alpha }_{SC}>0.75\\ {\displaystyle \frac{0.25-{\alpha }_{SC}}{0.2}}{K}_{L0}, P_e<0\cap {\alpha }_{SC}<0.25\\ 0, else \end{array}\right.$$

(18)

The DC-side SC power control block diagram for the MMC-HESS is shown in Figure 9. Based on the AC-side output power P_e and the supercapacitor compensation coefficients K_H and K_L, the supercapacitor power reference value P_SCref is calculated. This is then divided by the DC voltage U_SC, and the value is split equally across the three phases to obtain the circulating DC reference value i_DCjref. The difference between this and the actual circulating current i_cirj is processed by a PI controller to derive the DC equivalent electromotive force reference value e_DCjref.

3.3. SOC Balancing Strategy

3.3.1. Bridge Arm SOC Balancing and Circulating Current Control

According to Equation (3), a phase-to-phase power correction value is introduced into the circulating DC component i_DCjref in the DC-side SC power control to balance the phase-to-phase SOC.

According to Equation (4), an AC fundamental frequency component i_ACj, in phase with the AC-side voltage, is introduced to balance the SOC between the upper and lower arms of the system. The zero-sequence component of the circulating current introduces a power fundamental frequency component on the DC side. Therefore, after removing the zero-sequence component from the reference value, the fundamental frequency circulating current component is controlled using a resonant PR controller.

Figure 10 illustrates the circulating current control model, which comprises the circulating DC control module and the fundamental frequency control module. The circulating current control strategy determines the system’s circulating current reference value based on the AC output power P_e and the arm currents i_pj and i_nj, as well as the average SOC values S_pj and S_nj of each arm. Subsequently, the DC equivalent electromotive force reference value e_DCjref is derived.

3.3.2. SOC Balancing and Voltage Modulation Within the Bridge Arm

The SOC balancing control within the bridge arm is shown in Figure 11. The number of submodules to be activated N is determined by the ratio of the bridge arm voltage reference U_armref to the battery’s rated voltage V_d. The deadband (DB) defines the permissible SOC difference between two batteries. When the SOC difference does not exceed the deadband, the batteries are sorted according to their current state. The calculation formula for U_armref is shown in Equation (19).

$$U_{\mathrm{armref}}=\underset{\begin{array}{l}{K}_{\mathrm{p}}=-1\\ K_{\mathrm{n}}=1\end{array}}{\underbrace{K_{\mathrm{p},\mathrm{n}}}}{e}_{j\mathrm{ref}}+\underset{e_{\mathrm{dc}j\mathrm{ref}}}{\underbrace{u_{\mathrm{dc}j\mathrm{ref}}+u_{\mathrm{ac}j\mathrm{ref}}}}$$

(19)

3.4. Overall System Control Model

Figure 12 shows system control architecture with AC/DC power regulation and submodule modulation. AC-side HSC control enables frequency support and grid synchronization during faults/transients, while generating grid-connect/islanding signals. DC-side direct power control manages supercapacitors, coordinating with AC-side strategies to optimize storage dispatch and mitigate battery aging. Submodule control implements SOC balancing for battery stacks, enhancing utilization efficiency.

4. Discussion

To verify the HSC-MMC-HESS topology and control strategy mentioned above, a hardware-in-the-loop experimental model was constructed based on the experimental platform shown in Figure 13; the controller model is Texas Instruments TMS320F28335. The system parameters are listed in

Table 2. HSC-controlled MMC-HESS Parameters.

Structure	Parameter			Label	Configuration
Grid	Voltage level/kV			Vbase	10
	Rated frequency/Hz			f0	50
	Rated capacity/(MV·A)			Sbase	10
	Line inductance (p.u.)			Ls	0.2
	Line resistance (p.u.)			Rs	0.002
LC filter	Series inductance (p.u.)			Lf	0.2
	Inductive parasitic resistance (p.u.)			Rf	0.02
	Parallel capacitance (p.u.)			Cf	0.02
	Parallel parasitic resistance (p.u.)			RCf	0.1
Bridge arm structure	Submodules per bridge arm			N	8
	Bridge arm inductance/mH			L0	12
	Bridge arm resistance/Ω			R0	0.1
	SM internal capacitance/mF			C0	8.4
Battery	Rated voltage/kV			VBr	2.5
	Rated capacity/(A·h)			QBr	20
	SOC Initial value/%	A phase	upper	SOCpa	45
			lower	SOCna	47
		B phase	upper	SOCpb	51
			lower	SOCnb	49
		C phase	upper	SOCpc	53
			lower	SOCnc	55
DC-side supercapacitor	Total series capacitance/F			CSC	1
	Upper working voltage limit/kV			USCmax	11
	Lower working voltage limit/kV			USCmin	1
HSC power loop	Virtual inertia (p.u.)			J	2.5
	Damping coefficient (p.u.)			Dp	100
	PLL component ratio coefficient (p.u.)			Kp	10
Voltage inner loop	Proportional coefficient (p.u.)			Kpv	0.5
	Integral coefficient (p.u.)			Kiv	500
Current inner loop	Proportional coefficient (p.u.)			Kpi	1
	Integral coefficient (p.u.)			Kii	200
SC power	High-frequency component compensation coefficient (p.u.)			KH	5
	Low-frequency component compensation coefficient (p.u.)			KL0	0.5
DC current loop	Proportional coefficient (p.u.)			KpDC	0.5
	Integral coefficient (p.u.)			KiDC	100
SOC balance	Inter-phase SOC balancing coefficient (p.u.)			Kph	50
	Bridge arm SOC balancing coefficient (p.u.)			Karm	40
	DC component limit of circulating current (p.u.)			IDCcir_lim	3
	AC component limit of circulating current (p.u.)			IACcir_lim	2
	SOC dead zone/%			DB	0.1

. The voltage and current waveforms observed by the oscilloscope under normal operation are shown in Figure 14.

4.1. Inertia, Frequency Support, and Power Distribution

To verify the inertia and frequency support capabilities of the HSC-MMC-HESS and the feasibility of the power distribution strategy between energy storage and supercapacitors, a load step change experiment was conducted on the above-mentioned experimental platform. The grid-side power source simulates a synchronous machine, where J and D_p are 50 and 500, respectively. The initial load of the grid side is 1 p.u., and it steps to 1.2 p.u. and 0.8 p.u., respectively, for 1.5 s before recovery. The MMC machine-side load is 0.8 p.u., and the power command is 0.8 p.u. Under grid-connected conditions, the output power profile during load step changes is depicted in Figure 15, while the corresponding frequency variations are shown in Figure 16. For comparison with the grid-connected scenario, the frequency response under islanded operation during the same load transient is also presented in Figure 16.

From Figure 15, it can be seen that after a load step change on the grid side, the transient change in MMC output power has inertia and damping characteristics, providing or absorbing about 0.016 p.u. of active power to or from the grid. The inertia and frequency support capability are effectively verified. From Figure 16, it can be seen that the frequency variation of the grid-side power source is reduced after connection. When the load increases by 0.2 p.u., due to the supercapacitor voltage state coefficient α > 0.75 and its discharging state, the supercapacitor takes on part of the low-frequency power component. When α > 0.95, the maximum share reaches 0.5, which is the set K_L0. The power distribution strategy allows the supercapacitor to effectively handle high-frequency power components and some low-frequency power components while preventing overcharging or over-discharging, stabilizing the battery output power.

4.2. Low-Voltage Ride-Through and Grid Connection/Disconnection Switching

To verify the low-voltage ride-through switching function of the MMC-HSC and the grid connection and disconnection switching function, a voltage drop experiment was performed on the above-mentioned experimental platform. The grid-side load is 1.2 p.u., the machine-side load is 0.4 p.u., and the MMC active power command is 0.6 p.u. The voltage drops to 0.8 p.u. and 0.1 p.u., respectively, and recovers after 1 s. The output power and voltage curves are shown in Figure 17, and the voltage and current waveform when the grid voltage drops to 0.1 p.u. is shown in Figure 18.

From Figure 17a, when the voltage drops to 0.8 p.u., the system switches to current control, and the current amplitude does not reach the limit of 1.2 p.u.; so, the active power remains at 0.6 p.u. After 1 s, the voltage recovers, and the system exits the current control mode. From Figure 17b, when the voltage drops to 0.1 p.u., the output is reactive current, which compensates the grid voltage to 0.28 p.u. The current amplitude reaches the limit, and the active power is constrained. According to Equation (12), the system operates in islanded mode for about 0.79 s, with an output power of 0.4 p.u. from the machine-side load. After 1 s, the voltage recovers, and the MMC continues to grid connect after pre-synchronization. Based on the results above, the system can automatically and reliably switch between low-voltage ride-through, normal grid connection, and disconnection modes.

4.3. SOC Balancing Control

In the above experiment, the SOC balancing control was operating, and the SOC waveform is shown in Figure 19.

From Figure 19, it can be seen that after limiting the two components of the circulating current, the SOC balancing between phases and between the upper and lower bridge arms is achieved after approximately 23 s and 33 s post-startup, respectively. Through the intra-bridge arm submodule SOC balancing control, the SOC is maintained in a state of basic equilibrium within the deadband range.

5. Conclusions

The proposed HSC-MMC-HESS topology with hybrid synchronous control demonstrates inherent inertia support and frequency regulation capabilities, effectively enhancing grid stability through integrated LVRT functionality that enables reactive voltage support during faults and smooth grid–islanding transitions. By combining SOC-based power allocation with energy storage coordination, the system optimizes supercapacitor–battery synergies to improve utilization rates while mitigating device aging, showing strong potential for medium-voltage distribution network applications.

Future work can address computational complexity from massive submodules in large-grid applications, while renewable integration scenarios require adaptive filtering to mitigate supercapacitor aging caused by power fluctuation-induced frequent cycling.