1. Introduction
The growing computational demands of modern applications—driven by large-scale neural models, image processing, cryptographic computation, high-performance arithmetic, and the scalability requirements of distributed systems—have motivated the development of new massively parallel computational models.
Membrane computing, introduced by Păun [
1], is a hierarchical, bio-inspired model of distributed computation whose Turing-complete operational semantics offer a structured alternative to classical sequential architectures, while also incorporating a flexible hierarchical organization and inherent multiset dynamics that implement aggregation and annihilation in a natural way. Within this framework,
SNP [
2,
3] and
SNQ systems [
4] provide neuron-like computational abstractions in which arithmetic behavior is realized through the application of spike-handling rules. Although arithmetic can be expressed in SNP and SNQ systems, their usual dependence on selective-mode rule application restricts parallelism and leads to significant computation times [
5,
6,
7,
8]. In modular arithmetic, some existing systems compute (
) via iterative subtraction [
9], leading to execution times that depend on operand size and thereby limit scalability. These limitations prevent constant-time execution and significantly restrict the modular reuse of arithmetic components.
Recent research has further expanded the theoretical and practical scope of spiking neural and membrane computing models, particularly in relation to arithmetic processing and structured computational design. Comprehensive surveys have highlighted the sustained development of spiking neural P systems (SN P systems), including investigations into normal forms, homogeneous structures, software tools, and emerging research directions. These studies provide an updated view of the theoretical foundations and ongoing evolution of SN P systems as a mature paradigm within membrane computing and natural computing research [
10].
In parallel, increasing attention has been devoted to implementation-oriented aspects of membrane computing models and their potential for massively parallel computation. Hardware-focused analyses emphasize the suitability of membrane-based computational paradigms for FPGA- and GPU-based realizations, as well as their relevance for high-performance arithmetic and data-intensive applications. Such work underscores the importance of bio-inspired distributed models as viable alternatives to classical sequential architectures in contexts requiring scalable and modular arithmetic computation [
11].
Within this broader context, several works have addressed the construction of arithmetic components in spiking neural P systems. Implementations of binary adders and related arithmetic circuits demonstrate the feasibility of designing practical arithmetic modules using spike-based representations and neuron-level rule dynamics, with potential applications in cryptographic and hardware-oriented domains [
12]. At the same time, recent extensions of SN P systems have explored enriched rule semantics, including stochastic and probabilistic firing mechanisms, further expanding the modeling and computational capabilities of neural membrane systems [
13]. These developments reflect a growing interest in efficient arithmetic processing and modular computational design within membrane computing.
Despite these advances, most existing approaches rely on selective or sequential rule application and often exhibit execution times dependent on operand magnitude or structural complexity. Consequently, the development of compact and reusable arithmetic kernels operating in constant time, while maintaining structural simplicity and scalability, remains an open challenge in the design of membrane–neural computational architectures.
These considerations motivate the need for architectures using exhaustive semantics, together with biologically inspired mechanisms like spike aggregation, spike/anti-spike annihilation, and multiset-based computation, as these features simplify arithmetic design and lower neuron counts.
To overcome these limitations, we propose Hybrid Membrane–Neural (HMN) P systems, combining membrane hierarchies with exhaustive rule application and spiking neural computation. This integration yields compact, reusable arithmetic kernels operating in constant time, independent of operand values. The architecture includes:
A modular-reduction membrane , which evaluates in constant time using a single neuron with exhaustive semantics. This membrane is a fundamental primitive for all modular operations.
A synchronization membrane , designed to temporally synchronize incoming spike multisets before processing. This mechanism is needed for asynchronous operands and adds at most two steps: query and synchronized emission.
Signed arithmetic membranes and , which compute signed multiplication and division via spike/anti-spike encoding.
Composite modular kernels and , constructed by hierarchically composing the preceding modules within the membrane structure.
A notable property of HMN systems is that addition and subtraction operate without explicit membranes, emerging naturally from spike aggregation and spike/anti-spike annihilation. Consequently, specialized architectures are only necessary for multiplication, division, and modular reduction.
By integrating execution under exhaustive semantics, hierarchical modular composition, and bio-inspired spike/anti-spike interaction within multiset dynamics, the HMN P systems perform all modular and non-modular arithmetic kernels in constant time, without dependence on operand size.
This level of efficiency makes it attractive for diverse application domains, such as elliptic-curve arithmetic, error-correcting codes, DSP, machine-learning primitives, finite-field computation, cryptographic hardware, and bio-inspired computational architectures, and for the systematic development of scalable arithmetic libraries within membrane computing.
Beyond the specific constructions presented, the Hybrid Membrane–Neural (HMN) P system introduced in this work is intended as a reusable architectural framework for constant-time arithmetic in membrane–neural computation. By enabling modular composition of arithmetic kernels under exhaustive semantics and hierarchical membrane organization, the HMN model provides a structured basis for scalable arithmetic design in bio-inspired distributed computing. This perspective positions HMN P systems not only as individual constructions but as a foundation for the systematic development of arithmetic and algebraic components within membrane computing.
The organization of the paper is as follows.
Section 2 reviews the preliminaries on Spiking Neural P (SNP) systems, SNQ systems, and exhaustive semantics.
Section 3 introduces the Hybrid Membrane–Neural (HMN) P systems, while
Section 4 describes the arithmetic-kernel designs and their membrane-based implementations.
Section 5 provides a detailed comparative analysis of the arithmetic designs formulated within the HMN architecture. Finally,
Section 7 summarizes the primary contributions of the work and highlights promising directions for future research.
2. Preliminaries
2.1. Spiking Neural P Systems (SNP Systems)
Spiking Neural P (SNP) systems [
2] are computational abstractions of biologically inspired spiking networks. Information is represented by spike symbols, and computation results from the rule-based consumption, generation, and transmission of spikes across directed synaptic pathways.
An SNP system extended to multiple spike types [
14] is formally specified as
where
O is a finite alphabet of spike and anti-spike symbols representing multiple spike types; each neuron
is equipped with an initial spike multiset and a finite set of firing and forgetting rules; and
is the set of directed synapses. A firing rule
consumes the multiset
u, validates the enabling condition
E, and releases the multiset
v after delay
d. Forgetting rules delete a nonempty multiset of spikes, producing no output. Neurons evolve in synchrony under a global clock, with rule application limited to one per step. The computation halts once no rule remains applicable or once the output neuron emits its final spike.
2.2. Spiking Neural P Systems with Communication on Request (SNQ Systems)
SNQ systems [
4] enhance the SNP model by enabling neurons to request spikes from presynaptic neurons during rule execution. Rules are expressed as
, where
E represents a regular expression and
w specifies a nonempty multiset. When a rule fires, the neuron requests the multiset
w from every neuron
for which
. Requested spikes are conceptually replicated, enabling all requests to be fulfilled. As in SNP systems, the evolution proceeds synchronously, and neurons may apply only one rule per step. Computation halts when the system reaches a configuration in which no rule is enabled.
2.3. Exhaustive Semantics in SNP Systems
Under the
exhaustive semantics model [
15], a rule of the form
applied to a neuron containing
k spikes of type
a fires
times, producing
spikes in parallel. Such massively parallel rule execution treats spike multisets as divisible computational resources, leading to a marked improvement in computational throughput.
This property makes exhaustive semantics an effective basis for arithmetic computation, due to its capacity for parallel multiset processing and spike interactions, leading to reductions in neuron count and computation time—advantages leveraged by the HMN architecture introduced in the following section.
3. Hybrid Membrane–Neural P Systems
Classical cell-like P systems [
1] are based on a hierarchical membrane structure, where multisets of objects evolve through the application of rules operating within a hierarchy of nested regions. In SNP systems, biologically inspired neuronal units exchange multisets of spikes through directed synapses, and computation is performed through the application of firing and forgetting rules. SNQ systems enhance this model by enabling neurons to
request spikes from neighboring neurons instead of only receiving transmitted spikes.
The HMN model presented in this work unifies these principles into a single architecture by preserving the hierarchical membrane structure and introducing multiset-driven spike/anti-spike dynamics alongside exhaustive neuronal rule execution. This synergy yields compact arithmetic modules and enables arithmetic operations to execute in constant time.
4. Arithmetic-Kernel Designs
This section outlines the arithmetic kernels forming the computational backbone of the Hybrid Membrane–Neural P system (HMN P system). The framework supports signed multiplication and signed division, each offered in modular and non-modular form through the membranes , , , and . Together with these operator-specific kernels, two auxiliary modules play a key role in the architecture:
Modular-reduction membrane , responsible for computing the non-negative residue from a multiset encoding a signed integer. It serves as a reusable primitive that can be composed with other modular membranes.
Synchronization membrane , which collects and synchronizes spikes arriving at different computation steps. It guarantees that the arithmetic kernels receive operands as fully synchronized multisets, incurring at most two extra steps (query and synchronized emission).
Because addition and subtraction emerge naturally from spike aggregation and the annihilation of spike/anti-spike pairs, there is no need for explicit membrane-level modules implementing these operations. Instead, addition and subtraction occur naturally from the spiking-based semantics that govern the HMN P system.
The subsections that follow outline the design of each arithmetic kernel and illustrate how the modular composition of low-level membranes (e.g., , , , ) yields compact and reusable architectures. Each kernel is realized through a compact membrane–neuron architecture operating under exhaustive semantics and exhibiting constant-time execution. Their simplicity, reusability, and structural uniformity enable seamless integration into advanced arithmetic constructions arising in elliptic-curve computation, cryptography, finite-field arithmetic, neuromorphic architectures, DSP, and low-power embedded systems.
4.1. Membrane
This membrane, denoted by
, is initially empty and serves exclusively as a spike-storage membrane, passively collecting all incoming spikes. It receives multisets of the form
, which are accumulated in neuron
while preserving both spike type and multiplicity. This membrane does not emit any output spikes. Its complete architecture is shown in
Figure 1.
4.1.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3, the container membrane
constitutes a specific instance of the system
Working alphabet is given by: .
Membrane labels are: ; membrane 1 acts as the skin membrane.
Membrane structure: , membrane 1 contains no child membranes, i.e., .
The neuron set is , the single neuron of .
Initial multiset: , indicating that the neuron may accumulate spikes or anti-spikes of type for .
Rule set: .
Synapses: , .
Output membrane: , as no output spikes are produced.
4.1.2. Computation Time
Container membranes do not introduce additional computation steps, as their internal neuron applies no rules and merely accumulates incoming spikes.
4.2. Membrane
The membrane
contains the container membranes
, together with the query membrane
. Its function is to synchronize the spikes accumulated in the container membranes, independently of the simulation steps at which they are received. The number of container membranes matches the number of input multisets. A schematic representation is shown in
Figure 2.
4.2.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3, the system
is instantiated as a specific instance of the general model
The working alphabet is given by .
The membrane labels are , with membrane 1 as the skin membrane, membranes 2–m as container membranes, and membrane contains the synchronization neuron .
The membrane structure is specified as , with and for .
Each membrane has one neuron: ; for .
Initial multisets are for ; the synchronization neuron starts empty, .
There are no internal synaptic connections: for all j.
External synapses allow the synchronization neuron
to send the synchronized spikes to the
m target neurons:
and
for all
. Here,
is the input neuron of membrane
that receives the synchronized multiset from
.
The synchronization neuron contains the SNQ request rule
collecting the required spike multisets from the container membranes via SNQ request rules.
Once all queries are fulfilled,
emits the synchronized multiset via its synaptic SNP-like rules.
each rule is associated with a synapse
and is applied under exhaustive semantics in a single computation step.
Since no output is produced, .
In accordance with the SNQ semantics introduced by Păun et al. [
4], SNQ request rules in the synchronization neuron actively request and transfer the specified spike multisets from the container membranes to
in a single computation step. Once all requested multisets have been collected, synaptic SNP-like rules are applied to emit the synchronized spikes toward their target neurons under exhaustive semantics.
Once all SNQ queries have been satisfied, retrieves the spike multisets from , accumulates them in , and emits the synchronized operand via rules . If multiple upstream modules provide spikes of the same type, the corresponding container membranes accumulate them independently, while the synchronization neuron queries all containers to verify completeness before emitting the synchronized output.
4.2.2. Computation Time
When
is employed, two additional steps are required: the SNQ query step and the subsequent synaptic emission of the synchronized spikes, yielding a total of
4.2.3. Input Synchronization
All arithmetic membranes assume synchronized input. If multisets arrive at different times, can be used as a preprocessing step, adding at most two steps (query and synchronized emission) without changing the target membrane’s internal structure.
4.3. Membrane
This membrane, denoted as
, performs modular addition or subtraction of a single signed value. Addition and subtraction are performed implicitly and therefore do not require explicit rules: two membranes sending
and
to a common target, the bio-inspired mechanism aggregates them as
. Similarly, the neuron performs mutual annihilation upon the simultaneous reception of
and
, yielding
when
and
otherwise [
16,
17]. Thus, this membrane receives
if
and
if
. This membrane computes the modular reduction
independently of the spike type
i; the result is emitted using the same spike type that was received (see
Figure 3).
4.3.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3, the membrane
is a particular instance of the general model.
The working alphabet is .
, defining a single cell-like membrane with structure .
The membrane has a single neuron , acting as both input and output.
The neuron
, where:
and
, where:
and are parametric rule schemata defined for all and are counted as single rule types in the structural characterization.
The membrane has no synapses, i.e., .
The output membrane is .
4.3.2. Operational Semantics
The membrane computes as follows:
In neuron , the value b equals the total number of spikes received in the same computation step. If spikes of type or do not arrive simultaneously at , a synchronization membrane collects same-type spikes and releases them synchronously in one step, introducing two additional steps (query and transmission).
Rules and are applied exhaustively, i.e., repeatedly as long as they are applicable, to delete all full multiples of p encoded in or . Consequently, when no further application of or is possible, the remaining multiplicity is necessarily .
Only after the exhaustive application of and terminates, exactly one of or is applied, emitting and preserving the input spike type.
4.3.3. Computation Time
Under exhaustive semantics, the computation completes in at most two steps: optional elimination via or , followed by a single application of or .
4.4. Membrane
Within the Hybrid Membrane–Neural P system model, extends with a preliminary synchronization stage that temporally aligns incoming spikes prior to modular reduction.
4.4.1. Formal Definition
If the spikes encoding
b do not arrive simultaneously at
, a synchronization stage is required. Accordingly, we define the composite system
which combines the synchronization module
and the modular-reduction module
under a common skin membrane. Formally:
is the unified alphabet.
, where membrane 1 is the skin, and membranes 2 and 3 correspond to and , respectively.
, where membrane 2 is responsible for the synchronization stage, while membrane 3 performs the modular-reduction computation.
and .
The neurons are inherited from the corresponding component modules: and , while the skin membrane contains no neurons.
External synapses:
transmitting the synchronized multiset from membrane 2 to membrane 3.
The global rule set is given by
The output membrane is .
4.4.2. Computation Time
The architecture operates in two phases:
synchronizes the spikes in two steps, after which
performs modular reduction in two additional exhaustive steps. Hence,
4.5. Membrane for Signed Multiplication
This membrane, denoted
, computes the signed product of two operands
x and
y within the Hybrid Membrane–Neural architecture. The input is encoded as spike multisets
or
(multiplicand) and
or
(multiplier), where
are the spike-based instantiations of the abstract operands
. The dual-spike representation
enables direct handling of signed integers without auxiliary sign membranes (see
Figure 4).
4.5.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3,
is defined as an instance of the general HMN P system.
Formally:
is the working alphabet.
with membrane structure .
, as no internal submembranes are present.
The membrane contains a single neuron , acting as both input and output.
and .
The initial multiset encodes the signed operands as .
The rule set
implements the four sign combinations
,
,
and
under exhaustive semantics. In a single computation step, all multiplier spikes (
or
) are consumed, and
spikes of type
or
are emitted according to the resulting sign.
The output membrane is .
4.5.2. Computation Time
All rules are applied under exhaustive semantics within a single computation step, yielding .
If the spike multisets encoding do not arrive simultaneously, a preceding synchronization phase may be used to collect and synchronize all same-type spikes before delivery to . This optional preprocessing adds at most two additional steps (query and synchronized emission), without modifying the internal structure of .
The dual-spike representation (, ) allows the membrane to multiply signed integer values directly through its spiking dynamics, without requiring an additional sign-handling membrane. This enhances the compactness and modularity of the system, allowing the same computational structure to be reused in higher-level tasks such as modular multiplication or differential addition.
4.6. Membrane for Signed Division
This membrane, denoted
(see
Figure 5), computes the signed division of two operands
x and
y within the Hybrid Membrane–Neural framework. The dividend
x is encoded by a spike multiset
or
, where
c is the spike-based instantiation of
x, while the divisor
y is encoded by a single spike whose type index represents its magnitude and whose polarity represents its sign. Specifically, a positive divisor of magnitude
d is encoded by
, whereas a negative divisor of magnitude
d is encoded by
.
The membrane emits or , where , with the output polarity encoding the sign of the quotient. As in , the dual-spike representation allows direct manipulation of signed operands.
4.6.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3,
is instantiated as a specific instance of the general HMN P system.
Formally:
is the working alphabet. Spike types denoted by and are mnemonic names for specific elements of O, reserved to encode divisor magnitudes and assumed to be disjointed from those used for operand-value encoding.
with membrane structure .
, since membrane 1 contains no submembranes.
The membrane contains a single neuron , acting as both input and output.
The initial multiset encodes the signed operands as
where
and exactly one of
or
is present, and exactly one of
or
is present.
The rule set consists of the following finite schema, defined for each
:
Each rule is applied under exhaustive semantics. At each application, d spikes encoding the dividend magnitude are consumed, and one output spike is produced, while the divisor spike is preserved since it appears only in the enabling condition. Under exhaustive execution, the enabled rule is applied exactly times within a single global step, yielding the correct integer quotient.
and .
The output membrane is .
4.6.2. Computation Time
Under exhaustive semantics, all applicable rules fire within a single computation step.
If the spike multisets encoding
do not arrive simultaneously, a preceding synchronization membrane
may be employed to temporally synchronize all spikes and deliver them in a single step to
. This optional preprocessing adds at most two additional steps (query and synchronized emission), without modifying the internal structure of
.
Remark 2. The division membrane assumes a nonzero divisor () and computes the integer quotient .
4.7. Membrane
This membrane, denoted
, computes the signed modular product
by composing two previously defined arithmetic modules: the signed multiplication membrane
and the modular-reduction membrane
. In this architecture, the output of
is directly fed as input to
, with both modules contained within the skin membrane (see
Figure 6). This modular design avoids rule duplication and supports the reuse of low-level arithmetic components.
4.7.1. Formal Definition
Within the HMN P system model described in
Section 3,
is defined as an instance of the Hybrid Membrane–Neural P system.
Formally:
is the working alphabet.
, where membrane 1 is the skin and membranes 2 and 3 instantiate and , respectively.
The membrane structure is .
The membrane contents satisfy , and .
Each internal membrane inherits its corresponding neuron set:
The skin membrane 1 contains no neurons.
Internal synapses are inherited from the component modules.
External synapses are defined by
transmitting the output multiset of
to the input neuron of
.
The global rule set is defined as .
The output membrane is .
4.7.2. Computation Time
All submembranes operate under exhaustive semantics; consequently,
If the spike multisets corresponding to the operands arrive at at different computation steps, a preceding synchronization membrane can be employed as a preprocessing module to collect and temporally align all spikes of the same type before they are delivered to the arithmetic kernel. This optional preprocessing introduces at most two additional steps—corresponding to the SNQ query and the synchronized emission—without modifying the internal structure of or .
This compositional approach preserves modularity, reduces rule overhead, and enables the direct pipeline integration of signed multiplication and modular reduction within the HMN P system framework.
4.8. Membrane
This membrane, denoted
, computes the signed modular division
by composing two arithmetic modules: the division membrane
and the modular-reduction membrane
. The output spikes produced by
are delivered directly to
, with both modules enclosed within the skin membrane (see
Figure 7). This modular scheme avoids rule duplication and enables the reuse of low-level arithmetic components.
4.8.1. Formal Definition
Within the Hybrid Membrane–Neural P system model described in
Section 3, we instantiate the kernel
as a specific instance of the HMN P system.
Formally:
is the working alphabet.
, where membrane 1 is the skin and membranes 2 and 3 implement and , respectively.
The membrane structure is .
The membrane contents satisfy , , .
Each internal membrane inherits its corresponding neuron set:
The skin membrane 1 contains no neurons.
Internal synapses are inherited from the component modules:
External synapses are defined by
transmitting the output multiset of
to the input neuron of
.
The global rule set is defined as
The output membrane is .
4.8.2. Computation Time
All submembranes operate under exhaustive semantics; consequently,
When the spike multisets corresponding to the operands are not delivered simultaneously to , a preceding synchronization membrane may be employed to synchronize all same-type spikes prior to their delivery to the arithmetic kernel. This optional preprocessing introduces at most two additional steps—corresponding to the SNQ query and the synchronized emission—without modifying the internal structure of or .
This compositional design preserves modularity, minimizes redundancy, and enables direct coupling between division and modular reduction within the HMN P framework.
4.9. Worked Examples
In all examples, spike aggregation and spike–anti-spike annihilation follow the standard SNP semantics, where spikes of the same-type aggregate by multiplicity and simultaneous occurrences of
and
cancel out pairwise [
16,
17].
This subsection provides fully developed numerical examples that illustrate the step-by-step dynamics of the main arithmetic cores introduced in
Section 4.5,
Section 4.6,
Section 4.7 and
Section 4.8. The goal is to make the exhaustive execution semantics explicit by showing how spike and anti-spike multiplicities evolve at each global computation step for concrete signed operands.
Example 1 (Signed Modular Reduction)
. Consider the membrane with modulus . Let , encoded as seven spikes of type . The initial configuration of the unique neuron isUnder exhaustive semantics, rule is applied once, removing one full multiple of p and leaving two spikes. Since no further application of is possible, the reduction phase terminates, and rule emits the remainder:The configuration-level evolution is:confirming that the membrane correctly computes in a single global computation step. Example 2 (Signed Multiplication)
. Let and . In the multiplication membrane , the operands are encoded as multisets of spikes and anti-spikes of types (for x) and (for y). The initial multiset isUnder exhaustive semantics, only the rule corresponding to the case is enabled:This rule is applied once for each available , i.e., times, producing 12
spikes of type in a single global step:The configuration-level trace is:confirming that and that the output polarity matches the sign of . Example 3 (Signed Division)
. Let and , hence under truncation-based integer division. The initial configuration of isThe only enabled rule iswhich is applied exhaustively. Each firing consumes two dividend anti-spikes and produces one output anti-spike, while the divisor spike is preserved. The rule is applied times, yieldingThe configuration-level trace is:which makes explicit the truncation-based quotient and the correct propagation of the output sign. Example 4 (Signed Modular Multiplication)
. Let , , and . The multiplication membrane first computes , emitting . This multiset is then transmitted to the modular-reduction membrane , where exhaustive reduction rules consume 5
anti-spikes per application. Two full reductions are applied, leaving a remainder of 2
anti-spikes:Thus, the system correctly computes , which is congruent to 3 modulo 5 under the adopted signed encoding, illustrating how previously defined arithmetic cores are composed without modifying their internal rule sets.
5. Comparative Analysis of Arithmetic Designs in the HMN Framework
Throughout this section, execution times are measured in global HMN computation steps under exhaustive semantics and are independent of the magnitude of the operands. They depend only on the fixed architecture and composition of the corresponding arithmetic kernels.
This section presents a comparative evaluation of arithmetic modules within the Hybrid Membrane–Neural (HMN) P system model under exhaustive semantics. We report neuron counts and performance in terms of simulation steps for the fundamental arithmetic modules introduced in
Section 4, and contrast them with representative arithmetic constructions from the SNP and SNQ literature.
5.1. Comparison with Prior Work
Early arithmetic constructions in SNP systems [
5] implement addition, subtraction, multiplication, and division using unary representations. However, they exhibit operand-dependent computation times, require multiple auxiliary neurons, and do not provide direct support for signed integers. Subsequent approaches [
6,
17] reduced neuron counts or relaxed timing constraints, but remained dependent on a large number of rules whose execution time grows linearly with respect to the operand values. In particular, arithmetic constant-time execution limits their scalability as reusable arithmetic components. Single-neuron arithmetic constructions [
18] achieved the lowest structural complexity, but did not eliminate operand-dependent execution. Binary-encoded arithmetic constructions [
8] provided explicit complexity bounds in terms of bit-length, but still required a number of simulation steps linear in the operand bit-length. For modular arithmetic, the only previous system supporting all four operations is [
9], where repeated subtraction cycles result in data-dependent computation times.
In contrast, the HMN arithmetic kernels operate in constant time for both modular and non-modular arithmetic, require the fewest neurons among existing designs, and natively support signed values via dual-spike encoding.
5.2. Summary of Comparative Results
To facilitate interpretation, we note that the compared constructions differ along several orthogonal dimensions that are not always presented uniformly in the original sources, including: (i) the underlying computational model (SNP, SNQ, or HMN), (ii) the data encoding strategy (unary multiplicity-based, binary, or multi-type spike encoding), and (iii) the assumed temporal semantics (sequential, synchronous, or exhaustive execution). For this reason, these dimensions are discussed explicitly in the text accompanying the tables, rather than being collapsed into a single tabular comparison.
Specifically, the comparison text preceding and following the tables explicitly addresses these dimensions by discussing, for each group of related works, the underlying system model, the adopted data encoding strategy, and the assumed execution semantics.
The following tables summarize and compare neuron counts and simulation-step complexities for non-modular and modular arithmetic circuits across SNP, SNQ, and HMN-based systems.
Table 1 and
Table 2 summarize the structural and temporal costs of non-modular arithmetic operations, quantified in terms of neuron counts and simulation steps under exhaustive semantics, respectively. Unless otherwise specified in the cited works, all designs assume that operand spikes are delivered synchronously to the corresponding neurons, a common convention in SNP and SNQ arithmetic systems that eliminates the need for explicit synchronization components. For non-modular arithmetic, addition and subtraction are realized intrinsically through spike aggregation and spike–anti-spike annihilation, requiring no internal computation steps and only a single neuron. Addition and subtraction require no internal computation steps, as spike aggregation and spike/anti-spike annihilation occur implicitly upon arrival. Multiplication and division are performed by a single neuron and terminate in one simulation step under exhaustive semantics. Consequently, the HMN arithmetic kernels achieve constant-time execution while minimizing neuron usage.
5.2.1. Modular Arithmetic Circuits over
Entries marked as “–” or “n/a” indicate that the corresponding metric is not reported or not defined in the original source. This occurs either because the arithmetic operation is not supported in that construction or because the underlying model does not provide a directly comparable notion of simulation steps. In particular, the SNQ-based design of Jiang et al. [
7] does not include a division module, and no neuron count or execution time is therefore reported for this operation in
Table 1 and
Table 2.
Table 3 and
Table 4 present the corresponding results for modular arithmetic over
, the Galois field of order
p, where
p is a prime number.
The modular-reduction kernel (operations (Add mod p) and (Sub mod p)) is realized using a single neuron and completes in two simulation steps under exhaustive semantics. Modular multiplication and division are constructed compositionally by combining this kernel with the associated non-modular arithmetic modules, resulting in architectures with two neurons and a total of three simulation steps. If operand spikes are not synchronously available, an auxiliary synchronization membrane may be introduced as a preprocessing stage; this mechanism is accounted for separately and does not alter the intrinsic structural or temporal complexity of the core arithmetic modules.
Overall, the tables indicate that the proposed HMN arithmetic kernels achieve constant-step execution for both modular and non-modular operations, while using fewer neurons than previously reported SNP and SNQ constructions and natively supporting signed operands through the dual-spike representation.
5.2.2. Non-Modular Arithmetic Circuits
6. Discussion and Limitations
The Hybrid Membrane–Neural (HMN) arithmetic kernels are conceived as compact, constant-time building blocks within a formal membrane computing framework. While the results demonstrate advantages in neuron counts, execution time, and native support for signed arithmetic, the scope and limitations of the proposed approach must be carefully considered.
First, the HMN model is defined at an abstract level and is primarily intended as a theoretical model of computation. The arithmetic kernels are validated using formal semantic arguments and step-based analysis, rather than through full software or hardware implementations. As a consequence of this level of abstraction, practical issues related to low-level implementation are beyond the scope of the present work.
Second, following standard practice in SNP and SNQ arithmetic systems, the proposed designs assume that all spikes encoding a given operand arrive synchronously at the corresponding membrane. Although the HMN framework allows the optional use of a synchronization membrane to manage asynchronous arrivals, the associated preprocessing cost is not incorporated into the core arithmetic kernels and is reported separately. This assumption must be taken into account when comparing systems under conditions in which synchronization cannot be ensured.
Third, although the individual arithmetic kernels are structurally minimal and terminate in constant time, their composition into more complex systems may necessitate additional membranes and synchronization mechanisms. Consequently, the scalability of complex HMN-based architectures is determined primarily by the design of the surrounding system rather than by the individual kernels themselves.
Fourth, some arithmetic membranes, such as the signed division kernel , assume a finite and well-defined input domain induced by the working alphabet. In particular, the divisor magnitude is encoded in the spike type index , with , so the corresponding rule set is defined by finite schemata instantiated over this range, resulting in concrete evolution rules. This restriction reflects a design choice inherent to finite-alphabet HMN systems and does not affect the correctness or constant-time behavior of the kernel within its specified domain.
Finally, the scope of this work is limited to deterministic arithmetic computation under exhaustive semantics; extensions toward stochastic behavior, fault tolerance, and biologically realistic neuron models are left for future research.
7. Conclusions and Future Work
We presented a family of arithmetic kernels within the Hybrid Membrane–Neural (HMN) P system model that natively supports signed addition, subtraction, multiplication, and division, both with and without modular reduction. Exploiting the intrinsic dynamics of spike aggregation and spike–anti-spike annihilation, together with exhaustive semantics, these kernels operate in constant time under exhaustive execution and assuming synchronized input while minimizing neuron usage.
A comparison with representative SNP and SNQ arithmetic constructions demonstrates that the HMN kernels consistently require fewer neurons while achieving operand-independent execution time. In particular, non-modular addition and subtraction are performed intrinsically with zero internal computation steps, whereas multiplication and division are completed in a single simulation step using one neuron.
The proposed kernels follow a modular design that facilitates compositional arithmetic constructions while preserving low structural complexity and constant-time behavior. When operand spikes arrive at different computation steps, an auxiliary synchronization membrane may be employed to enforce the required input synchronization. This preprocessing mechanism operates independently of the arithmetic kernels and is therefore not included in the intrinsic neuron-count and time-complexity measures used for comparison.
As a result, the constant-time guarantees reported in this work apply to the arithmetic kernels themselves under exhaustive semantics and synchronized input, while the optional synchronization overhead is reported separately and does not affect the internal behavior of the kernels.
Future Work
The present work focuses on the design of constant-time arithmetic kernels within the HMN P system framework, which provide a reusable foundation for the construction of more complex computational modules within the HMN model. A natural direction for future research is the composition of these kernels into higher-level cryptographic algorithms, including elliptic-curve point addition and point doubling, as well as Montgomery-type curve arithmetic, where constant-time execution and efficient modular computation are critical.
Beyond cryptographic applications, an additional research direction concerns the investigation of hardware-oriented and neuromorphic realizations of HMN arithmetic kernels. While the exhaustive execution semantics adopted in this work are primarily intended for formal analysis, future studies may explore alternative execution strategies or hardware abstractions that preserve the functional behavior of the kernels while enabling practical implementations.
An implementation and simulation framework for HMN P systems is currently under development and will be released in a public repository to support reproducibility and experimentation.