Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals
Abstract
:1. Introduction
2. Stochastic Computing and Sigma-Delta Modulation Notation and Principle Operation
2.1. Stochastic Number Generation & Properties
2.2. Mathematical Properties of Logic Gates in Stochastic Computing
- NOT GateIn unipolar format, the output of the NOT gate, , complements the probability of the input,
- AND Gate:The AND gate in unipolar format, , performs multiplication.
- XNOR Gate:The XNOR gate in bipolar format, , performs multiplication.
- MultiplexerAssuming an an IID control sequence , the multiplexer (MUX), , is the standard way to perform scaled addition between two SN, regardless of the format used, and is given asFurthermore, if , the MUX operates as a scaling adder, i.e.,Stochastic subtraction, on the other hand, can only be realized in the bipolar format, using a NOT gate in one of the two inputs as
2.3. Correlation in Stochastic Computing
2.4. The First-Order Sigma-Delta Modulator
3. Prior Work in Stochastic Computing FIR Filters
4. Proposed SDM-SC Processing Scheme
4.1. SDM Encoding
4.2. Stochastic FIR Filter
4.3. Stochastic Coefficient Generation
5. Experimental Results
5.1. Performance of the Proposed SDM-SC Architecture in the Spectral Domain
5.2. Signal-to-Noise Ratio Comparisons
5.3. FPGA Synthesis Results and Comparison
5.4. Hardware Resources Comparison in a 45 nm Technology
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
FIR | Finite impulse response |
FPGA | Field-programmable gate-array |
LFSR | Linear-feedback shift register |
LUT | Look-up table |
MUX | Multiplexer |
OSR | Oversampling ratio |
PSD | Power Spectral Density |
SC | Stochastic computing |
SDM | Sigma-delta modulator |
SDM-SC | Sigma-delta modulator-stochastic computing |
SN | Stochastic number |
SNG | Stochastic number generator |
SNR | Signal-to-noise ratio |
XNOR | Exclusive-NOR |
XOR | Exclusive-OR |
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Parameter Name | Parameter Value |
---|---|
Input signal | |
5-tap FIR filter weights | |
7-tap FIR filter weights |
5-Tap FIR Filter | 7-Tap FIR Filter | |||||
---|---|---|---|---|---|---|
SDM-SC | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | SDM-SC | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | |
SNR (dB) | 47.01 | 31.41 | 97.21 | 42.94 | 29.93 | 91.31 |
5-Tap FIR Filter | |||
---|---|---|---|
SDM-SC Filter | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | |
Max Operating Frequency (MHz) | 667 | ||
Slice LUTs [Used/Util.] | 29/0.01% | 35/0.01% | 698/0.34% |
Slice Registers [Used/Util.] | 35/0.01% | 178/0.05% | 60/0.02% |
7-tap FIR filter | |||
SDM-SC Filter | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | |
Max Operating Frequency (MHz) | 667 | ||
Slice LUTs [Used/Util.] | 30/0.01% | 42/0.01% | 907/0.45% |
Slice Registers [Used/Util.] | 37/0.01% | 238/0.06% | 90/0.02% |
5-Tap FIR Filter | |||
---|---|---|---|
SDM-SC Filter | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | |
Area | 617.12 | 3425.88 | 9853.89 |
Power (mW) | 0.75 | 2.97 | 5.19 |
Delay (ns) | |||
Energy (pJ) | 1.13 | 4.46 | 7.78 |
7-tap FIR filter | |||
SDM-SC Filter | Inner-Product Adder-Tree [29,30,41] | Conv. Binary | |
Area | 700.66 | 4935.67 | 13,428.55 |
Power (mW) | 0.83 | 4.39 | 7.12 |
Delay (ns) | |||
Energy (pJ) | 1.24 | 6.51 | 10.58 |
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Temenos, N.; Vlachos, A.; Sotiriadis, P.P. Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals. Technologies 2022, 10, 14. https://doi.org/10.3390/technologies10010014
Temenos N, Vlachos A, Sotiriadis PP. Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals. Technologies. 2022; 10(1):14. https://doi.org/10.3390/technologies10010014
Chicago/Turabian StyleTemenos, Nikos, Anastasis Vlachos, and Paul P. Sotiriadis. 2022. "Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals" Technologies 10, no. 1: 14. https://doi.org/10.3390/technologies10010014