Open-Source Real-Time SDR Platform for Rapid Prototyping of LANS AFS Receiver
Abstract
1. Introduction
2. LANS AFS Overview
3. Baseband Signal Generator
3.1. Spreading Codes and Data
3.2. Satellite Dynamics and Pseudorange
- is an integer counter indicating the sequential week number from the start epoch of the LunaNet Reference Time (LRT).
- is the number of seconds in one week (i.e., 604,800 s).
- (interval time of week) is the number of block intervals that have occurred since the start of the current week.
- is the block interval duration, equal to 1200 s.
- (time of interval) is the number of frames from the beginning of the current block interval.
- is the frame duration, corresponding to 6000 data symbols, or 12 s.
3.3. Parallelization with OpenMP
4. LANS AFS Receiver
4.1. Adaptation for LANS AFS Reception
- Buffering: Symbols obtained from the PLL are stored in a FIFO buffer sized to accommodate one full navigation frame plus the SP (a total of symbols).
- Synchronization Check: If the initial 68 symbols in the FIFO buffer match the predefined SP, the implementation checks whether the SP also appears at the expected position one frame length later. If both instances match, frame synchronization is declared successful.
- Extraction: Upon successful synchronization, Subframe 1 (SB1), encoded with a BCH(52,9) code, is decoded in an attempt to extract the . If decoding fails or the cannot be determined, the process reverts to Step 1.
- CED Decoding: If the is successfully identified, Subframe 2 (SB2), which contains the Clock and Ephemeris Data (CED), is decoded using an LDPC decoder. If LDPC decoding fails, the process restarts from the beginning at Step 1. Subframes 3 and 4, currently undefined in the LSIS-AFS specification, are not processed in this implementation.
- CRC Verification: A cyclic redundancy check (CRC) is performed on the decoded SB2. If the CRC check fails, the system returns to the initial step. Otherwise, the CED is accepted and made available for positioning computation.
4.2. SIMD Optimization
4.3. Frontend Devices
5. Validation Tests
5.1. Offline Test Results
5.2. Real-Time Test Results
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
ADC | Analog-to-Digital Converter |
AFS | Augmented Forward Signal |
AGC | Automatic Gain Controlle |
API | Application Programming Interface |
BPSK | Binary Phase Shift Keying |
CBOC | Composite Binary Offset Carrier |
CED | Clock and Ephemeris Data |
CLT | Central Limit Theorem |
CNAV | Civil Navigation Message |
CPU | Central Processing Unit |
CRC | Cyclic Redundancy Check |
DLL | Delay-Locked Loop |
ELFO | Elliptical Lunar Frozen Orbits |
ESA | European Space Agency |
FEC | forward error correction |
GNSS | Global Navigation Satellite System |
GPS | Glonal Navigation System |
ITOW | Interval Time of Week |
JAXA | Japan Aerospace Exploration Agency |
LANS | Lunar Augmented Navigation Service |
LDPC | Low Density Parity Check |
LFSR | Linear Feedback Shift Register |
LLR | Log-Likelihood Ratio |
LNIS | LunaNet Interoperability Specification |
LNSP | LunaNet Service Provider |
LNSS | Lunar Navigation Satellite System |
LRT | LunaNet Reference Time |
NASA | National Aeronautics and Space Administration |
PLL | Phase-Locked Loop |
PNT | Position, Navigation, and Timing |
PRN | Rseudorandom Noise |
SDR | Software Defined Radio |
SIMD | Single Instruction, Multiple Data |
SNR | Signal-to-Noise Ratio |
SP | Synchronization Pattern |
SWaP | Size, Weight, and Power |
TOI | Time of Interval |
ToT | Time of Transmission |
WN | Week Number |
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Feature | LANS AFS | GPS L1 C/A | GPS L1C | Galileo E1 |
---|---|---|---|---|
Data/Pilot Channels | Yes | No | Yes | Yes |
Modulation | BPSK | BPSK | BOC/TMBOC | CBOC |
FEC Encoding | LDPC | None | LDPC | Convolutional |
Code Length (chips) | 2046/10,230 | 1023 | 10,230 | 4092 |
Spreading Rate (Mcps) | 1.023/5.115 | 1.023 | 1.023 | 1.023 |
Code Period (ms) | 2 | 1 | 10 | 4 |
Data Symbol Rate (sps) | 500 | 50 | 100 | 250 |
Processing Time (s) | |||
---|---|---|---|
Data Length (s) | Serial | OpenMP | Improvement |
30 | 14.4 | 2.5 | ×5.8 |
60 | 29.0 | 5.0 | ×5.8 |
90 | 43.8 | 7.6 | ×5.8 |
Function | Description | AVX2 | NEON |
---|---|---|---|
sdr_cpx_mul | Multiplication of two complex arrays | Yes | No |
mix_carr | Carrier mixing for carrier wipe-off | Yes | No |
sum_s16 | Summation of multiple int16 fields | Yes | Yes |
dot_IQ_code | Inner product of I/Q samples and local code | Yes | Yes |
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Sobukawa, R.; Ebinuma, T. Open-Source Real-Time SDR Platform for Rapid Prototyping of LANS AFS Receiver. Aerospace 2025, 12, 620. https://doi.org/10.3390/aerospace12070620
Sobukawa R, Ebinuma T. Open-Source Real-Time SDR Platform for Rapid Prototyping of LANS AFS Receiver. Aerospace. 2025; 12(7):620. https://doi.org/10.3390/aerospace12070620
Chicago/Turabian StyleSobukawa, Rion, and Takuji Ebinuma. 2025. "Open-Source Real-Time SDR Platform for Rapid Prototyping of LANS AFS Receiver" Aerospace 12, no. 7: 620. https://doi.org/10.3390/aerospace12070620
APA StyleSobukawa, R., & Ebinuma, T. (2025). Open-Source Real-Time SDR Platform for Rapid Prototyping of LANS AFS Receiver. Aerospace, 12(7), 620. https://doi.org/10.3390/aerospace12070620