A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS
Abstract
:1. Introduction
2. PLL Architecture
3. Design Details
3.1. Voltage-Controlled Oscillator (VCO)
3.2. Injection-Locked Frequency Divider (ILFD)
3.3. CML Frequency Divider Chain
3.4. Phase-Frequency Detector (PFD)
3.5. Charge Pump (CP) and Loop Filter (LF)
3.6. Layout Designing
4. Measured Results
5. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Parameter | [8] | [9] | [10] | [11] | [12] | [16] | [17] | Our Work |
---|---|---|---|---|---|---|---|---|
Technology (nm) | 65 | 90 | 40 LP | 65 | 65 | 65 | 28 | 65 LP |
Frequency (GHz) | 58.5–58.9 | 60.2–62.4 | 63–70 | 70–78 | 53–61 | 65–69 | 54.1–57 | 65.15–67.4 |
Supply Voltage (V) | 1.2 | 1.5 | 1.1 | 1 | 0.8 | 1.2 | - | 1.4 |
PN@1MHz (dBc/Hz) | −83.5 | −69.92 | −85 | −83 | −88 | −98.5 ** | −93 | −84.43 |
Ref. Frequency (MHz) | 150 | 78 | - | - | 56 | 67 | 2280 | 515 |
Power Consumption (mW) | 43 | 106.6 | 79.2 | 65 | 48 | 72.44 | 10 | 88 |
Active Chip Area (excluding pads) () | 1 * | 1.12 * | 0.192 | 0.31 | 0.32 | 3.24 * | 0.19 | 0.37 |
Output Power (dBm) | −14 | −9.5 | - | - | - | - | - | −11.6 |
FOM (dBc/Hz) | 119.16 | 116.5 | 142.9 | 142.9 | 148.6 | 152.58 | 152.24 | 132.58 |
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Abbas, W.; Mehmood, Z.; Seo, M. A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS. Electronics 2020, 9, 1502. https://doi.org/10.3390/electronics9091502
Abbas W, Mehmood Z, Seo M. A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS. Electronics. 2020; 9(9):1502. https://doi.org/10.3390/electronics9091502
Chicago/Turabian StyleAbbas, Waseem, Zubair Mehmood, and Munkyo Seo. 2020. "A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS" Electronics 9, no. 9: 1502. https://doi.org/10.3390/electronics9091502