Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

Abstract

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.

1. Introduction

Thin film transistors (TFTs) are key devices to develop large area electronics applications such as active matrix liquid crystal displays (AMLCD) [1,2,3], wearable sensors [4,5] and passive tags RFID (radio frequency identification) [6,7,8]. Nowadays, TFT technology is based on amorphous silicon (a-Si), polysilicon (poly-Si) and IGZO (indium-gallium-zinc oxide) semiconductors. The a-Si TFTs offer small electron mobilities (<1 cm²/Vs), and thus low switching speed [9]. The other hand, poly-Si TFTs are devices with high performance, but they are fabricated at higher temperatures (500–600 °C) [10,11,12], while IGZO TFTs have moderate mobilities (>10 cm²/Vs) and low temperature of fabrication [13]. However, this semiconductor is only used for the fabrication of n-type devices, for p-type is used a different semiconductor, such as SnO [14]. To overcome these limitations, hydrogenated amorphous silicon-germanium (a-SiGe:H) films can be used to fabricate TFTs at low temperature of deposition (<300 °C) by PECVD technique. This allows carrier mobilities higher than 1 cm²/Vs caused by the incorporation of germanium and hydrogen atoms. In addition, a-SiGe:H TFTs can have an ambipolar behavior, allowing their operation into either as n- or p-type [15]. In order to design a-SiGe:H TFTs for specific applications, it is necessary to predict the behavior of their drain currents. Shur et al. [16] reported a physical drain current model for n- and p-channels hydrogenated amorphous silicon and polysilicon staggered bottom-gate top-contact TFTs. This model was implemented into an AIM-SPICE circuit simulator. However, it is adapted from MOSFET model and it does not include semiconductor density of states. Chen et al. [17] reported an analytical drain current model for both triode and saturation region of operation for a-Si:H TFTs considering semiconductor density of states and an effective temperature approach. However, this model registered a high error between measurements and modeled results. Liu et al. [18] presented an analytical drain current model for a-Si:H TFTs based on surface potential, which was compared with numerical simulations considering free and localized carrier densities into the semiconductor. Colalongo et al. [19] designed an analytical drain current model for a-Si:H TFTs based on deep and tail states in both semiconductors, which describe the behavior at sub-threshold and above-threshold mode of operation.

In this paper, we develop an analytical drain current model for a-SiGe:H TFTs that considers free and localized charges into semiconductor and its characteristic temperatures, which can represent the behavior at sub-threshold and above-threshold regions of operation without using fitting parameters. In addition, 2D numerical simulations using finite element method of the output and transfer characteristics of bottom-gate top-contact coplanar a-SiGe:H TFTs are reported. The results of our analytical drain current model agree well with respect to those of the numerical simulations. In Section 2, electrostatic analysis and derivation of expressions for electric field and drain current are explained. In Section 3, comparison of our model and simulation results are presented. Finally, the conclusions are discussed in Section 4.

2. Analytical Drain Current Model for a-SiGe:H TFTs

2.1. Density of Estates of Amorphous Semiconductors

The density of states, g(E), of an amorphous semiconductor thin film consists of four energy bands over the bandgap: two tail bands and two deep bands. Tail bands consist of a donor-like valence band, g_TA(E), and an acceptor-like conduction band, $g_{TD}(E)$. On the other hand, deep bands are composed of a donor-like valence band, $g_{GA}(E)$, and an acceptor-like conduction band, $g_{GD}(E)$, which are represented as follow, [20]:

$$g\left(E\right)=g_{TA}\left(E\right)+g_{TD}\left(E\right)+g_{GA}\left(E\right)+g_{GD}\left(E\right)$$

(1)

$$g_{TA}(E)=NTA\cdot \exp \left[(E-E_C)/WTA\right]$$

(2)

$$g_{TD}(E)=NTD\cdot \exp \left[(E_V-E)/WTD\right]$$

(3)

$$g_{GA}(E)=NDA\cdot \exp \left[-{\left((E-E_{GA})/WGA\right)}^2\right]$$

(4)

$$g_{GD}(E)=NDD\cdot \exp \left[-{\left((E-E_{GD})/WGD\right)}^2\right]$$

(5)

where E is the trap energy, E_C and E_v are the conduction and valence band energy, respectively; WTA (kT_tail) and WTD (kT_tail) are acceptor and donor characteristic decay energy for the tail band, respectively; WGA (kT_deep) and WGD (kT_deep) are acceptor and donor characteristic decay energy for the deep band, respectively; NTA, NTD, NDA and NDD are the conduction and valence band edge intercept densities for the tail and deep band, respectively.

2.2. Analytical Drain Current Model

Figure 1a shows a schematic cross section of a n-type coplanar bottom-gate top-contact a-SiGe:H TFT with SiO₂ as gate insulator and a-Ge:H n+ layers for drain and source extensions. In this Figure, T_ox and T_sc are the gate oxide and semiconductor thickness, respectively. Figure 1b depicts the diagram of energy band for MIS (metal-insulator-semiconductor) region for this device working under accumulation regimen, when a positive gate potential (V_G) is applied. For this Figure, E_C and E_V are energy levels of conduction and valence bands, respectively; E_Fm, and E_Fn are the Fermi energy levels for metal, intrinsic and n-type semiconductor, respectively; φ_S and φ_CH(x) are surface and channel potential; and φ_F0(x) is the potential between E_c and E_Fn.

2.2.1. Derivation of Electric Field

Taking into account the free and localized electron concentration for an n-type amorphous semiconductor, the Poisson’s equation in one dimension, along the x direction, can be expressed as:

$$\frac{{\partial }^2\varphi \left(\mathrm{x}\right)}{\partial x^2}=-\frac{\rho \left(\mathrm{x}\right)}{{\epsilon }_{sc}}=\frac{q}{{\epsilon }_{sc}}\left(n_{free}\left(\mathrm{x}\right)+n_{deep}\left(\mathrm{x}\right)++n_{deep}\left(\mathrm{x}\right)\right)$$

(6)

where q is the electron charge, ϕ(x) is the potential across the active layer, ρ(x) is the total charge density, ɛ_sc is the permittivity constant of the semiconductor layer, n_free(x), n_deep(x) and n_tail(x) are the free, deep and tail electron concentrations, respectively. These concentrations for a-SiGe:H layer can be expressed as:

$$n_{free}(\mathrm{x})=N_{free}\exp \left[\frac{q\left(\varphi (\mathrm{x})-{\mathrm{V}}_{\mathrm{CH}}-{\varphi }_{\mathrm{F}0}\right)}{k{T}_{free}}\right]$$

(7)

$$N_{free}=N_C{g}^{\left(T/T_{free}\right)}kT\frac{\pi }{sin\left(\pi T/T_{free}\right)}$$

(8)

$$n_{deep}(\mathrm{x})=N_{deep}\exp \left[\frac{q\left(\varphi (\mathrm{x})-{\mathrm{V}}_{\mathrm{CH}}-{\varphi }_{\mathrm{F}0}\right)}{WGA}\right]$$

(9)

$$N_{deep}=g_{GA}{g}^{\left(T/T_{deep}\right)}kT\frac{\pi }{sin\left(\pi T/T_{deep}\right)}$$

(10)

$$n_{tail}(\mathrm{x})=N_{tail}\exp \left[\frac{q\left(\varphi (\mathrm{x})-{\mathrm{V}}_{\mathrm{CH}}-{\varphi }_{\mathrm{F}0}\right)}{WTA}\right]$$

(11)

$$N_{tail}=g_{TA}{g}^{\left(T/T_{deep}\right)}kT\frac{\pi }{sin\left(\pi T/T_{deep}\right)}$$

(12)

where N_C is the free electron concentration, V_CH is the potential along the channel, q is the electron charge, k is Boltzmann constant, T is a reference temperature and g is the degeneration factor which depends of the temperature ratio (T/T_eff) as exponential expression.

In order to simplify the analysis, an effective carrier concentration (N_eff) instead of free, deep or tail carrier concentrations (N_free, N_deep or N_tail), which are computed with Equations (8), (10) or (12) equations, respectively, is proposed. In the same way, an effective characteristic temperature (T_eff) instead of free, deep or tail temperature (T_free, T_deep or T_tail), respectively, is used.

To derivate the electric filed as function of electrostatic potential, it is necessary to solve the following Poisson´s equation:

$$\frac{{\partial }^2\varphi (\mathrm{x})}{\partial x^2}=-\frac{\rho (\mathrm{x})}{{\epsilon }_{sc}}=\frac{q}{{\epsilon }_{sc}}{n}_{eff}(\mathrm{x})$$

(13)

By employing the next expression to change the integration variable, from x to ϕ(x):

$$\frac{d}{dx}\left[{\left(\frac{d\varphi (\mathrm{x})}{dx}\right)}^2\right]=2\left(\frac{d\varphi (\mathrm{x})}{dx}\right)\left(\frac{d^2\varphi (\mathrm{x})}{d{x}^2}\right)$$

(14)

By integrating both sides in Equation (14) and applying the square root, we have:

$$\frac{d\varphi (\mathrm{x})}{dx}=\sqrt{2{\displaystyle \int \left(\frac{d\varphi (\mathrm{x})}{dx}\right)\left(\frac{d^2\varphi (\mathrm{x})}{d{x}^2}\right)}dx}=\sqrt{2{\displaystyle \int \left(\frac{d^2\varphi (\mathrm{x})}{d{x}^2}\right)d\varphi (\mathrm{x})}}$$

(15)

By substituting Equation (13) into Equation (15) and applying the boundary conditions from x = 0 (ϕ_S (x)) to x = T_SC (ϕ_B(x)), the electric field as a function of ϕ(x) is expressed as:

$$E(\varphi (\mathrm{x}))=-\frac{d\varphi (\mathrm{x})}{dx}=\sqrt{2{\displaystyle {\int }_{\varphi (\mathrm{x}=T_{sc})={\varphi }_B}^{\varphi (\mathrm{x}=0)={\varphi }_S}\frac{q}{{\epsilon }_{sc}}{n}_{eff}(\mathrm{x})d\varphi (\mathrm{x})}}=\sqrt{\frac{2N_{eff}k{T}_{eff}}{{\epsilon }_{sc}}\left(n_{eff}({\varphi }_S(\mathrm{x}))-n_{eff}({\varphi }_B(\mathrm{x}))\right)}$$

(16)

where n_eff is the effective electron density, T_eff is the effective characteristic temperature, ${\epsilon }_{sc}$ is the semiconductor permittivity, ϕ_S(x) is the electrostatic potential in the gate insulator/semiconductor interface_, ϕ_B(x) is the electrostatic potential in the semiconductor/passivation layer interface, which is neglected because is close to zero. Thus, the transversal electric field through an amorphous semiconductor, at x direction, is given by:

$$E(\varphi (\mathrm{x}))=\sqrt{\frac{2N_{eff}k{T}_{eff}}{{\epsilon }_{sc}}}\exp \left[\frac{q\left({\varphi }_S-{\mathrm{V}}_{\mathrm{CH}}-{\varphi }_{\mathrm{F}0}\right)}{2k{T}_{eff}}\right]$$

(17)

2.2.2. Derivation of Drain to Source Current in Subthreshold Region, I_{DS_sub}

In the subthreshold region operation of a-SiGe:H TFT, that is gate to source voltage, V_GS, is less than threshold voltage, V_TH, but larger than the flat band voltage, V_FB, (V_FB < V_GS < V_TH), most of the carriers are free electrons, because of deep and tail localized carriers are trapped into semiconductor defects. Therefore, it is necessary to apply a larger V_GS in order to generate a higher transversal electric field to the active layer to set free those charges. In addition, for this semiconductor (see

Table 1. Electrical parameters for a-SiGe:H and SiO₂ layers [20].

Name	Parameter	a-SiGe:H	SiO2
Permittivity	ɛ	11.8	3.9
Electronic affinity	Χ	4.01 eV	0.9 eV
Bandgap	Eg	1.4 eV	9 eV
Intrinsic concentration	ni	1 × 1012 cm–3	- *
Conduction band density	Nc	1 × 1020 cm–3	- *
Valence band density	Nv	1 × 1020 cm–3	- *
Electron band mobility	μ0	0.56 cm2/Vs	- *
Bulk Fermi Level	ΦF0	0.56 V	- *
Flat band voltage	VFB	−0.01 V	- *

* Data not available in the literature.

) the localized energy characteristics (kT_tail and kT_deep) are higher than the free energy characteristic (kT_free). Thus, $\rho (x)$ for an a-SiGe:H TFT at subthreshold operation can be obtained by:

$$\frac{\rho (\mathrm{x})}{-q}=n_{eff}(\mathrm{x})\approx n_{free}(\mathrm{x})$$

(18)

In order to derive the drain to source current in subthreshold regimen, I_{DS_sub}, is employed the gradual channel approximation expression, which is given by:

$$I_{\mathsf{D}\mathsf{S}\_\mathsf{s}\mathsf{u}\mathsf{b}}=W\frac{d{V}_{CH}(y)}{dy}{\displaystyle {\int }_{x=0}^{x=Tsc}{\sigma }_n}(\mathrm{x})\mathrm{d}\mathrm{x}=W\frac{d{V}_{CH}(\mathrm{y})}{dy}{\displaystyle {\int }_{\varphi (\mathrm{x}=t_{sc})}^{\varphi (\mathrm{x}=0)}q{\mu }_0\frac{n_{free}(\varphi (\mathrm{x}))}{E(\varphi (\mathrm{x}))}}d\varphi (\mathrm{x})$$

(19)

where W is the channel width of TFT, σ_n(x) is the n-type channel conductivity of a-SiGe:H, E(φ(x)) is the electric field dependent of potential at x direction, and μ₀ is the carrier mobility of semiconductor.

The final expression for drain to source current at region of subthreshold for an a-SiGe:H TFT is computing solving Equation (19), step-by-step at Appendix A, considering N_eff = N_free and T_eff = T_free, as follows:

$$I_{DS\_sub}(N_{free},T_{free})={\mu }_0\frac{W}{L}\frac{A_{free}}{B_{free}}{\left(\frac{C_{OX}}{\sqrt{2{\epsilon }_{sc}{N}_{free}k{T}_{free}}}\right)}^{C_{free}}\left[\frac{1}{C_{free}+1}\left({\left(\delta V_{SD}\right)}^{C_{free}+1}-{\left(\delta V_{SS}\right)}^{C_{free}+1}\right)+\frac{1}{\mathrm{q}{\mathsf{B}}_{free}}\left({\left(\delta V_{SD}\right)}^{C_{free}}-{\left(\delta V_{SS}\right)}^{C_{free}}\right)\right]$$

(20)

with:

$$A_{free}=\frac{N_c}{\sqrt{\frac{2N_{free}k{T}_{free}}{{\epsilon }_{sc}}}}$$

(21)

$$B_{free}=\frac{1}{kT}-\frac{1}{2k{T}_{free}}$$

(22)

$$C_{free}=2k{T}_{free}{B}_{free}$$

(23)

$$\delta V_{SD}=V_{GS}-V_{FB}-V_D$$

(24)

$$\delta V_{SS}=V_{GS}-V_{FB}-V_S$$

(25)

2.2.3. Derivation of Drain Current at Above Threshold Region, I_{DS_abv}

Above threshold region of a-SiGe:H TFT operation, that is when V_GS > V_TH, free and localized charges are taken in to account due to the applied gate to source voltage generates a strong transversal electric field to the active layer which produces an accumulation of both carriers in the semiconductor/gate-insulator interface. However, in this semiconductor n_deep(x) << n_tail(x). Thus, we obtained the following equation:

$$\frac{\rho (\mathrm{x})}{-q}=n_{eff}(\mathrm{x})\approx n_{free}(\mathrm{x})+n_{tail}(\mathrm{x})$$

(26)

Poisson’s equation is applied as follows:

$$\frac{{\partial }^2\varphi (\mathrm{x})}{\partial x^2}=-\frac{\rho (\mathrm{x})}{{\epsilon }_{sc}}\cong \frac{q}{{\epsilon }_{sc}}\left(n_{free}(\mathrm{x})+n_{tail}(\mathrm{x})\right)$$

(27)

By using the gradual channel approximation Equation (19) and the procedure in Appendix A, taking into account free and tail localized charges along the semiconductor, we can derive the drain to source current for the above threshold region, I_{DS_abv}, as follows:

$$\begin{array}{l}{I}_{DS\_abv}=I_{DS}(N_{free},T_{free})+{\mathrm{I}}_{\mathsf{D}\mathsf{S}}(N_{tail},T_{tail})\\ =I_{DS}(N_{free},T_{free})+{\mu }_0\frac{W}{L}\frac{A_{tail}}{B_{tail}}{\left(\frac{C_{O\mathrm{X}}}{\sqrt{2{\epsilon }_{sc}{N}_{tail}k{T}_{tail}}}\right)}^{C_{tail}}\left[\frac{1}{C_{tail}+1}\left({\left(\delta V_{SD}\right)}^{C_{tail}+1}-{\left(\delta V_{SS}\right)}^{C_{tail}+1}\right)+\frac{1}{q{B}_{tail}}\left({\left(\delta V_{SD}\right)}^{C_{tail}}-{\left(\delta V_{SS}\right)}^{C_{tail}}\right)\right]\end{array}$$

(28)

with

$$A_{tail}=\frac{N_c}{\sqrt{\frac{2N_{tail}k{T}_{tail}}{{\epsilon }_{sc}}}}$$

(29)

$$B_{tail}=\frac{1}{kT}-\frac{1}{2k{T}_{tail}}$$

(30)

$$C_{tail}=2k{T}_{tail}{B}_{tail}$$

(31)

2.2.4. Total Analytical Drain Current Model

The final unified analytical drain current model for a-SiGe:H TFTs takies into account the sub-threshold and above-threshold regions, which it considers the density of states of such amorphous semiconductor and free electrons, is estimated by adding I_{DS_sub} and I_{DS_abv} with the following expression:

$$I_{DS}=\frac{1}{\left(\frac{1}{I_{DS}{}_{\_sub}}+\frac{1}{I_{DS\_abv}}\right)}$$

(32)

3. Results and Discussion

In order to compare the results of our analytical drain current model, we develop 2D numerical simulations for bottom-gate top-contact coplanar a-SiGe:H TFTs using Silvaco TCAD software through Atlas and Devedit tools (Santa Clara, CA, USA) [21]. These simulation tools use finite element method to perform the electrostatic analysis. Figure 2 shows a schematic view of the cross-section of the proposed device and its main geometrical parameters. The substrate is silicon oxide with a thickness T_SUB = 200 nm. The gate and drain/source electrodes are aluminum with thickness T_G and T_D/S of 100 nm, respectively. SiO₂ is used as gate insulator with a thickness T_OX = 80 nm. An overlap length between gate and drain/source electrodes of L_OV = 10 nm is used. Then, a thin film of a-SiGe:H as active layer or semiconductor with a thickness T_SC = 100 nm and a length channel L = 75 µm is used. The width of the active layer W = 30 µm is used for calculation. A layer of high doped germanium as drain/source extension region with thickness T_EXT = 40 nm and length L_D/S = 2 µm are employed to get a good ohmic contact with the semiconductor. Finally, SiN₄ as passivating dielectric layer with T_PASS = 200 nm is used in order to reduce broken bonds of the a-SiGe:H surface and carriers recombination.

The parameters for semiconductor and gate insulator layers considered in the numerical simulations and analytical drain current model are listed in Table 1. Furthermore, defects parameters that define the density of states of a-SiGe:H layer used for simulations and modeling are shown in

Table 2. Defects parameters of a-SiGe:H layer employed in analytical model and numerical simulations [20].

Name	Parameter	Value
Zero bias density of states acceptor for tail state	gTA	1 × 1020
Zero bias density of states acceptor for deep state	gGA	2 × 1016
Degeneration factor	G	2
Correlation energy	U=EGA – EGD	0.3 eV
Acceptor characteristic decay energy for deep state	WGA	0.3 eV
Donor characteristic decay energy for deep state	WGD	0.3 eV
Acceptor density distribution for deep state	NGA	2 × 1016 cm–3
Donor density distribution for deep state	NGD	2 × 1016 cm–3
Acceptor density distribution for tail state	NTA	1 × 1020
Acceptor density distribution for deep state	NTD	1 × 1020
Reference characteristic temperature	T	182.8 K
Free characteristic temperature	Tfree	300 K
Deep state characteristic temperature	Tdeep	649.8 K
Tail state characteristic temperature	Ttail	324.92 K
Acceptor characteristic decay energy tail state	WTA	0.028 eV
Donor characteristic decay energy for tail state	WTD	0.056 eV
Electron capture cross-section for the donor gaussian state	SIGGDE	1.3 × 10–14
Electron capture cross-section for the acceptor gaussian state	SIGGAE	2.7 × 10–14
Electron capture cross-section for the donor tail state	SIGTDE	5 × 10–15
Electron capture cross-section for the acceptor tail state	SIGTAE	5 × 10–15
Hole capture cross-section for the donor gaussian state	SIGGDH	2 × 10–15
Hole capture cross-section for the acceptor gaussian state	SIGGAH	1.3 × 10–14
Hole capture cross-section for the donor tail state	SIGTDH	5 × 10–15
Hole capture cross-section for the acceptor tail state	SIGTAH	5 × 10–15

. Some of those values were taken from [20].

Figure 3 shows the comparison of modeled (lines) and simulated (symbols) characteristics I_DS vs V_DS for V_GS = 1, 2, 3 and 4 Volts. It can be seen that the model is able to represent the behavior of the drain current at the sub-threshold and above-threshold regions for each curve corresponding to different V_GS values with a small error for the whole V_DS range.

Figure 4 shows the absolute and average error between I_DS characteristics modeled and simulated presented, which is computed with Equation (33). It can be seen; the maximum absolute error occurs for the I_DS curve when V_DS = 0.5 V and V_GS = 4 V which is 9.8%. In addition, the average absolute error for all values of V_GS is 5%, approximately.

$$Error(\%)=100\left(\frac{abs\left(I_{DS(simulated)}-I_{DS(\mathrm{modeled})}\right)}{I_{DS(\mathrm{modeled})}}\right)$$

(33)

Figure 5 shows the comparison of the modeled (lines) and simulated (symbols) output characteristics I_DS vs V_GS for V_DS = 0.1, 1, 2, 3 and 4 Volts. It can be seen that there exist a good fit between modeled and simulated I_DS curves for both linear (V_DS = 0.1 Volts, V_GS > V_TH) and saturation (V_DS > V_GS – V_TH, V_GS > V_TH) regions of operation for a-SiGe:H TFT.

4. Conclusions

In this paper, was developed an analytical drain current model for a-SiGe:H TFTs that shows very good agreement with 2D numerical simulations which were used to validate it. The model considers free and localized charges into a-SiGe:H layer, characteristic temperature dependence and is able to work for sub- and above- threshold region of operation with a small absolute average error. In this sense, the proposed model has implication for development and prediction of electrical performance of TFTs at low frequencies based on amorphous semiconductors, such as a-SiGe:H, which is requested for analysis and design of circuits for large area and flexible electronic systems. Future work will include the fabrication and characterization of a-SiGe:H thin films transistors devices.