FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry
Abstract
:1. Introduction
2. Background and State-of-the-Art
2.1. Doppler Processing Data Path Overview
2.2. Power Spectral Estimation
2.3. Spectral Peak
2.4. Centroid Frequency Estimation
3. The Proposed Method
3.1. Method Basics
- (a)
- The peak estimator (6) is first applied to obtain ;
- (b)
- The frequency interval [], centered on and of extension 2B + 1 is considered. More details on B are given below.
- (c)
- The centroid frequency , output of the estimator, is estimated in the region located in previous step.
3.2. The B Parameter
3.3. Comparison of Proposed Method to Standard Methods
4. Circuit Architecture
- When data is processed according to Peak estimator, the Nios II activates the Max Detector only to get . When data is processed through full centroid estimator (7), the Nios II runs Num and Den modules on the whole PSD frequency range, followed by the A/B module.
5. Experiments and Results
5.1. Modules Latency
5.2. FPGA Resources and Maximum Clock Frequency
5.3. Data Throughput
5.4. Mathematical Noise
6. Discussion and Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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SNR | Peak Estimator | Full Centroid Estimator | Proposed | |||
---|---|---|---|---|---|---|
−20 dB | −8.74% | 51.1% | −68.3% | 63.3% | −8.8% | 50.7% |
−15 dB | −0.38% | 7.3% | −29.67% | 31.9% | −0.11% | 4.4% |
−10 dB | −0.21% | 6.9% | −2.38% | 6.7% | −0.15% | 3.2% |
0 dB | −0.13% | 6.8% | −0.04% | 3.2% | −0.06% | 3.2% |
10 dB | −0.17% | 6.8% | −0.04% | 3.2% | −0.04% | 3.2% |
20 dB | −0.13% | 6.7% | −0.04% | 3.2% | −0.04% | 3.2% |
Operations | Weight | Peak Estimator L = 128 | Full Centroid Estimator L = 128 | Proposed Estimator L = 128 B = 12 | |||
---|---|---|---|---|---|---|---|
Comparisons | 1 | L−1 | 127 | - | - | L−1 | 127 |
Additions | 1 | - | - | 2(L−1) | 254 | 4B | 48 |
Multiplications | 2 | - | - | L−1 | 127 | 2B | 24 |
Divisions | 16 | - | - | 1 | 1 | 1 | 1 |
Total Effort | 127 | 524 | 239 |
PSD Calculation (L = 128) | ||||
Block | Parameter | Latency (Clock Cycles) | ||
FFT | TFFT | 294 | ||
I2+Q2 | TIQ | 135 | ||
FP | TFP | 135 | ||
Doppler Frequency Calculation | ||||
Block | Parameter | Peak Estimator L = 128 | Full Centroid Estimator L = 128 | Proposed est. L = 128; B = 12 |
Max Det. | TM | 130 | Not used | 130 |
Num | TND | Not used | 131 | 29 |
Den | TND | Not used | 131 | 29 |
A/B | TD | Not used | 16 | 16 |
Block | LEs | DSPs | Memory Bits | Max Clock Freq. |
---|---|---|---|---|
FFT | 10,308 | 24 | 40,900 | 105 MHz |
I2 + Q2 | 400 | 14 | 0 | 110 MHz |
DP Mem | 0 | 0 | 4096 | 210 MHz |
Max Det. | 70 | 0 | 0 | 150 MHz |
Num | 600 | 0 | 0 | 120 MHz |
Den | 600 | 0 | 0 | 120 MHz |
A/B | 230 | 0 | 0 | 110 MHz |
FP | 300 | 0 | 0 | 120 MHz |
Estimator | T (Clock Cycles) | Throughput Estimates/s |
---|---|---|
Proposed B = 12 | 429 | 232 k |
Full centroid | 531 | 189 k |
Peak estimator | 429 | 232 k |
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Ricci, S.; Meacci, V. FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry. Electronics 2020, 9, 456. https://doi.org/10.3390/electronics9030456
Ricci S, Meacci V. FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry. Electronics. 2020; 9(3):456. https://doi.org/10.3390/electronics9030456
Chicago/Turabian StyleRicci, Stefano, and Valentino Meacci. 2020. "FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry" Electronics 9, no. 3: 456. https://doi.org/10.3390/electronics9030456
APA StyleRicci, S., & Meacci, V. (2020). FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry. Electronics, 9(3), 456. https://doi.org/10.3390/electronics9030456