# FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Background and State-of-the-Art

#### 2.1. Doppler Processing Data Path Overview

#### 2.2. Power Spectral Estimation

^{2}(x)), $F$ is the frame index that accounts for the matrix sequence, $w$ is the overlap percentage of successive data packets ($0\le w<1$). For example, in case of $L$ = 128, $\Gamma \left\{x\right\}={\mathrm{FFT}}^{2}\left(\mathrm{x}\right),$ $w$ = 0.5, the first 128 demodulated data ${s}_{SWDn}\left(d,l\right)$ (0 < $l$ < 127) are processed through a 128-poinf FFT for every depth $d$. The squared output represents the first ($F$ = 0) output frame, i.e., the first spectral power density matrix. From now on, every new 64 PRIs, the last $L$ = 128 data (w = 0.5, i.e., 50% overlap) are processed for generating the next frames ($F$ = 1,2,3, etc.).

#### 2.3. Spectral Peak

#### 2.4. Centroid Frequency Estimation

## 3. The Proposed Method

#### 3.1. Method Basics

- (a)
- The peak estimator (6) is first applied to obtain ${n}_{p}$;
- (b)
- The frequency interval [${n}_{p}-B,{n}_{p}+B$], centered on ${n}_{p}$ and of extension 2B + 1 is considered. More details on B are given below.
- (c)
- The centroid frequency ${n}_{n}$, output of the estimator, is estimated in the region located in previous step.

#### 3.2. The B Parameter

_{%}):

#### 3.3. Comparison of Proposed Method to Standard Methods

## 4. Circuit Architecture

^{2}+ Q

^{2}block (see Figure 4), where real and imaginary parts are squared and summed at 48 bit for obtaining the PSD. The 128 PSD samples are reduced to 32 bit and saved in the DP memory. When the 128 data block is completely moved in the memory, the FFT output buffer is empty, and the FFT starts loading and processing a new data block. A floating point converter (FP) is employed to output the PSD in floating point format.

- When data is processed according to Peak estimator, the Nios II activates the Max Detector only to get ${n}_{p}$. When data is processed through full centroid estimator (7), the Nios II runs Num and Den modules on the whole PSD frequency range, followed by the A/B module.

## 5. Experiments and Results

#### 5.1. Modules Latency

^{2}+ Q

^{2}and FP modules take 135 clock cycles for processing the 128-sample set, corresponding to 1 sample per clock in addition to 7 cycles needed for the initialization and the filling of their pipeline. Similarly, Max Detector processes 1 sample per clock in addition to 2 extra cycles, and Num and Den processes 1 sample per clock in addition to 5 extra cycles. The divisor performs the ratio and floating-point conversion in 16 cycles. First rows of Table 3 lists the number of clock cycles required by the FFT, I

^{2}+ Q

^{2}, and FP modules for the calculation of the PSD. The following rows of the Table compares the number of clock cycles required by the Max Detector, Num, Den, A/B modules when implementing the proposed (9), peak (6) and centroid (7) estimators, respectively.

#### 5.2. FPGA Resources and Maximum Clock Frequency

#### 5.3. Data Throughput

^{2}+Q

^{2}modules while they calculated the PSD. The FFT restarted its calculation cycle when its output buffer was empty, a condition that occurred when the I

^{2}+ Q

^{2}block had moved the data to DP memory. PSDs were calculated and stored in the DP memory at the maximum throughput T

_{1}allowed by the modules:

_{1}= T

_{FFT}+ T

_{IQ}= 294 + 135 = 429 clock cycles.

_{M}= 130 cycles, as confirmed by the assertion of the DataValid signal (6th row). The Max detector was much faster than FFT and I

^{2}+ Q

^{2}modules (429 against 130 cycles, see Table 3) and stalled for most of the time. The throughput was limited by the calculation of the PSD: a new frequency estimate was produced every T

_{1}cycles.

^{2}+ Q

^{2}module did not start immediately at the FFT end not to overwrite data in the DP memory that are used by the FP module (see curved arrow). The throughput was here limited by the estimator operations. The clock cycles needed for producing every new frequency estimate were:

_{2}= T

_{M}+ T

_{ND}+ T

_{FP}+ T

_{IQ}= 130 + 131 + 135 + 135 = 531.

_{D}< T

_{FP}.

_{ND}was much lower compared to the previous case, and the FP module completed its operations near the end of the FFT. Thus, the DP memory was free and I

^{2}+ Q

^{2}started the calculations as soon as FFT ended, like in Figure 7a. In other words, the bottleneck was not the estimator, but the calculation of the PSD, as in the case of the Peak estimator, and Equation (12) applies again.

#### 5.4. Mathematical Noise

## 6. Discussion and Conclusions

_{%}< 1% in Table 1) is not in conflict with literature, since it was obtained in simulation, where most of the uncertainties present in real experiments are avoided [29]. On the other hand, simulation results confirm that the proposed estimator achieves a better accuracy with respect to peak estimator.

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 1.**Typical Pulsed Wave Doppler processing. Received echoes are analog-to-digital (AD) converted and organized along the columns of a matrix. The signal is demodulated and processed through high-pass filtering and autocorrelation or, alternatively the power spectral density (PSD) is calculated through spectral estimation. From PSD, the velocity is recovered through peak detection or centroid estimation.

**Figure 2.**The proposed method is applied in 3 steps. (

**a**) The spectrum peak (red circle) and the corresponding frequency ${n}_{p}$ are detected. (

**b**) A frequency interval of extension 2B + 1 is centered around ${n}_{p}$. (

**c**) The centroid frequency ${n}_{d}$ is calculated in the detected interval. Red dashed and dotted segments report ${n}_{p}$ = 0.22 and ${n}_{d}$ = 0.24, respectively.

**Figure 3.**Performance of the proposed estimator at different values of B. (

**a**) Mean Doppler spectrum (blue curve) and a single spectrum (red dashed curve) produced by a flow signal with a nominal normalized Doppler frequency F

_{r}. (

**b**) Accuracy achieved for B in the range 0–63. (

**c**) Precision achieved for B in the range 0–63. Red dashed segments report the position for B = 12.

**Figure 4.**Data processing path implemented in the FPGA. The power of FFT output is calculated (I

^{2}+ Q

^{2}) and the resulting PSD is saved in a DP memory. Its maximum is detected (Max detector), then the numerator (Num) and denominator (Den) of the centroid formula are calculated. The results are divided, converted in floating point (A/B), and downloaded to host together with the data in memory. A Nios II soft processor supervises the operations.

**Figure 7.**Throughput of the processing chain of Figure 4 for (

**a**) the Peak, (

**b**) Full centroid and (

**c**) proposed frequency estimators. The “busy” signals represent status of the corresponding processing block. The DataValid is asserted when the Doppler frequency estimate is ready.

**Figure 8.**A 0.5 m/s flow was investigated with a focused transducer transmitting short 6 MHz frequency bursts. An example of power spectral density (PSD) matrix (left), frequency profile (center) and its error (right), calculated in the FPGA are reported.

SNR | Peak Estimator | Full Centroid Estimator | Proposed | |||
---|---|---|---|---|---|---|

$\mathbf{E}\mathbf{r}{\mathbf{r}}_{\mathbf{\%}}$ | $\mathbf{C}{\mathbf{V}}_{\mathbf{\%}}$ | $\mathbf{E}\mathbf{r}{\mathbf{r}}_{\mathbf{\%}}$ | $\mathbf{C}{\mathbf{V}}_{\mathbf{\%}}$ | $\mathbf{E}\mathbf{r}{\mathbf{r}}_{\mathbf{\%}}$ | $\mathbf{C}{\mathbf{V}}_{\mathbf{\%}}$ | |

−20 dB | −8.74% | 51.1% | −68.3% | 63.3% | −8.8% | 50.7% |

−15 dB | −0.38% | 7.3% | −29.67% | 31.9% | −0.11% | 4.4% |

−10 dB | −0.21% | 6.9% | −2.38% | 6.7% | −0.15% | 3.2% |

0 dB | −0.13% | 6.8% | −0.04% | 3.2% | −0.06% | 3.2% |

10 dB | −0.17% | 6.8% | −0.04% | 3.2% | −0.04% | 3.2% |

20 dB | −0.13% | 6.7% | −0.04% | 3.2% | −0.04% | 3.2% |

Operations | Weight | Peak Estimator L = 128 | Full Centroid Estimator L = 128 | Proposed Estimator L = 128 B = 12 | |||
---|---|---|---|---|---|---|---|

Comparisons | 1 | L−1 | 127 | - | - | L−1 | 127 |

Additions | 1 | - | - | 2(L−1) | 254 | 4B | 48 |

Multiplications | 2 | - | - | L−1 | 127 | 2B | 24 |

Divisions | 16 | - | - | 1 | 1 | 1 | 1 |

Total Effort | 127 | 524 | 239 |

PSD Calculation (L = 128) | ||||

Block | Parameter | Latency (Clock Cycles) | ||

FFT | T_{FFT} | 294 | ||

I^{2}+Q^{2} | T_{IQ} | 135 | ||

FP | T_{FP} | 135 | ||

Doppler Frequency Calculation | ||||

Block | Parameter | Peak EstimatorL = 128 | Full Centroid EstimatorL = 128 | Proposed est.L = 128; B = 12 |

Max Det. | T_{M} | 130 | Not used | 130 |

Num | T_{ND} | Not used | 131 | 29 |

Den | T_{ND} | Not used | 131 | 29 |

A/B | T_{D} | Not used | 16 | 16 |

Block | LEs | DSPs | Memory Bits | Max Clock Freq. |
---|---|---|---|---|

FFT | 10,308 | 24 | 40,900 | 105 MHz |

I^{2} + Q^{2} | 400 | 14 | 0 | 110 MHz |

DP Mem | 0 | 0 | 4096 | 210 MHz |

Max Det. | 70 | 0 | 0 | 150 MHz |

Num | 600 | 0 | 0 | 120 MHz |

Den | 600 | 0 | 0 | 120 MHz |

A/B | 230 | 0 | 0 | 110 MHz |

FP | 300 | 0 | 0 | 120 MHz |

Estimator | T (Clock Cycles) | Throughput Estimates/s |
---|---|---|

Proposed B = 12 | 429 | 232 k |

Full centroid | 531 | 189 k |

Peak estimator | 429 | 232 k |

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**MDPI and ACS Style**

Ricci, S.; Meacci, V.
FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry. *Electronics* **2020**, *9*, 456.
https://doi.org/10.3390/electronics9030456

**AMA Style**

Ricci S, Meacci V.
FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry. *Electronics*. 2020; 9(3):456.
https://doi.org/10.3390/electronics9030456

**Chicago/Turabian Style**

Ricci, Stefano, and Valentino Meacci.
2020. "FPGA-Based Doppler Frequency Estimator for Real-Time Velocimetry" *Electronics* 9, no. 3: 456.
https://doi.org/10.3390/electronics9030456