A New High Voltage Gain DC to DC Converter with Low Voltage Stress for Energy Storage System Application

Abstract

Increasing energy demand globally has led to exploring ways of utilizing renewable resources for sustainable development. More recently, the integration of renewable distributed resources in small- and large-scale grid has been seriously researched. Development in renewable power sources and its integration with the grid require voltage level conversion to match the grid/micro-grid level. The voltage level conversion is brought about by employing Direct Current-Direct Current (DC-DC) converters with boosting features. The paper presents a wide gain range DC-DC boost converter with a low-stress on switching devices. The proposed converter’s voltage gain is high compared with the conventional quadratic boost converter and other recently developed high gain boost converters. The topology has been compared with recently proposed topologies, and comparative analysis based on various performance parameters has shown that the topology is suitable for renewable and sustainable energy storage and grid integration. The power loss analysis has been done by incorporating the switching and conduction losses. A hardware prototype of 150 W has been developed to validate the converter’s performance in steady-state as well as in dynamic conditions.

1. Introduction

DC-DC converter works on the principle of energy transfer between energy storage elements. By controlling this transfer of energy in one complete cycle, constant and high voltage can be obtained at the output. Conventional boost converter uses a single inductor and capacitor to obtain high voltage at the output. Other variants such as Cuk converters, Single Ended Primary Inductor Converters (SEPIC), and ZETA converters are also being developed to get high DC voltage output. These converters have a simple structure, but the voltage gain is limited [1]. Moreover, the stress across the switching devices is high, and efficiency is low. The converter cannot be operated at very high duty ratios as the conduction losses become elevated due to parasitic resistances and voltage gain decreases. Due to these problems, high gain DC-DC converters employing more than one inductor, and multiple capacitors can be employed to increase the converter’s gain [2].

High gain DC-DC converters have increasingly become popular due to their suitability in solar Photovoltaic (PV) systems and electric vehicles. The output voltage from solar PV modules, fuel cells, and batteries is generally low and needs to be boosted up to maintain the DC-link voltage at the inverter’s input [3]. The power flow in DC-DC converters can be unidirectional or bidirectional. Isolated topologies are suitable for high power applications and where efficiency required is high. Non-isolated topologies are usually used in low and [4] medium power applications where efficiency and electromagnetic interference are not significant concerns. Several isolated and non-isolated topologies use voltage multiplier cells (VMC) made up of switched inductors and capacitors to increase the converter’s output voltage. In some topologies, a coupled inductor is also used in VMC to increase the gain of the converter. Another advantage of using VMC is that a high output voltage can be obtained at lower duty ratios [5].

Multilevel DC-DC structures use multiple switched capacitors [6] at the output stage to boost the output voltage. Authors have proposed a novel buck-boost and boost converters with continuous input current in [7] and [8], but the voltage gain is limited at higher duty ratios. A single switch modified SEPIC converter with a high voltage gain, and low voltage stress is proposed in [9]. Switched inductor topologies have an advantage that peak transient current through the switch is avoided as the capacitor is not charged directly through the source. The input current is also continuous if the inductor is on the input side. However, the gain is less as compared to the switched capacitor topology. The use of many inductors increases the weight and size of the circuit. Whereas multiple switched capacitors can easily enhance the converter’s voltage gain substantially [10,11,12]. Switched capacitors, when employed with DC-DC converters, increase the gain of the converter substantially but the high charging current decreases the efficiency of the converter. In steady-state, the capacitors are in series and transfer their energy to load. Inductors are charged in the ON cycle, and during the OFF mode, the inductor discharges [13], and capacitors are charged in parallel. A new buck-boost converter with continuous input current with a quadratic gain is proposed [14].

Coupled inductor topologies have a high voltage gain, higher efficiency, and reduced voltage and current stresses across switches. The problem with coupled inductor topologies is that energy trapped in the leakage inductance needs to be recycled to avoid voltage transients across the switch and increase the circuit’s overall efficiency. For this, an additional clamped circuit needs to be designed for these topologies [15,16,17,18], which increases the circuit’s complexity. A new triple mode converter is proposed in [19], but many switches and inductors are required to obtain high voltage gain. The converter in [20] uses a Cockcroft-Walton based VMC to increase the gain of the converter. A new converter boost converter with VMC with switched capacitors is presented. The topology uses only a single inductor with switched capacitors, but the voltage gain [21] is limited. At lower duty ratios, the gain is little. Interleaved boost converters are characterized by a low ripple in current and low stress across the switches but require multiple VMCs (Voltage Doublers, Dickson Cells) at the output to boost the voltage.

Researchers have made efforts to optimize the number of VMCs to be used at the output so that a smaller number of components are required [22,23,24]. Another family of the DC-DC converter is quasi z source converters. The input current for these converters is continuous, and the stress across switching devices and capacitors are low. However, these converters have limited voltage gain [25], [26], and cannot be operated at higher duty ratios. The DC-DC converter performance with non-ideal components is discussed in [27]. It is shown that at low input voltages and high duty ratios, the converter performance deteriorates. The voltage gain and efficiency both decreases substantially. Some other new and efficient topologies of the DC-DC converter with high gain is discussed in [28] and [29]. Quadratic boost topologies have the advantage that very high gain ratios can be obtained at [30] low duty ratios. Low duty ratio operation reduces the stress across devices and improves the efficiency of the converter. Quadratic boost converters (QBC) generally use switched inductors and capacitors to increase the converter’s gain. Non-isolated QBC provides high gain with reduced stress on switches but at the cost of reducing the efficiency at higher duty ratios efficiency [31,32,33]. The advantages of non-isolated QBC over other topologies makes it a suitable choice for low and medium power applications [34,35]. The DC power supply can be given to a high gain converter and can be used even for a DC-AC high conversion application [36,37]. The switched capacitor application has also been discussed in [38,39,40,41].

This work’s motivation and objective is to develop a new quadratic boost converter with voltage multiplier cells. The proposed converter’s performance is an improvement over conventional QBC (CQBC) and other recently developed topologies. The voltage gain of the proposed converter is much higher than the conventional boost and CQBC. Along with low voltage stress across all components, the proposed converter’s input current is also continuous, which is another desired feature of the proposed converter. The converters utilize only two inductors with the same gate signal to generate a high output voltage. The converter has a simple structure, and its control is easy. The convertor performance is analysed in an open loop structure, and the converter’s working in CCM is shown in Section 2. Voltage stress and design of passive components are shown in Section 3. A comparison of the proposed converter with other topologies is discussed in Section 4. The simulation and experimental results along with efficiency calculation discussed in Section 5 and Section 6, respectively. The working of the proposed converter in dynamic conditions is discussed in Section 7. Discussion and conclusion are in Section 8 and Section 9, respectively.

2. Proposed Topology

The conventional quadratic boost converter has one switch. The switch is connected across the load and hence has to bear the voltage stress equal to the output voltage (V_o). It utilizes two inductors, but the voltage gain remains limited.

The Proposed converter topology is shown in Figure 1. It has six passive components, namely two inductors and four capacitors. The proposed converter comprises two voltage multiplier cells (VMC), as shown in Figure 1. These VMCs are used to improve the voltage gain further and reduce the voltage stress on the switching components.

The proposed converter has two switches, and the same switching signal controls both. That is, both the switches are turned ON and turned OFF simultaneously. During the first mode of operation, when the control signal is high, both the switches are turned ON, diode D₂ and D₄ are conducting as shown in Figure 2.

The KVL equations during the first mode of operation are as follows:

$$V_{L1}=V_{in}+V_{C1}=V_{C2}$$

(1)

$$V_{L2}=V_{in}=V_{C4}$$

(2)

During the first mode of operation, the current in both the inductor increases, capacitor C₂ and C₄ charged while C₁ and C₂ discharged, as shown in Figure 3.

During the second mode of operation, when both the switches are turned OFF, diode D₁ and D₃ are conducting while reaming two diodes are reversed biased as shown in Figure 4. The current in both the inductor decreases, capacitor C₁ and C₃ are charged while the other two capacitors are discharged. The related equations during this mode of operation are as follows:

$$V_{L1}=2V_{in}+2V_{C1}-V_O$$

(3)

$$V_{L2}=V_{in}-V_{C1}$$

(4)

Now applying volt-sec balance in inductor L₂.

$${{\displaystyle \int }}_0^T{V}_{L2}\left(t\right)·dt=0$$

(5)

$$V_{in}\times DT+\left(V_{in}-V_{C1}\right)\times \left(1-D\right)T=0$$

(6)

$$V_{C1}=\frac{V_{in}}{1-D}$$

(7)

Now applying volt-sec balance in inductor L₁.

$${{\displaystyle \int }}_0^T{V}_{L1}\left(t\right)·dt=0$$

(8)

$$(V_{in}+V_{C1})\times DT+\left(2V_{in}+2V_{C1}-V_O\right)\times \left(1-D\right)T=0$$

(9)

After combining Equations (7) and (9), the voltage gain (M) of the converter can be written as:

$$V_O=\frac{V_{in}\left(4-4D+D^2\right)}{{(1-D)}^2}$$

(10)

Effect of Inductor’s Parasitic Resistance on Voltage Gain

Due to the circuit’s various components’ internal resistance, there are some power losses in the circuit. Because of these power losses, the voltage gain is not the same as explained before; it is reduced to some lower value. The output voltage, considering the power loss in the inductors, could be calculated as follows:

$$P_{in}=P_o+P_{L_{los{s}_{total}}}$$

(11)

$$P_{in}=\frac{V_{in}{V}_O\left(4-4D+D^2\right)}{R{(1-D)}^2}$$

(12)

$$P_{L_{los{s}_{total}}}={(\frac{V_O}{R\left(1-D\right)})}^2{r}_{L1}+{(\frac{V_O\left(2-D\right)}{R{(1-D)}^2})}^2{r}_{l2}$$

(13)

$$P_o=\frac{V_O{}^2}{R}$$

(14)

After combining the above equations, the output voltage obtained as:

$$V_O=\frac{V_{in}R{(1-D)}^2\left(4-4D+D^2\right)}{R{(1-D)}^4+r_{L1}{(1-D)}^2+r_{l2}{(2-D)}^2}$$

(15)

Using Equation (15), the proposed converter’s non-ideal voltage gain is calculated with the inductor’s parasitic resistance, which is 0.3 Ω for each inductor. The results are compared with the ideal conditions and presented in Figure 5. At lower duty ratios, both the ideal and real voltage gains are the same, but as the duty ratio increases, the deviation between these two becomes large. Further, the deviation increases with the decrease in the load resistance because a reduction in the load resistance increases the current in the circuit, which increases the power loss in the circuit. As the duty ratio is increased, the current in the circuit also increases, which increases conduction power loss in the circuit. Due to this reason, the efficiency of the DC-DC converters decreases at higher duty ratios, and the output voltage gain starts decreasing after reaching its maximum value. It is always recommended to use these converters below a certain value of a duty ratio.

3. Voltage Stress, Current and Passive Component Selection

The voltage stress across S₁, S₂, D₂, and D₄ is obtained by applying KVL during the second mode of operation, as shown in Figure 4. The voltage stress across diodes D₁ and D₃ could be obtained by applying KVL during the first mode of operation. The voltage stress and current across the switches and the diodes are shown in

Table 1. Voltage stress and current across the switches and diodes.

Component	Voltage Stress (Volt)	Average Current during Their Conduction (Amp)	Average Current for the Complete Cycle (Amp)	RMS Current (Amp)
S1	$\frac{V_{in}}{\left(1-D\right)}=\frac{V_O\left(1-D\right)}{\left(4-4D+D^2\right)}$	$\frac{V_O\left(2-D\right)}{R{(1-D)}^2}$	$\frac{V_O\left(2-D\right)D}{R{(1-D)}^2}$	$\frac{V_O\left(2-D\right)\sqrt{D}}{R{(1-D)}^2}$
S2	$\frac{V_{in}}{{(1-D)}^2}=\frac{V_O}{\left(4-4D+D^2\right)}$	$\frac{V_O}{RD\left(1-D\right)}$	$\frac{V_{O}D}{RD\left(1-D\right)}$	$\frac{V_O\sqrt{D}}{R\left(1-D\right)}$
D1	$\frac{V_{in}}{\left(1-D\right)}=\frac{V_O\left(1-D\right)}{\left(4-4D+D^2\right)}$	$\frac{V_O\left(2-D\right)}{R{(1-D)}^2}$	$\frac{V_O\left(2-D\right)}{R\left(1-D\right)}$	$\frac{V_O\left(2-D\right)}{R{(1-D)}^{3/2}}$
D2	$\frac{2V_{in}}{\left(1-D\right)}=\frac{2V_O\left(1-D\right)}{\left(4-4D+D^2\right)}$	$\frac{V_O}{RD}$	$\frac{V_O}{R}$	$\frac{V_O}{R\sqrt{D}}$
D3	$\frac{V_{in}\left(2-D\right)}{{(1-D)}^2}=\frac{V_O\left(2-D\right)}{\left(4-4D+D^2\right)}$	$\frac{V_O}{R\left(1-D\right)}$	$\frac{V_O}{R}$	$\frac{V_O}{R\sqrt{1-D}}$
D4	$\frac{V_{in}}{\left(1-D\right)}=\frac{V_O\left(1-D\right)}{\left(4-4D+D^2\right)}$	$\frac{V_O}{RD}$	$\frac{V_O}{R}$	$\frac{V_O}{R\sqrt{D}}$

. It can be inferred from Table 1 that the voltage stress across switches and diodes is much less than the output voltage, which makes the converter highly efficient. The low voltage stress across capacitors, switches, and diodes and the high voltage gain at lower duty ratios is the distinguishing feature of the proposed converter, making it superior to the literature’s proposed topologies.

For the continuous mode of operation, the minimum current of each inductor should be greater than zero. The minimum current of the inductor depends on the current ripple and average current. The average current of each inductor and the minimum value of inductance of each inductor could be calculated as follows:

$$I_{L1}=\frac{V_O}{R\left(1-D\right)}$$

(16)

$$I_{L2}=\frac{V_O\left(2-D\right)}{R{(1-D)}^2}$$

(17)

$$L_1\ge \frac{R{\left(1-D\right)}^2\left(2-D\right)D}{2f_s\left(4-4D+D^2\right)}$$

(18)

$$L_2\ge \frac{R{\left(1-D\right)}^{4}D}{2f_s\left(4-4D+D^2\right)\left(2-D\right)}$$

(19)

The selection of the capacitors is based on the switching frequency as well as the permissible ripple in the voltage across the relationship between the capacitance, and other parameters are as follows:

$$C_1=\frac{V_O}{R\left(1-D\right)f_s\Delta V_{C1}}=\frac{V_{in}\left(4-4D+D^2\right)}{R{(1-D)}^3{f}_s\Delta V_{C1}}$$

(20)

$$C_2=\frac{V_O}{RD{f}_s\Delta V_{C2}}=\frac{V_{in}\left(4-4D+D^2\right)}{RD{(1-D)}^2{f}_s\Delta V_{C2}}$$

(21)

$$C_3=\frac{V_{O}D}{R{f}_s\Delta V_{C3}}=\frac{V_{in}D\left(4-4D+D^2\right)}{R{(1-D)}^2{f}_s\Delta V_{C3}}$$

(22)

$$C_4=\frac{V_O}{R{f}_s\Delta V_{C4}}=\frac{V_{in}\left(4-4D+D^2\right)}{R{(1-D)}^2{f}_s\Delta V_{C4}}$$

(23)

4. Comparison with Other Recent Topologies

This section compares the proposed topology with some other recent structures of step-up converters. The proposed topology is compared with topologies with quadratic gain and ultra-high gain boost converter [24].

Table 2. Comparison of the proposed topology with other similar topologies.

Topology	NL (Inductors)	NC (Capacitors)	NSW (Switches)	ND (Diodes)	M $({\mathit{V}}_{\mathit{o}}/{\mathit{V}}_{\mathit{i}\mathit{n}})$	S $({\mathit{V}}_{\mathit{S}}/{\mathit{V}}_{\mathit{i}\mathit{n}})$
[9]	2	4	1	4	$\frac{3+D}{2\left(1-D\right)}$	$\frac{1}{1-D}$
[10]	4	1	2	7	$\frac{1+3D}{\left(1-D\right)}$	$\frac{1+D}{1-D}$
[11]	2	3	2	3	$\frac{3+D}{\left(1-D\right)}$	$\frac{1}{1-D}$
[17]	1+1 coupled inductor	3	1	5	$\frac{2-D}{\begin{array}{c}{\left(1-D\right)}^2\\ n=1\end{array}}$	$\frac{2}{1-D}$
[CQBC]	2	2	1	3	$\frac{1}{{\left(1-D\right)}^2}$	$\frac{1}{{\left(1-D\right)}^2}$
[24]	2	4	2	4	$\frac{4}{\left(1-D\right)}$	$\frac{1}{1-D}$
[33]	2	3	1	3	$\frac{1+D}{1-D}$	$\frac{1}{1-D}$
Proposed	2	4	2	4	$\frac{4-4D+D^2}{{\left(1-D\right)}^2}$	$S_1=\frac{1}{1-D}$ $S_2=\frac{1}{{\left(1-D\right)}^2}$

shows the overall comparison of the proposed topology with other recent topologies, where N denotes the number of components. As depicted in Figure 6, the proposed topology has the highest gain in the entire operation range in the non-isolated category of converters with 12 components. The topology’s gain in [9] is less than the proposed converter, although it utilizes four inductors and a total of 14 components. The ultra-high gain boost converter is proposed in [24] and employs 12 components, but its gain is less than the proposed topology. The normalized voltage stress curve versus voltage gain is shown in Figure 7. The switch S₁ has the lowest stress across all compared to the stress on all other topologies. The voltage stress across S₂ is greater than S₁, but for the voltage gain up to 10 times, it is lower than the stress of the converters in [9,10], [CQBC], and [33].

5. Simulation Results and Experimental Verification of the Proposed Converter

5.1. Simulation Results

To test the effectiveness of the proposed converter, the simulations are performed using PLECS software. The V_o at V_in of 24 V and D = 0.4 is found to be 167 V, as shown in Figure 8. The small voltage drop is because of the parasitic and ON state resistances of the converter. The inductor current is continuous, and the average value of I_L1 and I_L2 is found to be 1.1 A and 3.3 A, respectively, as shown in Figure 9. The capacitor voltages are shown in Figure 10. The capacitor voltages of C₁. C₂ and C₄ are 39 V, 63 V, and 23 V, respectively, which is an agreement with the theoretical analysis. The voltage stress across the capacitor is much less than the V_o, which leads to the selection of capacitors of low voltage rating. The choice of low rating components increases the efficiency of the converter. The stress across switch S₁ and S₂ is 40 V and 66 V, as depicted in Figure 11.

5.2. Experimental Verification

The hardware prototype is developed on the power circuit board (PCB) by using Altium Designer software. The designed PCB layout is shown in Figure 12. The hardware prototype is shown in Figure 13a, and the experimental setup is shown in Figure 13b. The specifications of the developed hardware prototype are shown in

Table 3. Specifications of the proposed converter.

Elements	Specification
Input Voltage (Vin)	24 V
Maximum Output Power	150 W
Switching Frequency	50 kHz
Load Resistance	R = 250 Ω, Electronic load simulator
Inductors	L1 = L2 = 330 µH, ESR = 0.3 Ω
Capacitors	C1 = 47 µF/100 V ESR = 0.26 Ω, C2 = C3 = 33 µF/200 V ESR = 0.3 Ω & C4 = 220 µF/50 V ESR = 0.20 Ω
Power MOSFET (S1 & S2)	SPW52N50C3, RDSon = 70 mΩ
Diodes (D1, D2, D3 & D4)	SF8L60USM, Vd = 0.6 V
Gate Drivers IC	TLP250H
Gate Driver Voltage Regulator IC	MCWI03-48S15
Microcontroller	STM32 Nucleo H743ZI2

. The theoretical and simulation results are confirmed by developing a prototype and of 150 W in the lab. Figure 14 shows the experimental waveform of the V_o at V_in = 24 V and D = 0.4. V_o is found to be 167 V, which in agreement with the derived voltage gain. The high gain of 7 times is obtained at a low-duty ratio is the converter’s main advantage. The experimental inductor current waveforms are shown in Figure 15. The capacitor voltages are shown in Figure 16. The capacitor voltages of C₁, C₂, and C₄ are much less than the output voltage V_o, which means that except for the output capacitor C₃ all the other capacitors have low voltage stress across them.

The stress across switch S₁ and S₂, as depicted in Figure 17, is found to be 40 V and 66 V, which is also much less than the V_O.

6. Efficiency Calculation

For the calculation of efficiency, the power loss in each component needs to be determined. The losses in switches are bifurcated into switching and conduction losses. The parasitic and ON state resistances are shown in Table 2. The total switching loss in switches S₁ and S₂ is found to be 0.298 W. The total conduction loss is found to be 0.773 W. The loss in capacitors:

$$\{\begin{array}{c}{P}_{S_{los{s}_{conduction}}}=P_{{S1}_{los{s}_{conduction}}}+P_{{S2}_{los{s}_{conduction}}}\\ P_{S_{los{s}_{conduction}}}=i_{S{1}_{RMS}}^2\times r_{S1}+i_{S{2}_{RMS}}^2\times r_{S2}\\ ={\left(\frac{V_O\left(2-D\right)\sqrt{D}}{R{(1-D)}^2}\right)}^2{r}_{S1}+{\left(\frac{V_O\sqrt{D}}{R\left(1-D\right)}\right)}^2{r}_{S2}\\ P_{S_{los{s}_{conduction}}}=0.285 W\\ P_{S_{los{s}_{switching}}}=\frac{\left(t_{on}+t_{off}\right)\left(I_{S1on}{V}_{S1off}+I_{S{2}_{on}}{V}_{S2off}\right)\times f_s}{2}=0.298 W\\ P_{S_{los{s}_{\left(conduction+switching\right)}}}=0.583 W\end{array}$$

(24)

The diode cut-in voltage for all diodes is 0.6 V the resistance is 0.06 Ω. The power loss for each of the diodes for an output voltage of 167 V and output power of 111.56 W can be calculated as shown.

$$\{\begin{array}{c}{P}_{D{1}_{loss}}=V_{D1}{I}_{D{1}_{avg}}+i^2{}_{ D{1}_{RMS}}{r}_{D1}\\ P_{D{1}_{loss}}=1.386 W\\ P_{D{2}_{loss}}=V_{D2}{I}_{D{2}_{avg}}+i^2{}_{D{2}_{RMS}}{r}_{D2}\\ P_{D{2}_{loss}}=0.57W\\ P_{D{3}_{loss}}=V_{D3}{I}_{D{3}_{avg}}+i^2{}_{D{3}_{RMS}}{r}_{D3}\\ P_{D{3}_{loss}}=0.475 W\\ P_{D{4}_{loss}}=V_{D4}{I}_{D{4}_{avg}}+i^2{}_{D{4}_{RMS}}{r}_{D4}\\ P_{D{4}_{loss}}=0.57 W\\ P_{D_{loss}{}_{total}}=3.001 W\end{array}$$

(25)

The total conduction losses in diodes are found to be 3 W.

The total conduction losses in capacitors are found to be 2.04 W.

$$\{\begin{array}{c}{P}_{C_{los{s}_{total}}}=i^2{}_{C{1}_{RMS}}{r}_{C1}+i^2{}_{C{2}_{RMS}}{r}_{C2}+i^2{}_{C{3}_{RMS}}{r}_{C3}+i^2{}_{C{4}_{RMS}}{r}_{C4}\\ ={(\frac{V_O}{R\left(1-D\right)}\sqrt{\frac{1+D-D^2}{D}})}^2{r}_{C1}+{(\frac{V_O}{R}\sqrt{\frac{1}{D\left(1-D\right)}})}^2{r}_{C2}+{(\frac{V_O}{R}\sqrt{\frac{D}{\left(1-D\right)}})}^2{r}_{C3}+{(\frac{V_O}{R}\sqrt{\frac{1}{D\left(1-D\right)}})}^2\\ =0.9 W+0.55 W+0.22 W+0.37 W\\ P_C{}_{los{s}_{total}}=2.04 W\end{array}$$

(26)

The parasitic resistance of each coil is found to be 0.3 Ω. The loss in coils L₁ and L₂ can be computed as:

$$\{\begin{array}{c}{P}_{L_{los{s}_{total}}}=i^2{}_{L{1}_{RMS}}{r}_{L1}+i^2{}_{L{2}_{RMS}}{r}_{L2}\\ ={(\frac{V_O}{R\left(1-D\right)})}^2{r}_{L1}+{(\frac{V_O\left(2-D\right)}{R{(1-D)}^2})}^2{r}_{l2}\\ =0.372 W+2.64 W\\ =3.01 W\end{array}$$

(27)

The total conduction losses in inductors are found to be 3.01 W. The bifurcation of losses in various components are shown in Figure 18. The loss in diodes and switches constitute around 46 percent of the total losses. The total loss in the converters is found to be 8.634 W.

Efficiency (η) of the converter can be expressed as:

$$\{\begin{array}{c}\eta =\frac{P_0}{P_0+P_{,loss}+P_{D,loss}+P_{C,loss}+P_{L,loss}}\\ \eta \%=\frac{\frac{{167}^2}{250}}{\frac{{167}^2}{250}+8.634}\times 100=92.82\%\end{array}$$

(28)

For an output power of 111.56 W, the efficiency is found to be 92.82%. The variation of efficiency with output power is shown in Figure 19a. The efficiency of the converter increases as the input voltage is increased. This increase in efficiency is because at higher input voltages, a small duty ratio is required to get the same amount of voltage gain, and hence conduction losses are significantly reduced. In Figure 19b, the comparison of efficiency at an input voltage of 24 V is shown. The coupled inductor topology proposed in [17] has higher efficiency than the proposed converter.

7. Performance of the Proposed Converter in Dynamic Conditions

The dynamic conditions are presented in Figure 20 and Figure 21. While changing the duty ratio, the load resistance is kept constant at 200 Ω. With the increase in the duty ratio, the voltage gain increases without any transient, as shown in Figure 20. To capture the dynamic load change, the electronic load is set to change its load between 100% and 75% of the rated load, and the duty ratio is kept constant at 0.4. With the increase in the load, the output current increases, which increases the internal power losses in the circuit, and output voltage decreases a little bit, as shown in Figure 21.

8. Discussion

From the steady-state and dynamic performance, it can be observed that the converter is working satisfactorily in an open loop. The output voltage and currents obtained through experimental investigations closely match the theoretical and simulation results. Further, the stress across switches capacitors and diodes is less than the output voltage. The low voltage stress leads to the selection of devices with low voltage ratings, which ultimately improves efficiency and decreases the converter’s cost. The proposed converter is suitable for low and medium power applications. It is to be noted that the parasitic resistances of inductors decrease the voltage gain and the efficiency of the converter [38,39]. To increase the converter’s gain and efficiency at high duty ratios, a coupled inductor can also be used in the proposed topology instead of two separate inductors.

9. Conclusions

The main challenge in developing high gain DC-DC converters is to get high voltage gain by keeping the stress across devices low. Further, the number of components should also be optimized so that the converter cost is low and high efficiency can be obtained. These features are obtained in the proposed high gain converter. The converter has been successfully developed, and its performance is validated through simulation and experimental results. The converter’s loss analysis reveals its good performance with more than 91% efficiency throughout the input power range. The peak efficiency was found to be 93.6% at 66 W output power. The voltage gain of the converter is high at low duty ratios. A gain of more than 12 times can be achieved in ideal conditions at a duty ratio of 0.6. However, the actual gain depends on the parasitic values of different components and the load resistance. Overall, the proposed converter has shown good performance in non-isolated category of converters and can be employed in industrial, energy storage, and PV applications.