X-Type Step-Up Multi-Level Inverter with Reduced Component Count Based on Switched-Capacitor Concept

Abstract

This paper aims to present a novel switched-capacitor multi-level inverter. The presented structure generates a staircase near sinusoidal AC voltage by using a single DC source and a few capacitors to step-up the input voltage. The nearest level control (NLC) strategy is used to control the operation of the converter. These switching states are designed in a way that they always ensure the self-voltage balancing of the capacitors. Low switching frequency, simple control, and inherent bipolar output are some of the advantages of the presented inverter. Compared to other existing topologies, the structure requires fewer circuit elements. Bi-directional power flow ability of the proposed topology, facilitates the operation of the circuit under wide range of load behaviors which makes it applicable in most industries. Besides, a 13-level laboratory prototype is implemented to realize and affirm the efficacy of the MATLAB Simulink model under different load conditions. The simulation and experimental results accredit the appropriate performance of the converter. Finally, a theoretical efficiency of 92.73% is reached.

1. Introduction

Nowadays, due to the progress of power electronic devices, an increase in fossil fuel prices, and global tendency towards emitting fewer greenhouse gases, most industries tend to utilize renewable energy sources. Especially wind and solar energies have received a great deal of attention among them. Various types of electrical power converters are used to connect these renewable energy sources to the local grids, including inverters which perform the DC to AC power conversion. Multilevel inverters (MLIs), which can generate a high-quality voltage, have become more applicable recently [1,2,3]. They are capable of generating near sinusoidal staircase voltage, which leads to a remarkable decrease in voltage stresses across the switching devices (dv/dt) and total harmonic distortion (THD) of the output. Therefore, the output filter would be reduced in size or even removed [2,4,5,6,7,8].

MLIs play a significant role in applications such as fuel cells [9], solar panels [10], electric vehicles [11], wind turbines, and connecting them to the network grid [12]. The evolution of MLIs during time is illustrated in Figure 1. As conventional MLI topologies, neutral point clamped (NPC) [13], flying capacitor (FC) [14], and cascaded H-bridge (CHB) [15] have some weaknesses. These topologies have a few advantages over two-level inverters such as: Less switching and conduction losses, higher efficiency, and remarkably more power quality. On the other hand, they suffer from sophisticated control methods. Furthermore, NPC and FC struggle with voltage imbalance of their DC link capacitors and CHB requires several independent DC sources [16].

Moreover, when an increase in output voltage levels (to lower the THD) is intended, the semiconductor devices count will considerably increase. The above-mentioned factors restrict the application of these converters in high voltage levels [6]. As a result, attaining maximum possible voltage levels with the least number of DC input sources and semiconductor devices has become the main objective for experts in the field of MLIs. As an alternative, switched-capacitor multi-level inverters (SCMLIs) were proposed to cover these issues. In this context, many new converters were designed to decrease the number of components such as semiconductors, DC sources, capacitors, and implementation costs [4].

The SCMLI circuits presented in [6,16], are comprised of the connection of a few DC/DC converters and an H bridge to change the polarity of the output. The DC/DC part is made up of a serial connection of switched-capacitor cells. Using a single DC source and multiplying the input voltage are the main advantages of these topologies [17]. However, they require many capacitors and switches, which increases the size, complexity, and overall cost of these structures. Furthermore, using an H bridge in these circuits oblige the four switches to withstand the maximum of the output voltage [18]. As a result, the need for high voltage switches restricts the application of such topologies in medium and high voltage. Hence, to overcome this concern, several step-up SCMLI with a single input source are presented in [19,20,21]. In this case, voltage stress across the circuit elements has been reduced, which leads to the reduction of the total standing voltage (TSV) of the structure. However, the appliance of series diodes with switches in [19] prevents the power flow back to the source. Bidirectional power flow ability, prevents the capacitors from over-charging and potential damages. Ergo, the excess charge is fed back to the input source. As a result, another crucial character for an SCMLI circuit is whether the inverter can be used in application with bi-directional power flow or not. This paper presents a novel switched-capacitor multilevel converter suitable for medium and high power usage.

The proposed topology requires no external circuit or complex control algorithm to maintain its capacitors’ voltage balance. The voltage boosting and reducing the semiconductor devices count are the advantages of the presented structure over conventional topologies. Since the proposed circuit inherently generates a bipolar voltage without using an H-bridge, the switching losses and voltage stresses across the semiconductor devices are reduced considerably.

The rest of this paper is organized as follows: Section 2 describes the proposed structure, its operating principles, capacitors charging paths, and the modulation strategy in detail. A comparative study, along with the determination of the circuit capacitances, power loss analysis, and efficiency calculations are carried out in Section 3. Then, the simulation and experimental results of the proposed inverter are brought in Section 4. At last, conclusion of this paper is added to Section 5.

2. Proposed Topology: Structure and Operating Principals

Figure 2 depicts the proposed switched capacitor topology. This circuit structure uses 3 capacitors and a single DC source to boost the input voltage 6 times and generate 13 levels in the output. Likewise, it consists of 15 power switches (including 13 uni-directional and one bi-directional) and 14 driving circuits to form the required current paths.

Each level of the staircase output voltage is achieved by a predetermined combination of capacitors and/or the DC source. A high-quality voltage can be obtained provided that: All capacitors are charged sufficiently, voltages of the capacitors and voltages across the switches does not exceed their rated values and the capacitors’ voltage drop remains in an acceptable range [22]. As shown in Figure 3, C₁ and C₂ are charged directly by the input source up to V_dc. Capacitor C₃ can be charged up to 3V_dc by a series combination of C₁, C₂, and DC source (Figure 3c).

Table 1. Corresponding switching states of the proposed circuit.

State	Active Switches	Output Voltage	C1	C2	C3
1	S1,S4,S5,S9,S10,S11,S14	+6Vdc	▼	▼	▼
2	S1,S3,S4,S7,S9,S10,S11,S14	+5Vdc	▼	▲	▼
3	S1,S3,S5,S6,S9,S10,S11,S14	+5Vdc	▲	▼	▼
4	S1,S6,S7,S9,S10,S11,S14	+4Vdc	-	-	▼
5	S1,S4,S5,S8,S9,S11,S12,S14	+3Vdc	▼	▼	▲
6	S1,S3,S4,S7,S9,S12,S14	+2Vdc	▼	▲	-
7	S1,S3,S5,S6,S9,S12,S14	+2Vdc	▲	▼	-
8	S1,S6,S7,S9,S12	+1Vdc	-	-	-
9	S1,S4,S5,S8,S9,S11,S12,S13	0	▼	▼	▲
10	S2,S4,S5,S8,S9,S11,S12,S14	0	▼	▼	▲
11	S2,S6,S7,S8,S11,S13	−1Vdc	-	-	-
12	S2,S3,S5,S6,S8,S11,S13	−2Vdc	▲	▼	-
13	S2,S3,S4,S7,S8,S11,S13	−2Vdc	▼	▲	-
14	S2,S4,S5,S8,S9,S11,S12,S13	−3Vdc	▼	▼	▲
15	S2,S6,S7,S8,S10,S12,S13	−4Vdc	-	-	▼
16	S2,S3,S5,S6,S8,S10,S12,S13	−5Vdc	▲	-	-
17	S2,S3,S4,S8,S10,S12,S13	−5Vdc	▼	▲	▼
18	S2,S4,S5,S8,S10,S12,S13	−6Vdc	▼	▼	▼

brings the switching states and their relevant capacitors’ state of charge. In addition, charging, discharging, and no change states of the circuit capacitors are shown by “▲”, “▼”, and “-”, respectively.

The procedure of generating voltage levels is as follows:

• Level +6V_dc: Figure 4a illustrates the current path for generating this level. Capacitors C₁, C₂, and C₃ are discharged across the load in series with the input source.
• Level +5V_dc: Two different switching states can be used to make this level. One is through the series connection of C₁, C₃, and DC source while charging C₂ simultaneously. The other is through series connection of C₂, C₃, and DC source while charging C₁ simultaneously.
• Level +4V_dc: C₃ and DC source make this level together.
• Level +3V_dc: This level is built with the help of C₁ and C₂ along with the DC source. Moreover, C₃ can be charged at the same time.
• Level +2V_dc: To make this level, there are two switching states. First, C₁ is discharged across the load with the DC source and at the same time C₂ is charged. Second, the capacitor C₂ and the input source supply the load and simultaneously C₁ is charged.
• Level +1V_dc: The voltage source is only used to make this voltage level (Figure 4b).
• Level zero: There are two switching states to form the level zero: First by turning the S₁, S₈, S₁₁, and S₁₃ switches on. Second using the switches S₂, S₉, S₁₂, and S₁₄. Moreover, C₃ can be charged through the C₁, C₂, and DC source, as shown in Figure 4c.
• Negative voltage levels of −1V_dc, −2V_dc, …, −6V_dc are obtained similarly.

2.1. Modulation Strategy

Figure 5a shows the control procedure of producing a near sinusoidal waveform, with a 50 Hz reference frequency. The switching angles t_i (i = 0, 1, 2, …, n) are selected based on nearest level control (NLC) method. Then, by applying these predetermined time intervals to the circuit with their corresponding switching states, the desired output waveform is shaped. This strategy tracks the closest voltage level of the sample staircase waveform to the reference [23].

By using this method, the time intervals of each voltage level to produce the desired output voltage is estimated. Then, using the switching states of Table 1 and based on the charging and discharging modes of the capacitors, the appropriate switching state for making each voltage level is selected (Figure 5b) [20].

2.2. Extended Topology

The proposed X-Type topology can be extended in case a higher output is required. For high power AC application, an extension for the simple module is introduced to achieve higher voltage levels. So that, by use of a single input source and ($\frac{n}{3} + 1$) capacitors, (2n + 1) voltage levels can be generated. It depends on the type of application and the output voltage required. In some cases, the input source is capable of supplying the required load current in high voltage application. Hence, Figure 6 version is preferred. Moreover, when multiple DC sources are available such as solar panels, this can be a very good option to collect all of the low voltage panels and connect them to each other in order to reach higher AC output voltages in both stand-alone and grid connected application.

Moreover, as some applications normally use low voltage DC sources, high amounts of currents are drawn from the sources in the case of single DC source when a boost AC output voltage is required. This may limit the power ranges of SCMLIs due to high current ratings of some power semiconductors. This problem can be solved by using multiple DC sources to split the amount of input current between different sources and different semiconductors. On the other hand, size of capacitors reduces as they are able to balance their voltage using paths through more DC sources. It seems that hybrid SCMLI with multiple DC sources is an intermediate solution for the drawbacks of single DC source SCMLI (high current ratings at high power application) and cascaded MLIs (high number of DC sources). Besides, by modular connection of SC cells, voltage of last cells may reduce. To achieve higher output voltages, it is needed to add some DC sources between the modules to keep the voltage in an acceptable range.

To overcome these problems, as shown in Figure 7, several basic SCMLI units of Figure 2 can be cascaded to achieve higher output voltage levels. This method would be useful where a few DC sources or DC links are accessible. The amount of different DC sources can be equal or asymmetric which depends on the number of required voltage levels and the type of application.

In the context of step-up SCMLI in a real application, it is essential to design a topology to use maximum possible standard rating of the switches. Therefore, the input voltage should be raised until the peak inverse voltage (PIV) is less than a certain acceptable range percentage (x%) of the switches rated voltage ($V_{rated}^{SW}$) as PIV < x%$V_{rated}^{SW}$.

3. Discussion

3.1. Determination of Capacitance

The voltage drop of the circuit capacitors in a switched capacitor converter (due to repeated charging and discharging cycles) should stay in an acceptable range. The scale of this range depends on the capacitance, discharge time, and the load current. The smaller the ripple, the lower the power losses and the higher the capacitors’ efficiency [21,24]. The maximum discharge rate ($\Delta Q$) for each capacitor is obtained by:

$$\Delta Q={\displaystyle \underset{t_s}{\overset{t_f}{\int }}{I}_{out}\sin (2\pi f_{ref}t)dt}$$

(1)

where, f_ref is the output frequency and I_out is the amplitude of the load current. Besides, [t_s, t_f] is the longest possible time interval in which each capacitor is discharged, assuming the worst case [2]. On the other hand, the maximum output current can be calculated by:

$$I_{load-\max }=\frac{V_{load-\max }}{R}=\frac{6V_{in}}{R}$$

(2)

Note that the capacitances C₁ and C₂ are the same. As the voltage of C₃ is three times the input, then its capacitance is one third of the other two capacitors. Then, the maximum discharge rate can be achieved by:

$$\Delta Q={\displaystyle \underset{t_s}{\overset{t_f}{\int }}{I}_{load-\max }}\sin (2\pi f_{ref}t)dt={\displaystyle \underset{t_s}{\overset{t_f}{\int }}\frac{6V_{in}}{R}}\sin (2\pi f_{ref}t)dt$$

(3)

Taking k as the acceptable ripple percentage (or ripple curtailment), the capacitance is obtained as follows:

$$C_{eq}\ge \frac{\Delta Q_c}{K{V}_{in}}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\Rightarrow \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}{C}_{eq}\ge \frac{6}{kR}{\displaystyle {\int }_{t_s}^{t_f}\sin (2\pi f_{ref}t)}\hspace{0.17em}dt$$

(4)

Since C_eq is formed by the series connection of the three capacitors, its capacitance is one fifth of C₁. Accordingly, the variation of the determined capacitance versus the load (R) changes with regard to the ripple curtailment is illustrated in Figure 8.

3.2. Power Loss Analysis

Generally, power loss in switched-capacitor converters are classified into three groups: switching loss, conduction loss, and the loss caused by capacitor voltage ripple [2,20,25,26].

3.2.1. Switching Losses

Switching loss caused by a delay in switch’s turn-on and turn-off time, is one of the major contributions for the power loss. Semiconductors have this kind of loss intrinsically. When the Semiconductor switch turns on, gate-emitter voltage reaches the threshold voltage and also the collector current increases and collector-emitter voltage has a downward trend until it reaches the on-state voltage of the switch that shows the turn on cycle is over. Similarly, in an opposite way in turn-off cycle and at the end of turn-off cycle, gate-emitter reaches the saturation voltage. Collector current and emitter voltage rise and finally the turn-off process ends [27]. Turn-on and turn-off loss for active switches is calculated by Equations (5) and (6).

$$\begin{array}{ll}{P}_{s,on}& =f_s{\displaystyle {\int }_0^{t_{on}}{V}_{off-state}(t)i_s(t)}dt=f_s{\displaystyle {\int }_0^{t_{on}}\left(\frac{I_{on-state}}{t_{on}}t\right)}\left(\frac{-V_{off-state}}{t_{off}}(t-t_{on})\right)dt\hspace{0.17em}\hspace{0.17em}\\ & =\frac{1}{6}{f}_s{V}_{off-state}{I}_{on-state}{t}_{on}\end{array}$$

(5)

$$\begin{array}{ll}{P}_{s,off}& =f_s{\displaystyle {\int }_0^{t_{off}}{V}_{off-state}(t)i_s(t)}dt=f_s{\displaystyle {\int }_0^{t_{off}}\left(\frac{V_{off-state}}{t_{off}}t\right)}\left(\frac{-I_{on-state}}{t_{off}}(t-t_{off})\right)dt\\ & =\frac{1}{6}{f}_s{V}_{off-state}{I}_{on-state}{t}_{off}\end{array}$$

(6)

where, V_off-state and I_on-state are off-state voltage and switch current when the switch becomes fully turned on, respectively. Switching losses which is the sum of turn-on and turn-off loss is calculated by Equation (7):

$$P_{sw}={\displaystyle \sum _{j=1}^{N_{switch}}\left(P_{sj,on}+P_{sj,off}\right)}$$

(7)

3.2.2. Conduction Losses

Conduction loss for power switches and power diodes is calculated by [2,23]:

$$P_{con-L}=(k_1{V}_{on}^{sw}+k_2{V}_{on}^D)i_{av-L}+(k_1{R}_{on}^{sw}+k_2{R}_{on}^D)i_{rms-L}^2$$

(8)

where, $V_{on}^{sw}$, $V_{on}^D$ are the on-state voltage of switch and the on-state voltage of diode, respectively. Additionally, $R_{on}^{sw}$ is on-state resistance of switches and $R_{on}^D$ is on-state resistance of diode [22,25]. The parasitic resistance of the circuit elements in each level (V_j = 0, ±1V_in, ±2V_in, ±3V_in, ±4V_in, ±5V_in, and ±6V_in) are listed in

Table 2. Equivalent parasitic resistance for each level.

Output Voltage Level	Equivalent Parasitic Resistance
0	6Ronsw + 1RonD
±1Vin	3Ronsw + 3RonD
±2Vin	4Ronsw + 3RonD
±3Vin	6Ronsw + 2RonD
±4Vin	5Ronsw + 2RonD
±5Vin	6Ronsw + 2RonD
±6Vin	7Ronsw

. I_rms and I_avg are the root mean square (RMS) and average current of semiconductors that obtain from Equation (9). It should be noted that k₁ and k₂ are the number of the switches which have been shown in this table.

$$\hspace{0.17em}{i}_{av}(n{V}_{dc})=\frac{2}{\pi }{\displaystyle {\int }_{t_a}^{t_b}\left[{\mathrm{I}}_m\sin tdt\right]}\hspace{0.17em},\hspace{0.17em}\hspace{0.17em}{i}_{rms}(n{V}_{dc})=\sqrt{\frac{2}{\pi }{\displaystyle {\int }_{t_a}^{t_b}{\left({\mathrm{I}}_m\sin t\right)}^{2}dt}}$$

(9)

Finally, the total conduction losses for the proposed 13-level X-Type inverter can be calculated by:

$$P_{con}^{total}=2{\displaystyle \sum _{k=1}^6{P}_{con}^{\left(k{V}_{dc}\right)}}+2{\displaystyle \sum _{m=-1}^{-6}{P}_{con}^{\left(m{V}_{dc}\right)}}$$

(10)

3.2.3. Losses Due to the Capacitors Voltage Ripple

The difference between the input DC voltage and the capacitor voltage is the essential of the capacitor ripple loss [19]. The ripple of the capacitor’s voltage obtained from:

$$\Delta V_{ripple,C}=\frac{1}{C}{\displaystyle {\int }_{t_c}^{t_d}{i}_C(t)}dt$$

(11)

It is worth mentioning I_c is the capacitor current and [t_c, t_d] is the discharge time of the capacitor that the period of discharge time for 13-level X-Type converter. So, the capacitor’s voltage ripples losses obtain from Equation (12). Finally, sum of the losses and efficiency are calculated by Equation (13), where P_in and P_out are the converter’s input and output powers, respectively.

$$P_{Rip}=\frac{f_{ref}}{2}\left(C_i\Delta V_{ripple,C}^2\right)$$

(12)

$$\eta =\frac{P_{out}}{P_{out}+P_{Loss}}=\frac{P_{out}}{P_{out}+P_{Sw}+P_{Con}+P_{Rip}}$$

(13)

3.3. Comparative Study

A comparative study is conducted between the proposed structure and several recently published articles on single-source structures in

Table 3. Comparison between the proposed converter and other topologies.

Items	[21]	[16]	[27]	[6]	[19]	X-Type
No. of Capacitors	$n-1$	$n-1$	$n-1$	$n-1$	$n-1$	$\frac{n}{3}+1$
No. of Switches	$3n+4$	$n+5$	$2n+4$	$3n+1$	$5n-1$	$\frac{5}{3}n+5$
No. of Drivers	$3n+4$	$n+5$	$2n+4$	$3n+1$	$5n-1$	$\frac{5}{3}n+4$
No. of Series Diodes	0	$2n-2$	$2n-2$	0	0	0
PIV(×VIN)	$n$	$n$	$n$	$n$	$1$	$3$
TSV(×VIN)	$7n-3$	$n^2+6n+4$	$n^2+5n+1$	$\frac{n^2}{2}+5n$	$5n-1$	$5n+2$
Polarity Generating	H-bridge	H-bridge	H-bridge	H-bridge	inherent	inherent
Bi-Directional Power Flow	NO	NO	YES	NO	NO	YES

. This comparison is based on the number of capacitors, semiconductor devices (diodes and active switches), starter circuits, bi-directional power flow ability, PIV, and TSV per (2n + 1) output levels.

According to the table, the proposed structure requires a smaller number of capacitors (approximately one-third) to generate the same output level. The circuits introduced in [6,16,21] consist of two parts for generating voltage levels and polarity. Therefore, they are not suitable for high-voltage applications. However, [19] and the proposed circuit can change the polarity of the load voltage without the need for an auxiliary circuit. Furthermore, the PIV and TSV in [19] are the lowest among other structures; however, it uses the most semiconductor components. It should be noted that the diodes in [16,19] limit the ability to absorb power from the load whenever it is needed.

To better understand the relative superiority of the proposed structure, the graphical comparison of the number of semiconductors used, capacitors, and TSV for different number of output levels is illustrated in Figure 9.

4. Performance Evaluation

This section presents a set of both simulation and experimental results in order to accredit the performance and effectiveness of the proposed model for a 13-level X-Type converter.

4.1. Simulation Results

To evaluate the function of the proposed 13-level X-Type converter, simulation studies are conducted in MATLAB Simulink environment with the characteristics listed in

Table 4. Simulation parameters in MATLAB.

Parameters	Values
Input DC Source (Vin)	30 V
Boost Ratio (n)	6
Output frequency (fo)	50 Hz
Capacitances (C)	C1 = C2 = 4700 µF, C3 = 2200 µF
Load (ZL)	90 Ω, 318 mH

.

It should be noted that because of using low voltage capacitors, their physical dimensions are remarkably small. Figure 10a,b displays the voltage waveform and the output current under the resistive and resistive-inductive load, respectively. At inductive load, the output current is smooth. Figure 10c shows the harmonic spectrum of the output voltage. The output’s THD is 6.42%. It can be seen that the amplitude of all unwanted harmonics are kept below 5% satisfying the IEEE-Std. 519-2014.

In order to highlight the capability of the proposed structure in an instantaneous load change condition, the following scenario was implemented in a way that the load changes between Z_L1 and Z_L2. Figure 11a shows the output current changes during instantaneous change. Likewise, during this condition, the capacitors follow the reference voltage representing the right function of the circuit which is shown in Figure 11.

4.2. Experimental Results

Experimental model for a 13-level converter was tested to verify the function of the circuit in the power electronics laboratory (see Figure 12a). Characteristics of the experimental model are listed in

Table 5. Specifications of the proposed 13-level X-Type inverter.

Parameters	Values
Input DC voltage (Vin)	30 V
Boost Ratio (n)	6
Output Frequency (fo)	50 Hz
Capacitances (C)	C1 = C2 = 4700 µF, C3 = 2200 µF
Load (ZL)	90 Ω, 318 mH
Main Switches (MOSFET)	IRFP460
Opto-coupler Driver	HCPL-3120
Main Control Chip	AVR ATMEGA16A
Voltage Probe	PINTEK DP-50
Current Probe	FLUKE 80i-110s AC/DC

. Switching pulses were generated by AVR-ATMEGA16A microcontroller. The switching process is written in BASCOM software and loaded onto the microcontroller. Similarly, for preventing damage to the low-voltage devices, the power circuit and control circuit were isolated electrically by utilizing opto-coupler HCPL3120 in gate driver circuit which is shown in Figure 12b.

Output voltage and current under resistive and resistive-inductive loads are shown in Figure 13a,b. A voltage source of 30 V is considered as input. The maximum output voltage is 180 V and also each voltage step is 30 V. An important feature of this structure is the capability of boosting the input voltage, about, six times and as an example of the voltage of the switches, the voltage across the S₁ is displayed in Figure 13c.

The transient performance of the proposed structure is evaluated by the load changing between Z_L1 = 250 Ω and Z_LP (Z_LP = Z_L1|| Z_L2, Z_L2 = 170 Ω) sequentially. In this way, the converter is operating normally under load Z_L1 and suddenly another load (Z_L2) is connected in parallel. To better demonstrate the impact of such sudden load change, Z_L2 is connected and disconnected repeatedly. Figure 14 illustrates the results of the function of the converter under sudden load changes. As revealed in this figure, the capacitors follow the reference voltage, and their voltages fluctuate within an acceptable range. So, the proposed converter has no need for any complex algorithm or external circuit for balancing the capacitor’s voltage.

5. Conclusions

In this paper, a 13-level single-source inverter with boosting capability is introduced. The ability to increase the input Voltage six times without using any inductor or transformer and also the self-balance of the capacitor’s voltage without the use of an external controller are the main advantages of this converter. A comparative study with some recent topologies shows that the proposed structure reduced the number of semiconductor components compared to other structures, which would reduce the implementing cost. This structure has less TSV and PIV than similar structures which provides conditions to reach higher levels. In particular, the modulation strategy, the calculation of the capacitance, the switching losses, and, also, conduction loss for the proposed structure have been investigated. The efficiency of the 13-level structure presented is 92.73%, and, also, the THD of output voltage for the proposed structure is 6.42%. Finally, experimental results of the proposed converter, verify its correct operation under different (resistive and resistive-inductive) loads and also instantaneous load change on the output. By analyzing the results, the proposed inverter is regarded as a suitable choice for renewable energy applications with low number of DC sources and also it is appropriate for voltage boosting at the output.