# Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Error Magnitude Evaluation in Reed–Solomon Codes

#### 2.1. Forney Method

#### 2.2. Lu Method

## 3. Hardware Configuration

## 4. Results and Discussion

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 4.**Error magnitude evaluation with $\nu =3$ implemented with the Forney algorithm. The blocks shown are additions, multiplications, and inversions (${(\xb7)}^{-1}$) over the Galois field.

**Figure 5.**Error magnitude evaluation with $\nu =3$ implemented with the Lu algorithm. The blocks shown are additions, multiplications, and inversions (${(\xb7)}^{-1}$) over the Galois field.

**Figure 6.**Register transfer level (RTL) result of the Forney method for the RS(15,11) configuration.

**Figure 9.**Flowcharts used for the C language implementation of the Forney (

**a**) and Lu (

**b**) methods. GPIO, general-purpose input/output.

**Figure 10.**Oscilloscope measurements of the GPIO pin for the configuration F of Table 3 in the case of FPGA implementation. (

**a**) Measurement of the execution time of the Forney algorithm. (

**b**) Measurement of the execution time of the Lu method.

**Figure 11.**Graphical representation of the results of Table 4. (

**a**) FPGA implementations resources’ usage in terms of cell look-up tables (LUTs), (

**b**) FPGA implementations’ output delay.

**Figure 12.**Oscilloscope measurements of the GPIO pin for the configuration F of Table 3 in the case of MCU implementation. (

**a**) Measurement of the execution time of Forney’s algorithm, (

**b**) Measurement of the execution time of Lu’s method.

**Figure 13.**Graphical representation of the results of Table 5 regarding the MCU implementations’ code execution time.

Galois Operation | Forney’s Method | Lu’s Method |
---|---|---|

Addition | ${N}_{\oplus}=\nu \left(\u23a3\frac{\nu -1}{2}\u23a6+\frac{3\left(\nu -1\right)}{2}\right)$ | ${N}_{\u2a01}=\frac{3\nu \left(\nu -1\right)}{2}$ |

Multiplication | ${N}_{\u2a02}=\nu \left(\u23a3\frac{\nu +1}{2}\u23a6+\frac{3\nu -1}{2}\right)$ | ${N}_{\u2a02}=\frac{\nu \left(3\nu -1\right)}{2}$ |

Inversion | ${N}^{-1}=\nu $ | ${N}^{-1}=\nu -1$ |

**Table 2.**Numerical example of equations of Table 1.

Number of Errors | Forney’s Method | Lu’s Method |
---|---|---|

$\nu =3$ | ${N}_{\u2a01}=12$ | ${N}_{\u2a01}=9$ |

${N}_{\u2a02}=18$ | ${N}_{\u2a02}=12$ | |

${N}^{-1}=3$ | ${N}^{-1}=2$ |

Configuration Name | m | $\left(\mathit{n},\mathit{k}\right)\text{}\mathbf{Notation}$ | Number of Correctable Errors (t) |
---|---|---|---|

A | 4 | (15,11) | 2 |

B | 4 | (15,9) | 3 |

C | 4 | (15,7) | 4 |

D | 8 | (255,249) | 3 |

E | 8 | (255,239) | 8 |

F | 8 | (255,223) | 16 |

System Configuration | Forney | Lu | ||
---|---|---|---|---|

Cell LUTs | Time (ns) | Cell LUTs | Time (ns) | |

A | 56 | 6.7 | 62 | 8.3 |

B | 163 | 10.2 | 138 | 15.2 |

C | 263 | 11.7 | 268 | 22.5 |

D | 828 | 20.8 | 760 | 32.8 |

E | 7126 | 47 | 6081 | 71 |

F | 27,100 | 72.2 | 21,082 | 136.4 |

System Configuration | Forney | Lu |
---|---|---|

Time (µs) | Time (µs) | |

A | 186.1 | 169.8 |

B | 668.1 | 389.3 |

C | 1400 | 699.2 |

D | 1100 | 607.3 |

E | 15,900 | 4500 |

F | 110,600 | 18,300 |

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**MDPI and ACS Style**

Bianchi, V.; Bassoli, M.; De Munari, I.
Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes. *Electronics* **2020**, *9*, 89.
https://doi.org/10.3390/electronics9010089

**AMA Style**

Bianchi V, Bassoli M, De Munari I.
Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes. *Electronics*. 2020; 9(1):89.
https://doi.org/10.3390/electronics9010089

**Chicago/Turabian Style**

Bianchi, Valentina, Marco Bassoli, and Ilaria De Munari.
2020. "Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes" *Electronics* 9, no. 1: 89.
https://doi.org/10.3390/electronics9010089